CROSS REFERENCE TO RELATED APPLICATIONS

This continuation application claims the benefit of U.S. application Ser. No. 11/161,079, filed on Jul. 22, 2005 and included herein by reference.

BACKGROUND

The invention relates to a digital phase-locked loop (PLL), and more particularly, to a digital PLL having an auto-gain control.

In an optical disc drive, an EFM (Eight-to-Fourteen Modulation) signal read from a disc needs to be synchronized so that the EFM signal can be further processed. In general, the optical disc drive is operated under a CAV (Constant Angular Velocity) mode and therefore, a channel bit rate of the EFM signal varies as a pick-up head of the optical disc drive moves from an inner track to an outer track or from an outer track to an inner track of the disc. The channel bit rate variation appears in way of phase and frequency variations of the EFM signal. To track the channel bit rate variation of the EFM signal, a phase-locked loop (PLL) is used.

Please refer to FIG. 1. FIG. 1 is a block diagram of a conventional digital PLL circuit 100 used for tracking the EFM signal. The PLL circuit 100 includes a phase detector (PD) 110, a plurality of multipliers 120 and 130, a digital loop filter 140, and a digitally controlled oscillator (DCO) 150. As the pick-up head moves from one track to another track of a disc, phase and frequency characteristics of the EFM signal change, and a multiplier gain G₁of the multiplier 120 and a multiplier gain G₂of the multiplier 130 require adjustments in order to lock the EFM signal. As known to those skilled in this art, the multiplier gains G₁and G₂set in PLL circuit 100 are acquired from a predetermined lookup table. As the pick-up head moves, suitable settings of these gains G₁and G₂will be decided according to the predetermined lookup table.

In a preferred operating condition, utilizing the lookup table to perform a gain control of the multipliers 120 and 130 satisfies the needs of the optical disc drive under CAV mode. However, the pick-up head will fail to read the EFM signal if a disc was not initially recorded properly. Utilizing the lookup table is insufficient to compensate for this fault since the lookup table expects only phase and frequency variations due to a movement of the pick-up head. Therefore, no matter how many times a re-read operation of the disc is performed, the optical disc drive still fails to read the disc under the above condition.

SUMMARY

It is therefore one of the objectives of the claimed invention to provide a digital phase-locked loop (PLL) circuit having an auto-gain control and method thereof for an optical disc drive, to solve the above-mentioned problem.

The claimed invention provides a digital PLL system. The digital PLL system comprises a phase detector coupled to an input signal and a clock signal for generating a phase difference signal indicating a phase difference between the input signal and the clock signal; a first multiplier coupled to the phase detector for multiplying the phase difference signal by a first gain factor; a second multiplier coupled to the phase detector for multiplying the phase difference signal by a second gain factor; a digital loop filter coupled to the first multiplier and the second multiplier for providing an integral signal and a proportional signal according to outputs of the first multiplier and the second multiplier and for generating a control signal according to the integral signal and the proportional signal; a digitally controlled oscillator coupled to the digital loop filter for generating the clock signal according to the control signal; and an auto-gain control (AGC) unit coupled to the first multiplier, the second multiplier, and the digital loop filter. The AGC unit further comprises a first control unit for updating the first gain factor according to the integral signal; and a second control unit for updating the second gain factor according to the proportional signal.

The claimed invention provides a method for controlling a digital PLL system. The method includes generating a phase difference signal according to an input signal and a clock signal; multiplying the phase difference signal by a first gain factor through a first multiplier of the digital PLL system; multiplying the phase difference signal by a second gain factor through a second multiplier of the digital PLL system; performing digital loop filtering upon outputs of the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal; generating the clock signal according to the control signal through a digitally controlled oscillator of the digital PLL system; updating the first gain factor according to the integral signal; and updating the second gain factor according to the proportional signal.

The claimed invention further provides a digital PLL system. The digital PLL system comprises a phase detector coupled to an input signal and a clock signal for generating a phase difference signal indicating a phase difference between the input signal and the clock signal; a first multiplier coupled to the phase detector for multiplying the phase difference signal by a first gain factor; a second multiplier coupled to the phase detector for multiplying the phase difference signal by a second gain factor; a digital loop filter coupled to the first multiplier and the second multiplier for providing an integral signal and a proportional signal according to outputs of the first multiplier and the second multiplier and for generating a control signal according to the integral signal and the proportional signal; a digitally controlled oscillator coupled to the digital loop filter for generating the clock signal according to the control signal; and an auto-gain control (AGC) unit coupled to the first multiplier, the second multiplier, and the digital loop filter. The AGC unit further comprises a first control unit for updating the first gain factor according to the integral signal; and a second control unit for updating the second gain factor according to the phase difference signal.

The claimed invention provides a method for controlling a digital PLL system. The method includes generating a phase difference signal according to an input signal and a clock signal; multiplying the phase difference signal by a first gain factor through a first multiplier of the digital PLL system; multiplying the phase difference signal by a second gain factor through a second multiplier of the digital PLL system; performing digital loop filtering upon outputs of the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal; generating the clock signal according to the control signal through a digitally controlled oscillator of the digital PLL system; updating the first gain factor according to the integral signal; and updating the second gain factor according to the phase difference signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a conventional digital phase-locked loop circuit.

FIG. 2 is a block diagram of an auto-gain controlled digital phase-locked loop circuit according to a first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a control unit shown in FIG. 2.

FIG. 4 is a block diagram illustrating another control unit shown in FIG. 2.

FIG. 5 is a block diagram of an auto-gain controlled digital phase-locked loop circuit according to a second embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 is a block diagram of an auto-gain controlled digital phase-locked loop (PLL) circuit 200 according to a first embodiment of the present invention. As shown in FIG. 2, the PLL circuit 200 contains a phase detector (PD) 210, a plurality of multipliers 220 and 230, a digital loop filter 240, a digitally controlled oscillator (DCO) 250 and an auto-gain control (AGC) unit 260. The PD 210 detects a phase difference between an input signal S_iand a clock signal S_oto provide a phase difference signal S_i. The phase difference signal S_iis fed into the multipliers 220 and 230 simultaneously. The multiplier 220 multiplies the phase difference signal S_iby a first gain factor G₁to generate a weighted signal S₂. Similarly, the multiplier 230 multiplies the phase difference signal S₁by a second gain factor G₂to generate a weighted signal S₃. In this embodiment, the AGC unit 260 is used to adapt the first gain factor G₁and the second gain factor G₂. The weighted signals S₂and S₃are inputted to the digital loop filter 240 for generating a control signal S_c. The DCO 250 receives the control signal S_cand outputs the clock signal S_ohaving a frequency corresponding to the control signal S_c. The clock signal S_ois further fed back to the PD 210. Please note that, as is well known in the art, the PLL circuit 200 can further comprise a frequency divider coupled between the PD 210 and the DCO 250.

The operation of the digital loop filter 240 will now be described. The digital loop filter 240 comprises an integrator 242 and an adder 244. The weighted signal S₂, after being inputted to the digital loop filter 240, is identified as a proportional signal S₄within the digital loop filter 240. The integrator 242 integrates the weighted signal S₃to generate an integral signal S₅. The adder 244 adds the integral signal S₅and the proportional signal S₄to generate the control signal S_c.

In this embodiment, the AGC unit 260 comprises a plurality of control units 262 and 264. The control unit 262 receives the integral signal S₅in the digital loop filter 240 and adapts the first gain factor G₁according to the integral signal S₅. On the other hand, the control unit 264 receives the proportional signal S₄in the digital loop filter 240 and adapt the second gain factor G₂according to the proportional signal S₄.

Please refer to FIG. 3. FIG. 3 is a block diagram illustrating the control unit 262 shown in FIG. 2. As shown in FIG. 3, the control unit 262 comprises a differentiator 310, an absolute value calculator 320, a multiplier 330, and an adder 340. The control unit 262 updates the first gain factor G₁according to the following formula:
G₁=K₁Â·|S_v|+G₁*â€ƒâ€ƒ(1)
where S_v=dS₅/dt is a variation signal, G₁is the first gain factor, K₁is a first preset value; |S_v| is an absolute variation signal S_a1, and G₁* is a first preset minimal value.

The differentiator 310 receives the integral signal S₅and differentiates the integral signal S₅to provide the variation signal S_v. The variation signal S_vrepresents a frequency variation at a time instant and the first gain factor G₁is generated according to this calculated frequency variation. In this embodiment, the differentiator 310 is simplified to compute a difference between two successive values transmitted via the integral signal S₅, but this simplification is not meant to be a limitation of the present invention. The variation S_vis fed into the absolute value calculator 320 for generating the absolute variation signal S_a1according to the variation signal S_v. The absolute variation signal S_a1is generated by taking absolute value over the variation signal S_v. Therefore, a value transmitted by the absolute variation signal S_a1is an absolute value of a corresponding value transmitted by the variation signal S_v. The absolute variation signal S_a1is then multiplied by the first preset value K₁to generate a first difference signal S_d1. After adding the first preset minimal value G₁* to the first difference signal S_d1, the first gain factor G₁is generated and is updated accordingly. Please note that the above-mentioned preset minimal value is for providing the first gain factor G₁with a value related to a loop gain of the digital PLL 200. Further, since the operation of the multiplier 220 is equivalent to performing a scaling operation on the phase difference signal S₁, the gain factor G₁set to the multiplier 220 is always a positive number.

The control unit 264 generates the second gain factor G₂in a similar way as that for the control unit 262 to generate the first gain factor G₁. Please refer to FIG. 4. FIG. 4 is a block diagram illustrating the control unit 264 shown in FIG. 2. As shown in FIG. 4, the control unit 264 comprises an average unit 410, an absolute value calculator 420, a multiplier 430, and an adder 440. The control unit 264 updates the second gain factor G₂according to the following formula:
G₂=K₂Â·|S_av|+G₂*â€ƒâ€ƒ(2)
where S_av=(Î£_{m=nâˆ’N+1}ⁿS₄(m))/N, which acts like an a finite impulse response (FIR) low pass filter, is an averaged signal, G₂is the second gain factor, K₂is a second preset value, |S_av| is an absolute averaged signal S_a2, G₂* is a second preset minimal value and N is a window size of a sliding window. Besides employing the FIR filter, the other way to form the averaged signal S_avis to use an infinite impulse response (IIR) low pass filter. For example, the averaged signal S_avcan be obtained by calculating a running average of the proportional signal S₄.

The average unit 410 receives the proportional signal S₄and averages values transmitted by the proportional signal S₄over the sliding window to generate the averaged signal S_av. The averaged S_avis fed into the absolute value calculator 420 for generating the absolute averaged signal S_a2according to the averaged signal S_av. The absolute averaged signal S_a2is generated by taking absolute value over the averaged signal S_av. Therefore, a value transmitted by the absolute averaged signal S_a2is an absolute value of a corresponding value transmitted by the averaged signal S_av. Then, the absolute averaged signal S_a2is multiplied by the second preset value K₂to generate a second difference signal S_d2. After adding the second preset minimal value G₂* to the second difference signal S_d2, the second gain factor G₂is acquired and is updated iteratively. Please note that the above-mentioned second preset minimal value is a value related to a natural frequency of the digital PLL 200. Further, since the operation of the multiplier 230 is equivalent to performing a scaling operation on the phase difference signal S₁, a second multiplier gain is always a positive number.

Please refer to FIG. 5. FIG. 5 is a block diagram of an auto-gain controlled digital phase-locked loop circuit 500 according to a second embodiment of the present invention. The auto-gain controlled digital PLL circuit 500 is similar to the digital PLL circuit 200 shown in FIG. 2 except that the phase difference signal S₁, rather than the proportional signal S₄, is inputted to the control unit 564. In this embodiment, the second preset value K₂is modified to a suitable value to compensate for the fact that the inputted signal S₁of the control unit 564 is not multiplied by a gain through the multiplier 520. Since the components of the same name in digital phase-locked loop circuits 200 and 500 have the same operation and functionality, further description is omitted for brevity.

The present invention, when used in an optical disc drive, can replace a conventional gain control mechanism applied to a digital PLL circuit. In other words, a conventional lookup table for determining a multiplier gain of a multiplier in the digital PLL circuit can be eliminated, and an auto-gain controlled digital PLL circuit as mentioned above is adopted instead. On the other hand, the present invention can be an auxiliary for a conventional gain control mechanism of a digital PLL circuit. When an optical disc drive fails to read an EFM signal from a disc, the above-mentioned auto-gain controlled mechanism is capable of supporting the following re-reading procedure.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.