CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit under 35 U.S.C. Â§119(e) of U.S. Provisional Application entitled â€œMethod of Phasor Estimation at Predetermined Time Instantsâ€ , filed on Oct. 18, 2005, having Ser. No. 60/727,764, naming Gregary C. Zweigle, Armando Guzman-Casillas, and Luther Scott Anderson as inventors, the complete disclosure thereof being incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to monitoring, metering, protection and control of electrical systems, and more specifically, to an apparatus and method for estimating synchronized phasors at predetermined times referenced to an absolute time standard in an electrical system.

Knowledge of the state of an electrical network is important in order to recognize and understand disturbances in the electrical network, provide protection functionality, provide metering, monitor the electrical network, and determine control actions. This is especially true for critical electrical networks such as an electric power system or grid where energy is generated and transported from the generating facilities to locations and loads requiring the energy. Electrical power systems include a variety of power system elements such as electrical generators, electrical motors, power transformers, power transmission lines, buses and capacitors, to name a few. The electric power systems also include various monitoring devices, control devices, metering devices, and protective devices (e.g. protective relays). In most cases, these devices are microprocessor-based or â€œintelligentâ€ electronic devices (IEDs), that utilize phasors (i.e., a constant complex number representing a sinusoidal function of time) to perform their respective function(s). The phasors are derived from local or shared remote measurements sampled from currents and/or voltages of the electric power system.

Regardless of whether the phasors are derived from local or remote measurements, the accuracy of such measurements is of paramount importance when achieving a desired level of electrical power system performance. Such accuracy is predicated on both the accuracy of the measurement itself and the accuracy of the knowledge of the acquisition time of the measurement.

Acquisition time accuracy has been addressed via time-keeping systems that distribute highly accurate time, referenced to an absolute time standard, which have been used to drive the acquisition time of a voltage or current measurement. The absolute time standard typically includes one of the coordinated universal time (UTC) or international atomic time (TAI), distributed by the Global Positioning System (GPS) and then with a time protocol such as the Inter Range Instrumentation Group time code standard (IRIG) or over Ethernet. Systems employing absolute time reference schemes utilize voltage and/or current measurements that are sampled from analog voltage and/or current signal(s) with respect to the absolute time. As a result, both the measurement value and the time at which the measurement value is acquired can be obtained, processed, stored, and/or transported with high accuracy.

In applications such as power system state determination, it is desirable to sample voltage and/or current signals at many points across the electric power system at the same moment. In that case, using an absolute time standard, the voltages and/or current signals are sampled at a coordinated time instant to allow synchronization of the acquisition across the network. The resulting voltage and/or current measurements are processed to form â€œsynchronized phasorsâ€ which are then utilized to enable new applications for the monitoring, metering, protection, and control of the electric power generation, transmission, and distribution network of the electric power system. The synchronized phasors may also be stored for subsequent use in analyzing a fault or other anomalous electrical power system condition.

Real-time monitoring of the present state of the electrical power system is often accomplished using a state-estimation algorithm. In general, the state-estimation algorithm utilizes measured voltage and power measurements that are collected from monitored points or nodes in the electric power system. The measured quantities are then used to estimate the state of the electric power system. One inherent limitation of state-estimation algorithms however is the time delay introduced as a result of the estimation of the power system estate. It is therefore desirable to minimize the delay due to determination of the estimated state values, as well as any delay between the determination of the estimated state values and any subsequent control action (i.e. a control latency).

An electric power system utilizing the synchronized phasors can aid in reducing the control latency inherent in state-estimation algorithms. Because each synchronized phasor represents a present state value of the power system, derivation of estimated state values is not required, and the mechanisms which determine the control action are able to act more quickly. A further application for the use of synchronized phasors includes the dynamic or continuous recording of the variable electric power system magnitude and phase angle. Utilizing such a dynamic recording enables subsequent analysis of changes in the electric power system due to, for example, opening or closing a line, equilibrium differences between generation and load, or unstable power swings. A number of types of protection functions such as those found in protective relays may also benefit from the use of synchronized phasors. For example, synchronized phasors may be used to improve detection of the loss of electric power system synchronization when generators begin operation at different speeds. When the loss of synchronization is detected, a remedial action scheme can be quickly employed to â€œislandâ€ a portion(s) of the electric power system or shed a load.

As mentioned above, phasors are calculated from stepped-down analog voltage and current signals of the electric power system. When received from respective voltage and current transformers, the analog voltage and/or current signals are filtered, sampled with respect to the local power system frequency (e.g., 60 Hz) and processed to form phasors suitable for use by a microprocessor or other intelligent device. Synchronous phasors are similarly calculated except that they are sampled with respect to an absolute time standard and derived with respect to a coordinated time instant.

For example, one method of computing the synchronized phasor is described in U.S. Pat. Nos. 6,845,333 and 6,662,124 assigned to Schweitzer Engineering Laboratories, Inc. In one embodiment, the absolute time reference is generated via GPS, transmitting time and location information that is used by local receivers of the intelligent electronic devices. The acquisition may be based on deriving each sample instant from the absolute time reference, and recording the time at which the sample is taken.

To be meaningful, a synchronized phasor or phasor quantity must be referenced to a standard to allow correlation to other synchronized phasors even when the synchronized phasors are acquired from multiple electric power system locations with varying states and frequencies. One method known in the art that may be used to reference a synchronized phasor includes correlating an associated sampled voltage or current signal to a phasor with a frequency equal to the nominal power system frequency and with a predetermined phase that has been set in all of the IEDs or measuring devices. Alternatively, a single analog quantity can be chosen as the reference for all IEDs communicating and sharing the synchronized phasors. For example, the frequency at one point in the distribution scheme is sometimes chosen as a reference for all devices computing synchronized phasors. In some cases a feature of a reference signal, such as a zero crossing, can provide the reference for the phase value.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the invention, an apparatus estimates a plurality of synchronized phasors at predetermined times referenced to an absolute time standard in an electrical power system. The apparatus includes a sample controller configured to determine a frequency of a power system signal acquired at each location of the electrical power system where the synchronized phasors are calculated, a sampling means configured to sample the power system signal at a sampling interval rate based on a frequency of the power system signal to form a plurality of signal samples, a time controller configured to generate a plurality of acquisition time values based on an occurrence of each of the plurality signal samples at a corresponding plurality of different times referenced to the absolute time standard. Each of the plurality of acquisition time values is associated with a phasor magnitude and a phasor phase angle derived from each of the plurality of signal samples. The apparatus also includes a phasor estimator configured to adjust the phasor magnitude and the phasor phase angle for each of the plurality of signal samples based on a time difference between a corresponding selected acquisition time value of the plurality of acquisition time values and a predetermined time of the predetermined times referenced to the absolute time standard to form the plurality of synchronized phasors.

In accordance with another embodiment of the invention, a method estimates a plurality of synchronized phasors at predetermined times referenced to an absolute time standard in an electrical power system. The method includes acquiring a power system signal at a location of the electrical power system, determining a frequency of the power system signal, sampling the power system signal at a sampling interval rate based on a frequency of the power system signal to form a plurality of signal samples, and generating a plurality of acquisition time values based on an occurrence of each of the plurality signal samples at a corresponding plurality of different times referenced to the absolute time standard. Each of the plurality of acquisition time values is associated with a phasor magnitude and a phasor phase angle derived from each of the plurality of signal samples. For each of the plurality of signal samples, the method further includes adjusting the phasor magnitude and the phasor phase angle based on a time difference between a corresponding selected acquisition time value of the plurality of acquisition time values and a predetermined time of the predetermined times referenced to the absolute time standard to form the plurality of synchronized phasors. According to one aspect of the invention, the location of the power system is local and the power system signal is a local analog input signal. According to another aspect of the invention, the location of the power system is remote and the power system signal is a digitized remote analog input signal.

In accordance with a further embodiment of the invention, a method estimates a plurality of synchronized phasors at predetermined times referenced to an absolute time standard in an electrical power system. The method includes acquiring a power system signal at a location of the electrical power system, determining a frequency of the power system signal, sampling the power system signal at a sampling interval rate based on a frequency of the power system signal to form a plurality of signal samples, and generating a plurality of acquisition time values based on an occurrence of each of the plurality signal samples at a corresponding plurality of different times referenced to the absolute time standard, each of the plurality of acquisition time values associated with a phasor magnitude and a phasor phase angle derived from each of the plurality of signal samples. For each of the plurality of signal samples, the method further includes interpolating the phasor magnitude and rotating phasor phase angle to form a corresponding plurality of referenced phasor magnitudes and referenced phasor phase angles of the plurality of synchronized phasors based on a time difference between a corresponding selected acquisition time value of the plurality of acquisition time values and a predetermined time of the predetermined times referenced to the absolute time standard.

It should be understood that the present invention includes a number of different aspects and/or features which may have utility alone and/or in combination with other aspects or features. Accordingly, this summary is not an exhaustive identification of each such aspect or feature that is now or may hereafter be claimed, but represents an overview of certain aspects of the present invention to assist in understanding the more detailed description that follows. The scope of the invention is not limited to the specific embodiments described below, but is set forth in the claims now or hereafter filed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a single line schematic of a power system that may be utilized in a typical wide area network.

FIG. 2 is a block diagram of the power system and the IED of FIG. 1 in conjunction with a time source configured to deliver an absolute time, according to an embodiment of the invention.

FIG. 3 is a functional block diagram of the IED of FIG. 1, according to an embodiment of the invention.

FIG. 4 is a functional block diagram of the phasor estimation of FIG. 3, according to an embodiment of the invention.

FIG. 5 is an exemplary timeline illustrating the relationship between the selected acquisition time values T_a, T_b, T_c. . . , the acquisition time values T₁, T₂, T₃, . . . and the predetermined times t₁, t₂, t₃. . . referenced to an absolute time standard of the phasor estimation of FIG. 4, according to an embodiment of the invention.

FIG. 6A is a functional block diagram of an exemplary phasor adjustment block of FIG. 4, according to an embodiment of the invention.

FIG. 6B is a functional block diagram of another exemplary phasor adjustment block of FIG. 4, according to an embodiment of the invention.

FIG. 7 is a functional block diagram of another IED of FIG. 1 that may be used in conjunction with remote acquisition devices, according to an embodiment of the invention.

FIG. 8 is a functional block diagram of yet another IED of FIG. 1, according to an embodiment of the invention.

FIG. 9 is a functional block diagram of a phasor estimation of FIG. 8, according to an embodiment of the invention.

FIG. 10 is a functional block diagram of an exemplary interpolate block of the phasor estimation of FIG. 9, according to an embodiment of the invention.

FIG. 11 is a functional block diagram of a correct block of FIG. 8, according to an embodiment of the invention.

FIG. 12 is a functional block diagram of yet another IED of FIG. 1, according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In contrast to existing systems, the present invention provides a calculation of synchronized phasors at predetermined times referenced to an absolute time standard, in a manner that eliminates the need for further time alignment, and allowing correlation to all synchronized phasors in the system, even when they are acquired from multiple electric power system locations with varying states and differing frequencies. The sampling interval rate is variable, based on the varying frequency of the local power system signal and can furthermore be based on an exact multiple of the frequency of the local power system signal. No corrections for frequency deviations are required. It provides synchronized phasors which are further processed for power system protection applications requiring sampling intervals also based on a multiple of the local power system frequency. It does not require sampling to be synchronized or based on the same frequency between measuring devices (e.g. IEDs) which are estimating the synchronized phasors. Control of the sampling interval is not based on an absolute time reference. The invention is simple in implementation and is computationally inexpensive. It allows the predetermined absolute time reference moment to be uniformly determined between the IEDs utilizing the phasors, or to be independently locally determined. It provides for the synchronized phasors to be referenced to a phasor of predetermined phase and frequency. Applications can provide signals for protection, monitoring, recording, metering, control, analyzing, or further processing due to the absolute time reference moment providing a common scale against which the signals can be compared.

FIG. 1 is a single line schematic diagram of a power system 10 that may be utilized in a typical wide area. As illustrated in FIG. 1, the power system 10 includes, among other things, three synchronous generators 11, 12 and 13, configured to generate three-phase sinusoidal waveforms such as 12 kV sinusoidal waveforms, three step-up power transformers 14a, 14b and 14c, configured to increase the generated waveforms to a higher voltage sinusoidal waveforms such as 138 kV sinusoidal waveforms and a number of circuit breakers 18. The step-up power transformers 14a, 14b, 14c operate to provide the higher voltage sinusoidal waveforms to a number of long distance transmission lines such as the transmission lines 20a, 20b, 20c and 20d. In an embodiment, a first substation 16 may be defined to include the two synchronous generators 11 and 12, the two step-up power transformers 14a and 14b and associated circuit breakers 18, all interconnected via a first bus 19. A second substation 35 may be defined to include the synchronous generator 13, the step-up power transformer 14c and associated circuit breakers 18, all interconnected via a second bus 25. At the end of the long distance transmission lines 20a, 20b, a third substation 22 may be defined to include two step-down power transformers 24a and 24b configured to transform the higher voltage sinusoidal waveforms to lower voltage sinusoidal waveforms (e.g., 15 kV) suitable for distribution via one or more distribution lines 26 to loads such as a load 32. The second substation 35 also includes two step-down power transformers 24c and 24d to transform the higher voltage sinusoidal waveforms, received via the second bus 25, to lower voltage sinusoidal waveforms suitable for use by respective loads 30 and 34.

A number of intelligent electronic devices (IED) are connected at various points in the electric power system 10. For ease of discussion however, only one IED 100 is shown operatively connected to the transmission line 20b via a one transformer. In general, an IED can be configured to perform one or more of power system protection (e.g., a line current differential protection), automation (e.g., reclosing a circuit breaker), control (e.g., capacitor bank switching) and metering (e.g., power consumption calculation).

FIG. 2 is a block diagram of the power system 10 and the IED 100 in conjunction with a time source 108 configured to deliver an absolute time to the IED 100. FIG. 2 also includes a second IED 110 and a monitoring and control system 112 operatively coupled the IED 100 via a communications network 107. The network 107 may be any suitable network adapted to enable transmission between the various interconnected devices of FIG. 2. For example, the network 107 may be configured as an Ethernet based local area network or wide area network, etc., and may include a number of universal asynchronous receiver transmitters. The monitoring and control system 112 is configured to, among other things, provide SCADA (Supervisory Control and Data Acquisition) and EMS (Energy Management System) functions by applying synchrophasor information received from additional devices of the power system 10.

As discussed below in connection with a number of figures, the IED 100 is configured to estimate synchronized phasors at predetermined time instants that are based on an absolute time reference and, in some embodiments, referencing to a phasor with predetermined phase and frequency. Referring to FIG. 2, the IED 100 has an input configured to receive an input analog signal 102, and a bidirectional signal configured to provide a system control signal 104 to the power system 10 (e.g., a signal to the open circuit breaker 18 to isolate a portion of the first substation 16 from the remainder of the power system 10). The system control signal 104 may also provide control information to IED 100. The input analog signal 102, which may be representative of one or more local voltages (e.g., an A-phase to ground voltage, B-phase to ground voltage and a C-phase to ground voltage) and/or one or more local currents (e.g., an A-phase current, B-phase current and C-phase current), is received by IED 100 via voltage and/or current transformers connected to one or more phases of the power system 10. Alternatively, the input analog signal 102 may be representative of a remote voltage and/or a current signal received by the IED 100 from a remote acquisition device monitoring the power system 10.

A time source 108 provides an absolute time reference 101 to the IED 100 where the absolute time 101 is a synchronized to an absolute time standard such as UTC, and distributed using GPS, preferably formatted in an Inter Range Instrumentation Group time code standard (IRIG) signal for receipt by IED 100. Additional formats, distribution schemes, and time standards may also be utilized.

In general, the input analog signal 102 received from the power system 10 is filtered, multiplexed, sampled and digitized to form a signal of analog instantaneous samples suitable for use by a microcontroller 103 of the IED 100. In one embodiment, the microcontroller 103 includes a CPU, or a microprocessor, a program memory (e.g., a Flash EPROM) and a parameter memory (e.g., an EEPROM). As will be appreciated by those skilled in the art, other suitable microcontroller configurations may be utilized. Further, although discussed in terms of the microcontroller 103, it should be noted that the embodiments presented and claimed herein may be practiced using an FPGA or other equivalent.

Depending on the IED 100 configuration, the microcontroller 103 executes a protection function and/or an automation function and/or a control function and/or a metering function. Further, the microprocessor 103 executes a computer program or control logic scheme to estimate the synchronized phasors 111 at predetermined times referenced to an absolute time standard, discussed below in connection with FIGS. 3-11, according to an embodiment of the invention. For ease of discussion, the computer program or control logic scheme to estimate synchronized phasors is referred to herein as a synchronized phasor estimation method that may or may not be in addition to a protection function and/or an automation function and/or a control function and/or a metering function of the IED 100.

FIG. 3 is a functional block diagram of the IED 100, according to an embodiment of the invention. Although discussed as functional blocks, it should be understood that the IED 100 may be implemented in hardware, software, firmware or a combination thereof. Referring to FIG. 3, the IED 100 includes an analog filter 140 having an input for receiving the input analog signal 102 and an output for providing a filtered analog instantaneous signal 142 to an analog-to-digital converter (ADC) 144. When received by the ADC 144, the filtered analog instantaneous signal 142 is sampled at a rate determined by a frequency of the input analog signal 102 to generate a sampled analog instantaneous signal 146. The series of filtered signal samples representative of the filtered analog instantaneous signal 142 can be generated at a frequency associated with an integer multiple of the input analog signal 102.

The IED 100 also includes a digital filter 148 having an input for receiving the sampled analog instantaneous signal 146. In operation, the digital filter 148 rejects unwanted signal characteristics such as harmonic distortion, thermal noise, and exponentially decaying DC offsets, from the sampled analog instantaneous signal 146 in order to provide a filtered signal 150 via its output. The filtered signal 150 represents digitized, filtered instantaneous samples of the input analog signal 102, where the instantaneous samples of the input analog signal 102 are taken at a frequency of the input analog signal 102. A typical impulse response of the digital filter 148 is a full-cycle cosine waveform response or a half-cycle cosine waveform response.

The filtered signal 150 is provided to a phasor calculator 152 where a series of instantaneous phasors 154 are calculated based on the filtered signal 150. Although not separately illustrated, the phasor calculator 152 may include a 90 degree phase shift function in order to provide a quadrature representation suitable for the calculation of magnitudes and phase angles. As noted above, for ease of subsequent calculations by the microcontroller 103, each of the instantaneous phasors 154 is expressed in polar coordinate form to include an instantaneous phasor magnitude 154a and an instantaneous phasor phase angle 154b. Alternatively, a representation as a complex value may be utilized, depending on the nature of the IED function 156. In this case each of the instantaneous phasors 154 is expressed as an instantaneous phasor real component 154a and an instantaneous phasor imaginary component 154b. For ease of discussion, both versions, the magnitude and phase combination and the real part imaginary part combination, are referred to herein as an instantaneous phasor, or in general as a phasor. The instantaneous phasor phase angle 154b is referenced to, for example, (one of the input analog signal(s) 102. The phasor calculator 152 may also include calculation of sequence values such as positive sequence, negative sequence, or zero sequence. These additional quantities may also be part of instantaneous phasors 154.

An IED function 156 is configured to receive the instantaneous phasors 154, and utilizing an algorithm or equivalent, perform the appropriate IED function (e.g., protection, automation, control, metering) to determine a status of the power system 10. Based on the determined status, the system control signal 104 is provided to the power system 10, other IEDs, etc. The system control signal 104 may be transmitted directly to an actuating device associated with the IED 100, or may be transmitted via the network 107 where it is coordinated with other control signals for further decoding and processing by a remote actuating device. The IED function 156 is also configured to utilize the synchronized phasors 111 to perform power system functions, such as causing a breaker to trip. The IED function 156 may also include a link to the network 107 in order to transmit and receive various data related to protection, monitoring, automation and control, and to receive synchronized phasors 111 from other IEDs coupled to the power system 10.

In addition to the signal processing functions described above, the IED 100 includes a sample controller 160 having an input for receiving the filtered analog instantaneous signal 142. The sample controller 160 also includes two outputs; a first output for providing a control signal stream 162 to the ADC 144 and a time controller 166, and a second output configured to provide a local frequency 164 to a phasor estimation 200. The sample controller 160 has no control input based on the absolute time 101 and therefore does not provide a control signal stream 162 to the ADC 144 based on the absolute time 101.

The local frequency 164 is representative of a frequency (e.g., 60.2 Hz) of the input analog signal 102. In one embodiment, the local frequency 164 is derived from the filtered analog instantaneous signal 142 using one of any number of well-known methods. For example, an interval between two or more zero crossings of the filtered analog instantaneous signal 142 may be measured as a sinusoidal period. The interval(s) between the zero crossings can be filtered to reduce noise, harmonics and other undesirable distortions. The local frequency 164 may then be calculated as a reciprocal of the sinusoidal period. The local frequency 164 may also be derived from one of the filtered analog instantaneous signal 142, the input analog signal 102, the sampled analog instantaneous signal 146, the filtered signal 150 and/or the instantaneous phasors 154.

After deriving the local frequency 164, an equal number of integer samples instants may be placed within each period to provide a basis for the control signal stream 162. For example, each period may include 8 sampling instants yielding nominally 480 sampling instants of the filtered analog instantaneous signal 142 per second for a local frequency of 60 Hz. Thus, sampling instants of the control signal stream 162 are based on the local frequency.

In one embodiment the sample controller 160 operates to generate a series of the sampling instants at the local sampling interval rate, herein referred to as the control signal stream 162, where the sampling instants are an integer number multiple of the frequency of the input analog signal 102. As will appreciated by one skilled in the art, the sampling instants may be based on other multiples of the frequency of the input analog signal 102. For ease of discussion, the control signal stream 162 may be viewed as a pulse train of sampling instants. In general however, the control signal stream 162 may be configured in one of any number of signal configurations adapted to control analog multiplexers, gain circuits, sample and hold switches, programmable logic, and other devices.

In addition to receiving the control signal stream 162, the time controller 166 includes an input for receiving the absolute time 101. As described above, the absolute time 101 is a time referenced to an absolute time standard and communicated via a protocol such as IRIG. The time controller 166 utilizes the absolute time 101 to generate a series of instantaneous time values 168 where each is denoted as T. Each instantaneous time value 168 is representative of one decoded instant of the absolute time 101, and is updated periodically (e.g., once per second), depending on the absolute time standard and the nature of the implementation.

For example, if the absolute time 101 is formatted in using an IRIG-B protocol, a single bit stream of 100 pulses per second is transmitted. This means that 100 bits of information, representing one data frame of time information, are transmitted every second. Each one-second data frame contains information about the day of the year (1-366), hours, minutes, and seconds (e.g., Aug. 17, 2005 at 4:13.000000 PM). Accordingly, in one embodiment, the instantaneous time value 168 is representative of one decoded instant of the absolute time 101, and is updated once per second.

Using the time information provided by the absolute time 101, the time controller 166 also monitors the control signal stream 162 to form the acquisition time value stream 170 having a series of acquisition time values denoted as T₁, T₂, T₃, . . . . Each acquisition time value is associated with one sampling instant of the analog input signal and is therefore associated with one instantaneous phasor magnitude 154a and one instantaneous phasor phase angle 154b.

For example, if the control signal stream 162 is a series of pulses where the leading edge of each pulse represents the beginning of one ADC operation of the filtered analog instantaneous signal 142, the acquisition time value stream 170 may be a series of time values coinciding with the time of the leading edge of each pulse, yielding an acquisition time value stream 170 having a number of acquisition time values per second as determined by the local frequency 164. Thus the acquisition time value T₂may occur approximately 2 milliseconds (ms) after the acquisition time value T₁, the acquisition time value T₃may occur approximately 2 ms after the acquisition time value T₂or approximately 4 ms after the acquisition time value T₁, the acquisition time value T₄may occur approximately 2 ms after the acquisition time value T₃or approximately 6 ms after the acquisition time value T₁, and so on, and each acquisition time values encodes the value of the sampling instant of the filtered analog instantaneous signal. Depending on the phase relationship between the sampling instants of the control signal stream 162 and the absolute time 101, a time offset from the absolute time 101 may be used to express each of the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170. In this case, the time controller 166 may record the interval from the absolute time 101 to the time of a next control signal stream 162 pulse, and then add this recorded interval to the absolute time 101 to generate each of the acquisition time values T₁, T₂, T₃, . . . of the acquisition time stream 170.

In general, the phasor estimation 200 is configured to generate synchronized phasors 111 indicative of the input analog signal 102. The synchronized phasors 111 are magnitude adjusted and phase-aligned to the absolute time 101, and in some embodiments further phase aligned to reference to a phasor with predetermined phase and frequency. FIG. 4 is a functional block diagram of the phasor estimation 200, according to an embodiment of the invention. The phasor estimation 200 operates to generate the synchronized phasors 111 in response to receipt of a series of the instantaneous phasor magnitudes 154a, a corresponding series of instantaneous phasor phase angles 154b, the local frequency 164, the instantaneous time values 168 and the acquisition time value stream 170. Although described as functional blocks, it should be understood that the phasor estimation 200 may be implemented in hardware, software, firmware or a combination thereof.

Referring to FIG. 4, the phasor estimation 200 includes a generate predetermined time function 202 and a phasor adjustment block 214 operatively coupled to the generate predetermined time function 202. The generate predetermined time function 202 has a first input for receiving the instantaneous time values 168 T and a second input for receiving the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170. The phasor estimation 200 also has a first output for providing predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a. The predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a may be a result of synchronization across all or a portion of the power system 10 (e.g., synchronized phasors), or may be specific to the IED 100, therefore generated and used locally only, depending on the desired application of the synchronized phasors 111. In any case, the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a are the desired time values at which the magnitudes and phase angles of the synchronized phasors 111 are to be estimated from the magnitudes and phase angles of phasors calculated at known times (e.g., the acquisition time values T₁, T₂, T₃, . . . ).

The generate predetermined time function 202 further has a second output for providing a time value pair stream 206 configured as a series of pairs of corresponding time values to the phase adjustment block 214. Each of the corresponding time value pairs includes one predetermined time referenced to the absolute time standard 111a and a corresponding selected acquisition time value from a series of selected acquisition time values T_a, T_b, T_c. . . . Each of the selected acquisition time values T_a, T_b, T_c. . . corresponds to one of the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170, such that the selected acquisition time values T_a, T_b, T_c. . . are a subset of the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170.

For example, in one implementation T_a=T₄, T_b=T₂₅₄, T_c=T₅₀₄, and so on, depending on the occurrence of the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a with respect to the occurrence of the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170.

In summary, each of the selected acquisition time values T_a, T_b, T_c. . . corresponds to one of the acquisition value T₁, T₂, T₃, . . . of the acquisition time value stream 170 that directly precedes an occurrence of one of the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a. FIG. 5 is an exemplary timeline 250 illustrating the relationship between the series of selected acquisition time values T_a, T_b, T_c. . . , the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170 and the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a of the phasor estimation 200. As shown in FIG. 5, the instantaneous time values T are selected to occur once every second, the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a are selected to occur every 250 ms and the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170 occur approximately every 2 1/12 ms (based on 8 sampling instants per period of a local frequency of 60 Hz), however other time intervals are possible.

Recall that, each acquisition time value T₁, T₂, T₃, . . . correlates to the control signal stream 162 which, in one embodiment, correlates to an integer multiple of the frequency of the input analog signal 102. Referring to FIG. 5, upon an occurrence of a predetermined time of the predetermined times t₁, t₂, t₃. . . , for example, the predetermined time t₁, an acquisition time value T₁, T₂, T₃, . . . of the acquisition time value stream 170 immediately preceding the predetermined time t₁, for example, the acquisition time value T₄, is assigned a selected acquisition time value, for example T_a, and so on. In this example, the predetermined time t₁and the selected acquisition time value T_aform a corresponding time value pair t₁, T_aof the time value pair stream 206. The corresponding time value pair, for example t₁, T_a, is then forwarded to the phasor adjustment block 214. Similarly, the corresponding time value pair t₂, T_b, the time value pair t₃, T_cand so on are forwarded to the phasor adjustment block 214 as they are generated.

As discussed above, each acquisition time value T₁, T₂, T₃, . . . of the acquisition time value stream 170 is associated with an instantaneous phasor magnitude 154a and an instantaneous phasor phase angle 154b. As a result of being derived from one acquisition time value T₁, T₂, T₃, . . . , each of the selected acquisition time values T_a, T_b, T_c. . . correspond to one instantaneous phasor magnitude 154a and one instantaneous phasor phase angle 154b.

Referring again to FIG. 4, phasor adjustment block 214 is configured to adjust or realign the instantaneous phasor magnitude 154a and the instantaneous phasor phase angle 154b in order to generate the synchronized phasor 111, shown as referenced phasor magnitude stream 111b and referenced phasor phase angle stream 111c or 111d, suitable for use, for example, in the protection function 156. In general, the instantaneous phasor magnitude 154a and the instantaneous phasor phase angle 154b of the instantaneous phasor 154 occurring at the time of one of the acquisition time value T₁, T₂, T₃, . . . is adjusted such that the resulting magnitude and phase angle are equal to a magnitude and phase angle of an equivalent phasor occurring at the time of the next occurring predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a. As noted above, the phase angle of the synchronized phasor 111 may further be referenced to a phasor of predetermined phase and frequency in order to compare to other similarly generated referenced phasors.

More specifically, the generate predetermined time function 202 generates an acquisition time value control signal 208 that operates to enable selected receipt of the instantaneous phasor magnitude 154a by an interpolate function of the phasor adjustment block 214, and to enable selected receipt of the instantaneous phasor phase angle 154b by a rotate block of the phasor adjustment block 214. Selected receipt is enabled upon an occurrence of each of the selected acquisition time values T_a, T_b, T_c. . . . Although illustrated as causing a switching action, the acquisition time value control signal 208 may cause any suitable action that selectively enables the instantaneous phasor magnitude 154a and the instantaneous phasor phase angle 154b to be provided to the phasor adjustment block 214 upon an occurrence of a selected acquisition time value of the series of selected acquisition time values T_a, T_b, T_{c . . . .}

Referring again to FIG. 5, a magnitude line 260 illustrates a series of instantaneous phasor magnitudes 154a (represented as dots) where each of the series of instantaneous phasor magnitudes 154a corresponds to an occurrence of an acquisition time value T₁, T₂, T₃, . . . . Similarly, a phase angle line 262 is aligned to the magnitude line 260 to illustrate a series of instantaneous phasor phase angle 154b (represented as dots) where each of the series of instantaneous phasor phase angles 154b corresponds to an occurrence of an acquisition time value. T₁, T₂, T₃, . . . .

For example, an instantaneous phasor magnitude 154a occurring at the acquisition time value T₁is denoted as X_M(T₁) 264 while an instantaneous phasor phase angle 154b occurring at the acquisition time value T₁is denoted as X_A(T₁) 266. Similarly, directly preceding the predetermined time t₁, an instantaneous phasor magnitude 154a occurring at the acquisition time value T₄=T_a271 is denoted as X_M(T_a) 268 while an instantaneous phasor phase angle 154b occurring at the acquisition time value T₄=T_ais denoted as X_A(T_a) 270. It should be noted that in FIG. 5, the relationship of T₄=T_aand T₅=T_a+dT with respect to t₁is used for illustrative purposes and that other alignments to t₁are possible depending on the IED 100 implementation.

The synchronized phasor 111, derived at the predetermined time t₁, may be similarly illustrated in FIG. 5 as a referenced phasor magnitude X_M(t₁) of a referenced phasor magnitude stream 111b denoted as X_M(t₁, t₂, t₃, . . . ), and a referenced phasor phase angle X_A(t₁) of a referenced phasor phase angle stream 111c denoted as X_A(t₁, t₂, t₃, . . . ).

In one embodiment, the phase angles of the referenced phasor phase angle stream 111c are further processed to reference them to a phasor with predetermined phase and frequency. By subtracting a phase angle associated with fixed frequency reference phasor having a pre-selected reference frequency (e.g., 60.0 Hz) from each of the phase angles (e.g., for a system instantaneously at 60.2 Hz) of the referenced phasor phase angle stream 111c, the resulting phase angles are referenced to a phasor with predetermined phase and frequency to form an adjusted referenced phasor phase angle stream 111d. In other words, each referenced phasor phase angle can be further processed to remove a fixed frequency such that a resulting adjusted referenced phasor phase angle is estimated with respect to an associated time t₁, t₂, t₃. . . referenced to the absolute time standard 111a and a phasor with predetermined phase and frequency.

In the illustrated example of FIG. 5, a fixed frequency reference phasor line 265 is shown. Prior to referencing to a phasor with predetermined phase and frequency 265, a referenced phasor phase angle is located at the intersection of the phase angle line 262 and a bisecting line corresponding to the time value t₁, and is denoted as X_A(t₁) 111c. Subsequent to referencing to a phasor with predetermined phase and frequency, the fixed frequency 265 is subtracted from the referenced phasor phase angle, resulting in an adjusted referenced phasor angle denoted as X_A(t₁)_ADJ111c. The subtraction is performed modulo the phase angle range of the referenced phasor phase angle 111c. For example, if the referenced phasor phase angle 111c is in range zero to 360 degrees, then the subtraction is computed modulo 360.

If the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a are chosen appropriately to the time instants when the reference phasor with predetermined phase and frequency is at zero degrees, then the conversion to the phasor with predetermined phase and frequency is accomplished without further processing. This is due to the fact that the subtraction operation is always subtracting a value of zero and therefore does not need to be explicitly computed.

FIG. 6A is a functional block diagram of an exemplary phasor adjustment block 214, according to an embodiment of the invention. In the exemplary phasor adjusted block of FIG. 6A, each resulting synchronized phasor includes a predetermined time t₁, t₂, t₃. . . referenced to the absolute time standard 111a, a referenced phasor magnitude of the referenced phasor magnitude stream 111b and an adjusted referenced phasor phase angle of the adjusted referenced phasor phase angle stream 111d. Although illustrated using a number of multipliers, adders, and operators as described below, it is contemplated that the phasor adjustment block 214 may be implement in one of any number of ways to provide interpolation of the instantaneous phasor magnitude 154a and rotation of the instantaneous phasor phase angle 154b to form the referenced phasor magnitude 111b and the referenced phasor phase angle 111c of the synchronized phasor 111.

Referring to FIGS. 5 and 6A, the phasor adjustment block 214 includes a first adder 302 configured to subtract the instantaneous phasor magnitude at the selected acquisition time value X_A(T_a) 268 from the next instantaneous phasor magnitude at the selected acquisition time value X_M(T_a+dT) 284 to generate a phasor magnitude difference 301, where T_a+dT represents the time of the next acquisition time value following the selected acquisition time value T_a. Note that the selected acquisition time value X_M(T_a+dT) 284 is simply available from the series of instantaneous phasor magnitudes 154a and does not imply anticausal processing. The phasor magnitude difference 301 represents a difference in the magnitude between two sequential instantaneous phasor magnitudes. The phasor adjustment block 214 also includes a second adder 308 configured to subtract the selected acquisition time value T_aof the series of selected acquisition time values T_a, T_b, T_c. . . . from the predetermined time t₁referenced to an absolute time standard 111a in order to generate a time value difference 310. The phasor adjustment block 214 further includes a divider 306 configured to divide the time value difference 310 by an acquisition time value delta dT 274 to generate a first proportionality factor 307. The time value difference 310 represents the difference in time from the selected acquisition time value T_a271 to the time value referenced to an absolute time standard t₁, and the acquisition time value delta dT 274 represents a time between the sampling instants of the control signal stream 162 provided by the sample controller 160. A first multiplier 304 is configured to multiply the phasor magnitude difference 301 by the first proportionality factor 307 to generate an intermediate magnitude difference signal 305.

The phasor adjustment block 214 further includes a third adder 328 configured to add the instantaneous phasor magnitude at the selected acquisition time value X_M(T_a) 268 to the intermediate magnitude difference signal 305 to form an uncalibrated referenced phasor magnitude 311. A first operator 312 and a second operator 316 are also included in the phasor adjustment block 214. The first operator 312 is configured to multiply the local frequency 164 by the time value difference 310, followed by conversion from unity units to phase angle units by multiplication with a constant value representative of the conversion factor, to form a second proportionality factor 313. The second operator 316 is configured to multiply a fixed frequency 324 of the phasor with predetermined phase and frequency by the predetermined time value t₁referenced to an absolute time standard 111a, followed similarly by unit conversion to generate a third proportionality factor 309. The second operator 316 uses the fact that phase values remain within a fixed range (e.g. zero to 360 degrees) to convert the predetermined time value t₁referenced to an absolute time standard 111a to a small range of values prior to multiplication. For example, if the phasor with predetermined phase and frequency is chosen such that the phase is always equal to zero at each exact multiple of one second, according to the absolute time standard, then the predetermined time value t₁referenced to an absolute time standard 111a can be converted to a range of zero to one second prior to multiplication by fixed frequency 324. To convert the range for this example, simply remove the rest of the time information, according to the representation of the predetermined time value t₁referenced to an absolute time standard 111a, for example the year, day, hours, and minutes information can be removed, along with subtracting an integer number of seconds from the predetermined time value t₁referenced to an absolute time standard 111a so that the resulting range is zero to one second.

The phasor adjustment block 214 also includes a third and a fourth operator 314 and 318, where the third operator 314 is configured to add the instantaneous phasor phase angle at the selected acquisition time value X_A(T_a) 270 to the second proportionality factor 313, followed by modulo conversion to the desired phase angle range, to form a pre-aligned referenced phasor 315. The fourth operator 318 is configured to add the pre-aligned referenced phasor 315 to the third proportionality factor 309, followed by modulo conversion to the desired phase angle range to form an adjusted uncalibrated referenced phasor phase angle 319.

Implementation magnitude distortion can be approximated and removed via a Mag Implement Correction 330 configured to receive the local frequency 164 and remove any implementation distortion to form a magnitude correction factor 321 using one of a number of techniques. Such implementation distortion may be introduced via IED components such as the analog filter 140 distorting the filtered analog instantaneous signal 142 with gain compression as a function of the local frequency. This is because each filter has a specific magnitude and phase response which varies as a function of the frequency content of the signal upon which it acts. It is not the purpose of Mag Implement Correction 330 to correct for off-nominal sampling errors. This is because the invention samples as a function of the varying frequency of the local signal (e.g. input analog signal 102) and therefore does not require corrections to compensate for sampling at a rate different than the local signal, such as fixed rates or rates based on the absolute time reference. One technique that may be employed by the Mag Implement Correction 330 includes use of a look-up table containing the distortion compensating values as a function of the instantaneous phasor magnitude 154a. Furthermore, the compensation can be included with the interpolation operation by further adjusting the time value referenced to an absolute time standard according to the amount of effective time shift required to compensate for phase shifts of the, for example, analog filter 140.

Similarly, phase angle distortion or shift can be approximated and removed via an Angle Implement Correction 332 configured to receive the local frequency 164 and remove any implementation distortion to form a phase correction factor 317, using one of a number of techniques. Such implementation distortion may be caused by phase shifts introduced by IED components such as the analog filter 140. It is not the purpose of Angle Implement Correction 332 to correct for off-nominal sampling errors. This is because the invention samples as a function of the varying frequency of the local signal (e.g. input analog signal 102) and therefore does not require corrections to compensate for sampling at a rate different than the local signal, such as fixed rates or rates based on the absolute time reference. One technique that may be employed by the Angle Implement Correction 332 includes use of a pre-selected constant or a parameter such as a look-up table containing the distortion compensating values as a function of the instantaneous phasor magnitude 154a.

A second multiplier of the phasor adjustment block 214 is configured to multiply the uncalibrated referenced phasor magnitude 311 with the magnitude correction factor 321 to form the referenced phasor magnitude X_M(t₁) of the referenced phasor magnitude stream 111b. Similarly, a fifth operator 322 of the phasor adjustment block 214 is configured to add the adjusted uncalibrated referenced phasor phase angle 319 to the phase correction factor 317 to form the adjusted referenced phasor phase angle X_M(t₁)_ADJof the adjusted referenced phasor phase angle stream 111d. In this way, synchronized phasors 111 are estimated at predetermined times referenced to the absolute time standard in an electrical system and referenced to a phasor with predetermined phase and frequency.

In an alternate embodiment, the Phasor Estimation 200 can use selected acquisition time values T_a, T_b, T_c. . . which correspond to existing sample instants that immediately precede an associated predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 11 la in conjunction with the time next time values T_a+dT, T_b+dT, T+dT_c. . . (immediately subsequent to a predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a) to interpolate the instantaneous phasor phase angle 154b to form the referenced phasor phase angle of the referenced phasor phase angle stream 111c, in a manner equivalent to the interpolation shown in FIG. 6A for the referenced phasor magnitude of the referenced phasor magnitude stream 111b. Whereas the rotation of the instantaneous phasor phase angle 154b of the above embodiment takes advantage of the known slope of phase change as a function of the local frequency 164, the alternate embodiment interpolation utilizes the instantaneous phasor phase angle 154b sampled on either side of a predetermined time, for example t₁, to determine the referenced phasor phase angle of the referenced phasor phase angle stream 111c (see FIG. 5).

In the alternate embodiment, a representation of the phasors as complex real and imaginary components can be similarly converted from the selected acquisition time values T_a, T_b, T_c. . . to predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a in a manner equivalent to the interpolation shown in FIG. 6A for each referenced phasor magnitude of the referenced phasor magnitude stream 111b. In this case, referencing to a phasor with predetermined phase and frequency of the phase angles is performed in a manner shown by the second operator 316 and the fourth operator 318 of FIG. 6A if the phasor is characterized as having a magnitude and phase angle. For phasors characterized as having a complex real and imaginary part, complex multiplication of the phasor by the phasor with predetermined phase and frequency is sufficient to convert a referenced phasor phase angle of the referenced phasor phase angle stream 111c to an adjusted referenced phasor phase angle of the adjusted referenced phasor phase angle stream 111d.

FIG. 6B is a functional block diagram of another exemplary phasor adjustment block 214, according to an embodiment of the invention. In the exemplary phasor adjusted block of FIG. 6B, referencing to a phasor with predetermined phase and frequency is not performed such that each resulting synchronized phasor includes a predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a, a referenced phasor magnitude of the referenced phasor magnitude stream 111b and a referenced phasor phase angle of the referenced phasor phase angle stream 111c. The exemplary phasor block of FIG. 6B is configured and operational as described in FIG. 6A, except it excludes the second operator to multiply a fixed frequency by the time value referenced to the absolute time standard. As a result, the referenced phasor phase angle stream 111c is generated rather than the adjusted referenced phasor phase angle stream 111d.

FIG. 7 is a functional block diagram of another IED 400 that may be used in conjunction with one or more remote devices, according to an embodiment of the invention. In this case, the remote device (not separately illustrated) converts its input analog signal 102 into a digital format suitable for transmission to the IED 400. A digitized input analog signal 402 is therefore received by the IED 400.

Referring to FIG. 7, rather than the analog filter 140 and the ADC 144 of the IED 100, the IED 400 includes a channel decode 404 configured to decode the digitized input analog signal 402 received from another IED, and a resample block 406. The digitized input analog signal 402 may be received via one of any number of mediums including wired and wireless. The digitized input analog signal 402 may be encoded using well-known methods to ensure transmission security, reduce unwanted effects of noise, reduce multipath signal interference and burst errors, and the like, and may be decoded using one of any number of well-known suitable formats, depending on the IED implementation and/or the encoding scheme.

When received by the channel decode 404, the digitized input analog signal 402 is decoded to form a decoded instantaneous signal 405. The decoded instantaneous signal 405 includes the instantaneous amplitude of the remote analog input signal as well as information regarding a remote data acquisition time value. The remote data acquisition time value indicates an instant at which the power system signal was sampled by the remote device to acquire its analog input signal, where the sampling instant is referenced to an absolute time standard (e.g., UTC). The decoded instantaneous signal 405 may further include additional data such as a power system frequency measured by the remote device (remote frequency), although such frequency information may be derived by the IED 400 from the instantaneous amplitude of the decoded instantaneous signal 405 and the remote data acquisition timestamp, using well-known methods.

The resample block 406 is configured to generate signal samples representative of the input analog signal 102 received by the remote device. Thus, upon receipt by the resample block 406, the decoded instantaneous signal 405 is adjusted from the remote sampling interval to an interval which is representative of the remote frequency. As a result, the sampled analog instantaneous signal 146 (representative of the input analog signal 102 received by the remote device) is provided to the digital filter 148. The remaining components (e.g., sample controller 160) of FIG. 7 are substantially configured and operable as described in connection with FIGS. 3-6 to provide synchronized phasors 111 indication of the power system 10 referenced to the absolute time instants.

FIG. 8 is a functional block diagram of yet another IED 500, according to an embodiment of the invention. In this case, the IED 500 converts the input analog signal 102 to synchronized phasors 111 prior to performing the appropriate protection, automation, control, metering function by the IED function 156 to determine the status of the power system 10. In summary, rather than providing the series of instantaneous phasors 154 from the magnitude and phase angle calculator, along with synchronized phasors 111 from the phasor estimation 200, to the IED function 156 as shown in FIG. 3, the IED 500 includes a phasor estimation 502 coupled to the IED function 156 such that the synchronized phasors 111 are first calculated and then forwarded for use by the IED function 156.

Like the IED of FIG. 3, the IED 500 includes the analog filter 140, the ADC 144, the digital filter 148, the sample controller 160 and the time controller 166, operating as described in connection with FIGS. 3-6. Unlike the IED of FIG. 3 however, the phasor estimation 502 of the IED 500 includes the functionality of the phase calculator 152 (without the 90 degree phase shift functionality), and utilizes a separate 90 degree shift in conjunction with an interpolation to adjust the phase angle of the filtered signal 150 and form the referenced phasor magnitude stream 111b and the referenced phasor phase angle stream 111c and/or the adjusted referenced phasor phase angle stream 111d of the synchronized phasors 111.

FIG. 9 is a functional block diagram of the phasor estimation 502 of the IED 500, according to an embodiment of the invention. The phasor estimation 502 includes a 90 degree shift block 504 having an input for receiving the filtered signal 150. The filtered signal 150 is representative of the input analog signal 102 and is generated in response to the sampling instants of the control signal stream 162. The filtered signal 150 may therefore be denoted as A(T₁, T₂, T₃, . . . ) where each of T₁, T₂, T₃, . . . is an acquisition time value of a corresponding sample of the filtered signal 150, and where A is an instantaneous amplitude.

Upon receipt of the filtered signal 150, the 90 degree shift block 504 operates to shift the filtered signal 150 by 90 degrees to form a shifted filtered signal 503. The 90 degree shift may be accomplished by delaying each of the samples forming the filtered signal 150 by Â¼ cycle, according to the local frequency 164. In one embodiment, the samples of the filtered signal are taken at an integer multiple sixteen times the local frequency 164. The shifted filtered signal 503 may be denoted as A(T₁âˆ’kdT, T₂âˆ’kdT, T₃âˆ’kdT, . . . ) where each of the samples of the filtered signal 150 is delayed by kdT, where k equals an integer value equal to Â¼ of the total number of samples of the filtered signal 150 included in a single analog waveform period T, in this case k=4, and where dT equals a time period between each sample of the filtered signal 150.

The phasor estimation 502 also includes an interpolate block 506 having a first input for receiving the filtered signal 150, having a second input for receiving the shifted filtered signal 503, having a third input for receiving the acquisition time values T₁, T₂, T₃, . . . of the acquisition time value stream 170, and having a fourth input for receiving time value pair stream 513, which includes the predetermined times t₁, t₂, t₃. . . referenced to the absolute time standard 111a along with the selected acquisition time values T_a, T_b, T_c. . . . The interpolate block 506 is configured to adjust the time of each of the samples of the filtered signal 150 and shifted filtered signal 503 from an acquisition time value such as T_a=T₄to a time value referenced to the absolute time standard such as the predetermined time value t₁occurring between two of the acquisition time values such as T₄and T₅

For example, FIG. 10 is a functional block diagram of one example of the interpolate block 506 of the phasor estimation 502, according to an embodiment of the invention. Although illustrated using a number of multipliers, adders, and operators as described below, it is contemplated that the interpolate block 502 may be implemented in one of any number of ways to provide adjustment from the remote sampling interval to the interval which is representative of the remote frequency.

Referring to FIG. 10, the interpolate block 506 includes the first adder 302 configured to subtract a first sample 507 of the filtered signal 150 taken at a selected acquisition time value such as T_a=T₄from a corresponding next sample 509 of the filtered signal 150 taken at a an acquisition time value such as T₅to generate a sample amplitude difference 508. The sample amplitude difference 508 represents a difference in the amplitude between two sequential instantaneous sample magnitudes of the filtered signal 150. The interpolate block 506 also includes the second adder 308 configured to subtract a selected acquisition time value of the selected acquisition time value stream 170, for example, T_afrom a predetermined time referenced to an absolute time standard 111a, for example t₁, to generate the time value difference 310.

Further, the divider 306 of FIG. 10 is configured to divide the time value difference 310 by the acquisition time value delta dT 274 to generate the first proportionality factor 307 (see, FIGS. 5 and 6). In the illustrated example, the time value difference 310 represents a difference in time between the selected acquisition time value T_ato the predetermined time t₁referenced to the absolute time standard 111a, and the acquisition time value delta dT 274 represents a time between the sampling instants of the control signal stream 162. The first multiplier 304 is configured to multiply the sample amplitude difference 508 by the first proportionality factor 307 to generate an intermediate amplitude difference signal 512.

The interpolate block 506 further includes the third adder 328 configured to add the first sample 507 of the filtered signal 150 to the intermediate amplitude difference signal 512 to form an uncalibrated referenced sample amplitude A(t₁) 514. Although not separately illustrated, a shifted uncalibrated referenced sample amplitude A(t₁âˆ’kdT) 516 is equivalently formed via the interpolation block 506. The implementation of âˆ’kdT can be simply selecting a value that is k samples previous to the present value.

Referring again to FIG. 9, each of the uncalibrated referenced sample amplitudes 514, for example A(t₁), and each of the shifted uncalibrated referenced sample amplitudes 516, for example A(t₁âˆ’kdT), are received by a phasor calculator 153. The phasor calculator 153 is configured to calculate a series of uncalibrated referenced phasor magnitudes 518 from the uncalibrated referenced sample amplitudes 514 and the shifted uncalibrated referenced sample amplitudes 516. Similarly, the phasor calculator 153 is configured to calculate a corresponding series of prealigned referenced phasor phase angles 520 from the uncalibrated referenced sample amplitudes 514 and the shifted uncalibrated referenced sample amplitudes 516. Accordingly, each uncalibrated referenced phasor magnitude 518 has a corresponding prealigned referenced phasor phase angle 520. The details of calculating a phasor magnitude and angle representation from a real and imaginary representation is well known, and furthermore can include the well known calculation of sequence quantities such as positive sequence, negative sequence, and zero sequence. In FIG. 9 the real component is represented by the uncalibrated referenced sample amplitude 514 and the imaginary component is represented by the shifted uncalibrated referenced sample amplitudes 516.

The phasor estimation 502 also includes a correct block 522 configured to remove implementation artifacts and distortion from the uncalibrated referenced phasor magnitudes 518 and the prealigned referenced phasor phase angles 520 to form corresponding referenced phasor magnitudes of the referenced phasor magnitude stream 111b and referenced phasor phase angles of the referenced phasor phase angles stream 111c, and/or to form corresponding adjusted referenced phasor magnitudes of the referenced phasor magnitude stream 111 b and corresponding adjusted referenced phasor phase angles of the adjusted referenced phasor phase angles stream 111d.

FIG. 11 is a functional block diagram of an exemplary correct block 522, according to an embodiment of the invention. In the exemplary correct block 522 of FIG. 11, referencing to a phasor with predetermined phase and frequency is performed such that each resulting referenced phasor includes a referenced phasor magnitude of the referenced phasor magnitude stream 111b and an adjusted referenced phasor phase angle of the adjusted referenced phasor phase angle stream 111d, at a predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a. It is contemplated however, that like the phasor adjustment block of FIG. 6A, referencing to a phasor with predetermined phase and frequency is not necessarily performed in the exemplary correct block 522 of FIG. 11 such that each resulting referenced phasor includes a referenced phasor magnitude of the referenced phasor magnitude stream 111b and a referenced phasor phase angle of the referenced phasor phase angle stream 111c at a predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a.

As illustrated, the correct block 522 includes a first input for receiving the uncalibrated referenced phasor magnitude 518, a second input for receiving the local frequency 164, a third input for receiving the predetermined time value stream 111a, and a fourth input for receiving the prealigned referenced phasor phase angle 520. The correct block 522 also includes the second operator 316 configured to multiply the reference frequency 324 of the fixed frequency reference phasor by a time value of the predetermined time value stream 111a, for example, the time value t₁, followed similarly by unit conversion, to generate the third proportionality factor 309. The correct block 522 further includes the fourth operator 318 configured to add the prealigned referenced phasor phase angle 520 to the third proportionality factor 309, followed by modulo conversion to the desired phase angle range to form an uncalibrated referenced phasor phase angle 526.

Implementation magnitude distortion can be approximated and removed via the Mag Implement Correction 330 configured to receive the local frequency 164 and remove any implementation distortion to form the magnitude correction factor 321 using one of a number of techniques as described in connection with FIGS. 6A and B. Similarly, implementation phase angle distortion or shift can be approximated and removed via the Angle Implement Correction 332 configured to receive the local frequency 164 and remove any implementation distortion to form the angle correction factor 317 using one of a number of techniques as described in connection with FIGS. 6A and B. It is not the purpose of Mag Implement Correction 330 or Angle Implement Correction 332 to correct for off-nominal sampling errors. This is because the invention samples as a function of the varying frequency of the local signal (e.g. input analog signal 102) and therefore does not require corrections to compensate for sampling at a rate different than the local signal, such as fixed rates or rates based on the absolute time reference.

The second multiplier 320 of the correct block 522 is configured to multiply the uncalibrated referenced phasor magnitude 518 with the magnitude correction factor 321 to form the referenced phasor magnitudes of the referenced phasor magnitude stream 111 b. Similarly, the fifth operator 322 of the correct block 522 is configured to add the uncalibrated referenced phasor phase angle 526 to the angle correction factor 317 to form the referenced phasor phase angles of the referenced phasor phase angle stream 111d. In this way, referenced phasors are accurately estimated at time values referenced to an absolute time standard in an electrical system. The uncalibrated referenced phasor magnitude 518 and the prealigned referenced phasor phase angle 520 may be representative of values at times slightly different than the predetermined time t₁, t₂, t₃. . . referenced to an absolute time standard 111a and this difference is corrected by the magnitude correction factor 321 and the phase correction factor 317. In some cases the uncalibrated referenced phasor magnitude 518 can be corrected by an interpolation step in place of the second multiplier 320.

The present method may be implemented as a computer process, a computing system or as an article of manufacture such as a computer program product or computer readable media. The computer program product may be a computer storage media readable by a computer system and encoding a computer program of instructions for executing a computer process. The computer program product may also be a propagated signal on a carrier readable by a computing system and encoding a computer program of instructions for executing a computer process.

FIG. 12 is a functional block diagram of yet another IED 600 that may be used in conjunction with one or more remote devices, according to an embodiment of the invention. In this case, the remote device (not separately illustrated) converts its input analog signal 102 into a digital format suitable for transmission to the IED 600. A digitized input analog signal 602 is therefore received by the IED 600.

Rather than the analog filter 140 and the ADC 144 of the IED 100, the IED 400 includes channel decode block 604 configured to decode the digitized input analog signal 602 received from a remote IED, and a resample block 406. The digitized input analog signal 602 may be received via one of any number of mediums including wired and wireless. The digitized input analog signal 602 may be encoded using well-known methods to ensure transmission security, reduce unwanted effects of noise, reduce multipath signal interference and burst errors, and the like, and may be decoded using one of any number of well-known suitable formats, depending on the IED implementation and/or the encoding scheme.

When received by the channel decode block 604, the digitized input analog signal 602 is decoded to form a decoded instantaneous signal 405. The decoded instantaneous signal 405 includes the instantaneous amplitude of the remote analog input signal as well as information regarding a remote data acquisition time value. The remote data acquisition time value indicates an instant at which the power system signal was sampled by the remote device to acquire its analog input signal, where the sampling instant is referenced to an absolute time standard (e.g., UTC). The decoded instantaneous signal 405 may further include additional data such as power system frequency measured by the remote device (remote frequency), although such frequency information may be derived by the IED 400 from the instantaneous amplitude of the decoded instantaneous signal 405 and the remote data acquisition timestamp, using well-known methods.

The resample block 606 is configured to generate signal samples representative of the input analog signal 602 received by the remote device. Thus, upon receipt by the resample block 606, the decoded instantaneous signal 405 is adjusted from the remote sampling interval to an interval which is representative of the remote frequency. As a result, the sampled analog instantaneous signal 146 (representative of the input analog signal 602 received by the remote device) is provided to the digital filter 148. The remaining components (e.g., sample controller 160) of FIG. 12 are substantially configured and operable as described in connection with FIGS. 8 to provide synchronized phasors 111 indication of the power system 10 referenced to the absolute time instants.

In one embodiment, the logical operations of the present method are implemented (1) as a sequence of computer implemented acts or program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system. The implementation is a matter of choice dependent on the performance requirements of the computing system implementing the invention. Accordingly, the logical operations making up the embodiments of the present invention described herein are referred to variously as operations, structural devices, acts or modules. It will be recognized by one skilled in the art that these operations, structural devices, acts and modules may be implemented in software, in firmware, in special purpose digital logic, and any combination thereof without deviating from the spirit and scope of the present invention as recited within the claims attached hereto.

While this invention has been described with reference to certain illustrative aspects, it will be understood that this description shall not be construed in a limiting sense. Rather, various changes and modifications can be made to the illustrative embodiments without departing from the true spirit, central characteristics and scope of the invention, including those combinations of features that are individually disclosed or claimed herein. Furthermore, it will be appreciated that any such changes and modifications will be recognized by those skilled in the art as an equivalent to one or more elements of the following claims, and shall be covered by such claims to the fullest extent permitted by law.