BACKGOUND OF THE INVENTION 0001 1. Field of the Invention 0002 This invention relates to an improved single-stage input-current-shaping flyback converter with fast output-voltage regulation, and, more particularly, to a single-stage, single-switch input-current-shaping flyback converter with reduced conduction losses in the primary side of the converter. 0003 2. Discussion of the Related Art 0004 In single-stage input-current-shaping (S21CS) converters, input-current shaping (ICS), isolation, and high-bandwidth output-voltage control are performed in a single conversion step (i.e., without creating a regulated DC bus, as is commonly found in two-stage ICS converters). Most of the S2ICS circuits integrate a boost ICS stage with a forward or flyback DC/DC-converter stage. Generally, S2ICS converters meet European and/or Japanese regulatory requirements regarding the line-current harmonic limits, but they do not improve the power factor (PF) and reduce the total harmonic distortion (THD) as much as their two-stage counterparts. Typically, PF for the S2ICS converters is between 0.8 and 0.9 with a THD in the 40-75% range. 0005 An input-current-shaping circuit of a simple, cost-effective, and efficient S2ICS flyback converter is described in U.S. Pat. No. 5,991,172 (the Jovanovic '172 patent) to M. M. Jovanovic and L. Huber, entitled AC/DC flyback converter with improved power factor and reduced switching loss, and U.S. Pat. No. 6,005,780 (the Hua '780 patent) to G. Hua, entitled Single-stage ac/dc conversion with PFC-tapped transformers. FIG. 1 shows such an input-current shaping circuit in S2ICS converter 100. In FIG. 1, ICS in S2ICS converter 100 is achieved by adding inductor 101 (LICS) in series with rectifier 102 (DICS) to a conventional AC/DC flyback converter without PFC. Inductor 101 and rectifier 102 are connected between the positive terminal of full-bridge rectifier 103 (FBR) and primary-winding tap 105 of flyback transformer 104 (T). 0006 By connecting inductor 101 and rectifier 102 in series to primary-winding tap 105 of flyback transformer 104, the voltage across energy-storage (bulk) capacitor 106 (CB) can be limited to a desired level (e.g., 400 V at the universal line range of 90-264 Vnms) In fact, when switch 108 (SW) is closed (on), winding 107a (N1), which is a portion of primary winding 107 (NP) of flyback transformer 104, appears in series with ICS inductor 101. When switch 108 is open (off), winding 107b (N2), which is the other portion of primary winding 107 (NP), appears in series with ICS inductor 101. Thus, regardless of whether switch 108 is open or closed, the voltage across the portion of primary winding 107 conducting the ICS inductor current opposes the rectified line voltage Vin, across capacitor 109 (Cin). Consequently, the volt-second balance of the ICS-inductor core is achieved at a substantially reduced bulk-voltage level. In addition, winding 107b provides a direct energy transfer path to the output load 110 when switch 108 is off, thereby improving conversion efficiency. Performance in S2ICS converter 100 is optimized by varying the tap location on the primary winding 107 of flyback transformer 104. 0007 Input-current shaping inductor 101 is usually designed to operate in discontinuous conduction mode (DCM). Under DCM operation, low input-current harmonic distortion is achieved because a DCM boost converter inherently draws a near sinusoidal current if its duty cycle is held relatively constant during a half line cycle. If the inductance of ICS inductor 101 exceeds its maximum value for DCM operation, inductor 101 operates in the continuous conduction mode (CCM) during a narrow interval near the peak of the rectified line voltage. Generally, a larger inductance of inductor 101 increases converter efficiency and decreases input-current ripples. However, a larger inductance of inductor 101 also decreases input power factor and increases line current harmonics. 0008 A flyback transformer can operate in DCM, CCM, or at the DCM/CCM boundary. As described in the Jovanovic '172 patent, turn-on switching loss can be substantially reduced by operating flyback transformer 104 at the DCM/CCM boundary. To operate flyback transformer at the DCM/CCM boundary over the entire line and load range, a variable switching-frequency control circuit is used. Control circuit 120 provides the required control signal SW for periodically opening and closing switch 108. 0009 Input-filter capacitor 109 can be connected on either the DC side of full-wave bridge rectifier 103 (such as shown in FIG. 1), or the AC side of full-wave bridge rectifier 103. Similarly, input-filter inductors 111a (Lin1) and 111b (Lin2) can be connected on either side of full-bridge rectifier 103. 0010 With ICS-inductor 101 operating in DCM, S2ICS flyback converter 100 is well suited for universal-line applications (e.g., in a notebook adapter or charger). In such a configuration, the line current quality of S2ICS converter 100 is approximately the same at low-line and high-line voltages, as explained in U.S. Pat. No. 5,757,626 (the Jovanovic '626 patent) to M. M. Jovanovic and L. Huber, entitled Single-stage, single-switch, isolated power-supply technique with input-current shaping and fast output-voltage regulation. However, the DCM operation of the ICS inductor results in a larger current stress on switch 108 and larger input-current ripple. A larger current stress on switch 108 reduces converter efficiency, and a larger input-current ripple requires a larger input filter. Furthermore, the conduction loss of the primary-side rectifiers (i.e., full bridge rectifier 103 and rectifier 102) in FIG. 1 is high because the current of ICS inductor 102 always includes three rectifiers: rectifiers 103a, 102, and 103d conduct during a positive half cycle of line voltage vin, and rectifiers 103b, 102, and 103c conduct during a negative half cycle of line voltage vin. Generally, S2ICS flyback converter 100 in FIG. 1 is limited to operation at power levels below 100 W. 0011 To improve efficiency and power level, two S2ICS flyback converters can be interleavedi.e., two converters can be connected in parallel, with the switching instances of the primary gate signals phase-shifted by 180. With interleaving, input and output filter sizes can be significantly reduced and the total power loss can be evenly distributed between the two parallel converters. However, interleaving of two converters significantly increases the number of components. Furthermore, if the flyback transformer operates at the DCM/CCM boundary, interleaving of variable-frequency converters requires a relatively complex control circuit. 0012 It is thus desired to improve efficiency and to increase the maximum power level of the S2ICS flyback converter by reducing primary-side conduction losses caused by increased input-current ripple and increased rectifier conduction losses in a simple and cost-effective way.

SUMMARY OF THE INVENTION 0013 The present invention provides a single-stage input-current-shaping (S2ICS) flyback converter that has substantially reduced conduction losses in the primary side of the converter. According to one embodiment of the present invention, a bypass diode is connected between the positive terminal of the full-bridge rectifier and the positive terminal of an energy-storage capacitor. In that configuration, current interleaving between an energy-storage inductor in the ICS part of the S2ICS flyback converter and the bypass diode is achieved around the peak of the rectified line voltage, which results in a significantly reduced input-current ripple and reduced current stress on the switch. 0014 According to another embodiment of the present invention, the rectifiers in the ICS part of the S2ICS flyback converter are arranged in such a way that the energy-storage capacitor and the ICS inductor are connected to the AC line voltage through only two rectifiers, thus eliminating one diode forward-voltage drop and hence achieving a substantially reduced conduction loss in the primary-side rectifiers. 0015 Accordingly, the present invention improves both efficiency and the maximum power level of a S2ICS flyback converter by reducing primary-side conduction losses caused by increased input-current ripple and increased rectifier conduction losses. 0016 The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS 0017 FIG. 1 shows S2ICS converter 100 with input current-shaping of the prior art. 0018 FIG. 2 is a circuit diagram of S2ICS flyback converter 200, according to one embodiment of the present invention. 0019 FIG. 3(a) shows typical waveforms of line voltage vin, line current iin, and voltage VCB of bulk capacitor 106 in S2ICS flyback converter 200. 0020 FIG. 3(b) shows waveforms of line current iin, current ILICS of ICS inductor 101, current iDBYP of bypass diode 201, and voltage vCin of input filter capacitor 109 in S2ICS flyback converter 200 at instant T0, which is indicated in FIG. 3(a). 0021 FIG. 3(c) shows waveforms of line current iin, current iLICS of ICS inductor 101, current iDBYP of bypass diode 201, and voltage VCin of input filter capacitor 109 in S2ICS flyback converter 200 at instant T1, which is indicated in FIG. 3(a). 0022 FIG. 4(a) shows the current path of ICS inductor current iLICS in S2ICS flyback converter 200 during a positive half-cycle of line voltage Vin, when switch 108 is closed. 0023 FIG. 4(b) shows the current path of ICS inductor current iLICS in S2ICS flyback converter 200 during a positive half-cycle of line voltage vin, when switch 108 is open. 0024 FIG. 4(c) shows the current path of ICS inductor current iLICS in S2ICS flyback converter 200 during a negative half-cycle of line voltage vin, when switch 108 is closed. 0025 FIG. 4(d) shows current path of ICS inductor current iLICS in S2ICS flyback converter 200 during a negative half-cycle of line voltage Vin, when switch 108 is open. 0026 FIG. 5(a) shows the path of bypass-diode current iDBYP in S2ICS flyback converter 200 during a positive half-cycle of the line voltage. 0027 FIG. 5(b) shows the path of bypass-diode current iDBYP in S2ICS flyback converter 200 during a negative half-cycle of the line voltage, 0028 FIG. 6 shows a circuit diagram of S2ICS flyback converter 600, according to a second embodiment of the present invention. 0029 FIG. 7(a) shows the current path for ICS-inductor current iLICS in S2ICS flyback converter 600 during a positive half-cycle of line voltage vin, when switch 108 is closed. 0030 FIG. 7(b) shows the current path for ICS-inductor current iLICS in S2ICS flyback converter 600 during a positive half-cycle of line voltage vin, when switch 108 is open. 0031 FIG. 7(c) shows the current path for ICS-inductor current iLICS in S2ICS flyback converter 600 during a negative half-cycle of line voltage vin, when switch 108 is closed. 0032 FIG. 7(d) shows the current path for ICS-inductor current iLICS in S2ICS flyback converter 600 during a negative half-cycle of line voltage Vin, when switch 108 is open. 0033 FIG. 8(a) shows the path of bypass-diode current iDBYP in S2ICS flyback converter 600 during a positive half-cycle of line voltage vin. 0034 FIG. 8(b) shows the path of bypass-diode current iDBYP in S2ICS flyback converter 600 during a negative half-cycle of line voltage vin. 0035 FIG. 9 shows a circuit diagram of S2ICS converter 700, including RCD clamp circuit. 0036 FIG. 10 shows a circuit diagram of S2ICS converter 800 including a combined RCD clamp for rectifiers 601e and 601f of full-wave bridge rectifier 602 and for switch 108.

0037 To facilitate comparison among features shown in the various figures, like elements are assigned like reference numerals.

DETAILED DESCRIPTIONS OF THE PREFERRED EMBODIMENTS 0038 FIG. 2 is a circuit diagram of S2ICS flyback converter 200, according to one embodiment of the present invention. As shown in FIG. 2, S2ICS flyback converter 200 is substantially the same as S2ICS flyback converter 100 of FIG. 1, except that bypass diode 201 (DBYP) is connected between the positive terminal of full-bridge rectifier (FBR) 103 and the positive terminal of energy-storage (bulk) capacitor 106 (CB). A control circuit 205 provides a control signal SW for periodically opening and closing switch 108, according to a switching control scheme. One such scheme, for example, opens and closes switch 108 at a variable frequency such that transformer 104 operates at the boundary between discontinuous and continuous conduction modes. Secondary-side rectifier 115 can be implemented either with a Schottky rectifier or with a synchronous rectifier. 0039 FIGS. 3(a), 3(b) and 3(c) illustrate the basic operation of bypass diode 201 and the effects of diode 201 on the ICS waveforms. FIG. 3(a) shows typical waveforms of line voltage vin, line current iin, and voltage VCB of bulk (or energy-storage) capacitor 106. FIGS. 3(b) and 3(c) respectively show waveforms of line current iin, current iLICS of ICS inductor 101, current iDBYP of bypass diode 201, and voltage VCin, of input filter capacitor 109 at two different instants T0 and T1 that are indicated in FIG. 3(a). 0040 At instant T0, as shown in FIGS. 3(a) and 3(b), rectified line voltage vin at terminal 202 (waveform 301) is lower than voltage VCB of capacitor 106 (waveform 302), and bypass diode 201 is not conducting (i.e. current iDBYP0, waveform 305). The peak value of DCM ICS-inductor current iLICS (waveform 303) is slightly larger than twice line current iin (waveform 304), which is the average of ICS-inductor current iLICS over a switching cycle. As shown in FIG. 3(b), the high-frequency ripple component of ICS-inductor current iLICS that flows through input-filter capacitor 109 generates a substantial ripple voltage VCin, across capacitor 109. At instant T1, as shown in FIGS. 3(a) and 3(c), rectified line voltage vin (waveform 301), which is near its peak value, is higher than bulk-capacitor voltage VCB (waveform 302) and bypass diode 201 is conducting. As shown in FIG. 3(c), the peak value of DCM ICS-inductor current iLICS (waveform 303) is significantly smaller than twice line current iin (waveform 304), as in FIG. 3(b), i.e., ICS-inductor current iLICS is only slightly larger than line current iin, which is at its peak value at instant T1. In fact, when bypass diode 201 conducts, energy-storage capacitor 106 is connected in parallel to input-filter capacitor 109, thus keeping voltage vCin across input-filter capacitor 109 at an almost constant level. Consequently, the current through input-filter capacitor 109, which includes high-frequency ripple components of current iLICS of ICS inductor 101 and current IDBYP of bypass diode 201, does not exhibit a high ripple. As shown in FIG. 3(c), to result in such low-ripple, DCM current iDBYP of bypass diode 201 has substantially the same waveshape as DCM current iLICS of ICS-inductor 101, but phase shifted by approximately 180 from current iLICS. In converter 200 of FIG. 2, current iDBYP of bypass diode 201 is interleaved with current iLICS of ICS-inductor 101 at or about the peak of the line voltage vin (waveform 301). 0041 As illustrated in FIG. 3(c), at instant T1, the sum of interleaved currents iLICS and iDBYP, which is shown as waveform 306, exhibits a very small ripple. The average of current sum iLICSiDBYP over a switching cycle is equal to line current iin. The small high-frequency ripple component of current sum iLICSiDBYP flows through input-filter capacitor 109 generating a small ripple voltage VCin across capacitor 109. Because the current sum iLICSiDBYP has a low ripple around the peak of the rectified line voltage (i.e., waveform 301), the size of input filter capacitor 109 can be significantly reduced. Also, because the peak value of current iLICS is reduced almost 50% compared to the peak current without interleaving, the current stress on switch 108 is also significantly reduced. 0042 In FIG. 2, input-filter capacitor 109 is connected on the DC side of full-wave bridge rectifier 103. However, the effect of bypass diode 201 on the operation of S2ICS flyback converter 200 is the same, even if input-filter capacitor 109 is connected on the AC side of full-bridge rectifier 103. Similarly, input-filter inductors 111a and 111b can be connected on either side of full-wave bridge rectifier 103. 0043 The paths of ICS-inductor current iLICS and bypass-diode current iDBYP each include three rectifiers, resulting in a substantial conduction loss. FIGS. 4 and 5 show the paths of ICS-inductor current iLICS and bypass-diode current iDBYP under different operation modes. To simplify description, FIGS. 4 and 5 both show input-filter capacitor 109 connected on the AC side of full-wave bridge rectifier 103 and incorporated into input-filter block 401 with EMI filter 112 and input-filter inductors 111a and 111b. 0044 FIGS. 4(a) and 4(b) show the paths of ICS-inductor current iLICS during a positive half-cycle of line voltage vin, with switch 108 closed and open, respectively. As shown in FIG. 4(a), with switch 108 closed and input voltage Vin at a positive half-cycle, the current path of ICS-inductor current iLICS includes rectifiers 103a and 103d of full-wave bridge rectifier 103, rectifier 102, ICS inductor 101, primary winding 107a of transformer 104 and switch 108. When switch 108 is open and input voltage Vin, is at a positive half-cycle, the current path of ICS-inductor current iLICS includes rectifiers 103a and 103d of full-wave bridge rectifier 103, rectifier 102, ICS inductor 101, primary winding 107b of transformer 104 and bulk capacitor 106. 0045 FIGS. 4(c) and 4(d) show the paths of ICS-inductor current iLICS during a negative half-cycle of line voltage vin, with switch 108 closed and open, respectively. As shown in FIG. 4(c), with switch 108 closed and input voltage Vin, at a negative half-cycle, the current path of ICS-inductor current iLICS includes rectifiers 103b and 103c of full-wave bridge rectifier 103, rectifier 102, ICS inductor 101, primary winding 107a of transformer 104 and switch 108. When switch 108 is open and input voltage vin is at a negative half-cycle, the current path of ICS-inductor current iLICS includes rectifiers 103b and 103c of full-wave bridge rectifier 104, rectifier 102, ICS inductor 101, primary winding 107b of transformer 104 and bulk capacitor 106. 0046 FIGS. 5(a) and 5(b) show the paths of bypass-diode current iDBYP during positive and negative half-cycles of the line voltage, respectively. As shown in FIG. 5(a), during a positive half cycle of line voltage vin, the current path of bypass-diode current iDBYP includes rectifiers 103a and 103d of full bridge rectifier 104, bypass-diode 201, and bulk capacitor 106. During a negative half-cycle of line voltage Vin, as shown in FIG. 5(b), the current path of bypass-diode current iDBYP includes rectifiers 103b and 103c of full bridge rectifier 104, bypass-diode 201, and bulk capacitor 106. 0047 By arranging the primary-side rectifiers such that energy-storage capacitor 106 and ICS inductor 101 are connected to AC line voltage vin, through two separated full-wave bridge rectifiers, a diode forward-voltage drop can be eliminated from the current paths of both ICS-inductor current iLICS and bypass-diode current iBYPD. Such an arrangement is shown in FIG. 6, for example, which shows a circuit diagram of S2ICS flyback converter 600, according to a second embodiment of the present invention. In FIG. 6, energy-storage capacitor 106 and ICS-inductor 101 are connected to AC line voltage vin, through two full-wave bridge rectifiers 601 and 602, formed respectively by rectifiers 601a, 601b, 601c and 601d, and 601a, 601b, 601e and 601f (i.e., rectifiers 601a and 601b are common to both full-bridge rectifiers). Even though the total number of the primary-side rectifiers in S2ICS flyback converter 600 in FIG. 6 is the same as the total number of primary-side rectifiers in S2ICS flyback converter 200 of FIG. 2, as shown below, only two rectifiers conduct at a time in a current path of S2ICS. A control circuit 603 provides a control signal SW for periodically opening and closing switch 108 according to a switching control scheme. As in control circuit 205 of FIG. 2, one applicable switching scheme, for example, opens and closes switch 108 such that transformer 104 operates at the boundary between discontinuous and continuous conduction modes. 0048 For S2ICS converter 600, the paths of ICS-inductor current iLICS and bypass-diode current iDBYP under different operation modes are shown in FIGS. 7(a)-7(d), 8(a) and 8(b). FIG. 7(a) shows the current path for ICS-inductor current iLICS during a positive half-cycle of line voltage Vin, when switch 108 is closed. As shown in FIG. 7(a), during a positive half-cycle of line voltage vin, with switch 108 closed, current path of ICS-inductor current iLICS of ICS inductor 101 includes rectifiers 601b, 601e, ICS inductor 101, portion 107a of a primary winding of transformer 104, and switch 108. FIG. 7(b) shows the current path for ICS-inductor current iLICS during a positive half-cycle of line voltage vin, when switch 108 is open. During a positive half-cycle of line voltage vin, with switch 108 open, current path of ICS-inductor current iLICS of ICS inductor 101 includes rectifiers 601b, 601e, ICS inductor 101, portion 107b of a primary winding of transformer 104, and bulk capacitor 106. 0049 FIG. 7(c) shows the current path for ICS-inductor current iLICS during a negative half-cycle of line voltage Vin, when switch 108 is closed. During a negative half-cycle of line voltage vin, with switch 108 closed, current path of ICS-inductor current iLICS of ICS inductor 101 includes rectifiers 601a, 601f, ICS inductor 101, portion 107a of a primary winding of transformer 104, and switch 108. FIG. 7(d) shows the current path for ICS-inductor current iLICS during a negative half-cycle of line voltage vin, when switch 108 is open. During a negative half-cycle of line voltage Vin, with switch 108 open, current path of ICS-inductor current iLICS of ICS inductor 101 includes rectifiers 601a, 601f, ICS inductor 101, portion 107b of a primary winding of transformer 104, and bulk capacitor 106. 0050 FIG. 8(a) shows the path of bypass-diode current iDBYP during a positive half-cycle of line voltage vin. During a positive half-cycle of line voltage vin, the current path of bypass-diode current iBYPD includes rectifiers 601b, 601c, and bulk capacitor 106. FIG. 8(b) shows the path of bypass-diode current iDBYP during a negative half-cycle of line voltage vin. During a negative half-cycle of line voltage vin, the current path of bypass-diode current iBYPD includes rectifiers 601a, 601d, and bulk capacitor 106. 0051 With the reduced number of diode-forward-voltage drops, the conduction loss of the primary-side rectifiers in the S2ICS flyback converter in FIG. 6 is substantially reduced. 0052 FIG. 9 shows a circuit diagram of S2ICS converter 700, which differs from the circuit diagram of S2ICS converter 600 in FIG. 6 in an additional RCD clamp circuit that includes rectifier 701, resistor 702, and capacitors 703. This RCD clamp is used to limit the voltage stress on switch 108 caused mainly by the leakage inductance of transformer 104. 0053 Rectifiers 601e and 601f of full-wave bridge rectifier 602 in FIG. 9 may be also exposed to considerable voltage stresses because of the ringing between ICS inductor 101 and the capacitance of the inversely polarized rectifiers in full-wave bridge rectifier 602. This ringing occurs after the reset of ICS inductor 101 in a switching cycle. To limit the voltage stress on rectifiers 601e and 601f, the common-cathode voltage of rectifiers 601e and 601f is clamped. To clamp the voltage of rectifiers 601e and 601f, an RCD clamp that is similar to the RCD clamp for switch 108 (described above) can be used. FIG. 10 shows, for example, a circuit diagram of S2ICS converter 800, which combines the voltage clamp for rectifiers 601e and 601f and the voltage clamp for switch 108 in an RCD clamp circuit that includes rectifiers 701 and 801, resistors 702 and 802, and capacitors 703 and 803. By properly selecting the values of the resistances and capacitances in the voltage divider circuit that includes resistors 702 and 802 and capacitors 703 and 803, the voltage clamp level for rectifiers 601e and 601f and the voltage clamp level for switch 108 can be optimized. A simplified implementation of the RCD clamp circuit in FIG. 10 is obtained when resistor 702 is shorted and the cathodes of rectifiers 701 and 801 are connected together. The voltages of rectifiers 601a and 601b of full-wave bridge rectifier 601 are already clamped to the bulk-capacitor voltage through rectifiers 601c and 601d of full-wave bridge rectifier 601. 0054 In flyback converter 200 of FIG. 2, a voltage clamp circuit can be used to limit the voltage stress on rectifier 102, in the manner similar to the voltage clamp circuits described above with respect to FIGS. 9 and 10. 0055 The above detailed description is provided to illustrate the specific embodiments of the present invention. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the claims set forth in the following.