FIELD OF THE INVENTION 0001 The present invention relates to electronic industry, and more particularly to a method of forming connections on a printed circuit board (PCB).

BACKGROUND OF THE INVENTION 0002 In a conventional PCB, there always were connections, interconnections or interfacial connections, on a conductor pattern thereof to electrically connect the conductor pattern to another electronic devices or another conductor pattern. 0003 A conventional method of making the interconnections was that remove the specific part of a solder mask of the PCB to expose the specific portion of the conductor pattern, and then plate NiAu layers on the exposed conductor pattern to form the interconnections. The interconnections, we called them as bonding pads, can be electrically connected with another electronic device by solder jointing, wire bonding or by direct connection. The interconnection also can be bump pads with which bare chips can be connected thereto by direct chip attach (DCA). 0004 Plating method was popular in making interfacial connections in a multi-layer PCB for electrical connection circuits on different layers such that we always found blind via, buried via or plated through hole therein. 0005 The conventional plated connections usually have lands on the surface of the substrate. They took larger space of the PCB such that the conductor pattern had to increase the pitch between two traces. It is harmful to make the PCB into a smaller size. The plated connections also have some problems, such as tough process control on copper-reduction or hole-filling, poor adhesion caused by incomplete cleaning the smear on the side wall of the via, and registration error of the via due to the shrinkage or expansion of conductor patterns etc. That will make the PCB having higher proportion of defective.

SUMMARY OF THE INVENTION 0006 The primary object of the present invention is to provide a method of making connections on a conductor pattern of a PCB, which take less space of the PCB. The secondary object the present invention is to provide a method of making connections on a conductor pattern of a PCB, which manufactures the PCB having a lower proportion of defective. 0007 According to the objects of the present invention, a method of making connections on a conductor pattern of a PCB comprises the steps of: 0008 a) Prepare a substrate with a conductive layer at a side thereof 0009 b) Form the conductive layer to a conductor pattern having at least a first portion and second portions, wherein a surface of the first portion is higher than the surfaces of the second portions, and 0010 c) Provide an insulating layer on the substrate for sheltering the second portions of the conductor pattern but exposing the first portion of the conductor pattern.

BRIEF DESCRIPTION OF THE DRAWINGS 0011 FIG. 1 is a flow chart of a preferred embodiment of the present invention. 0012 FIG. 2 is a sectional view of the preferred embodiment of the present invention, showing a substrate with a conductive layer thereon; 0013 FIG. 3 is a sectional view of the preferred embodiment of the present invention, showing the conductive layer is made into a conductor pattern having first portions and second portions; 0014 FIG. 4 is a sectional view of the preferred embodiment of the present invention, showing an insulating layer sheltering the second portions but exposing the first portion; 0015 FIG. 5 is a sectional view of the preferred embodiment of the present invention, showing a first way to form the first portions and the second portions; 0016 FIG. 6 to FIG. 9 are sectional views of the preferred embodiment of the present invention, showing a second way to form the first portions and the second portions; 0017 FIG. 10 to FIG. 12 are sectional views of the preferred embodiment of the present invention, showing three formats of the first portions being exposed; 0018 FIG. 13 to FIG. 15 are sectional views of the preferred embodiment of the present invention, showing a build-up process is applied on the substrate, and 0019 FIG. 16 is a sectional view of the preferred embodiment of the present invention, showing the exposed portions of the first portions are plated with NiAu layers.

DETAIL DESCRIPTION OF THE INVENTION 0020 Please refer to FIGS. from FIG. 1 to FIG. 4, a method of making connections on a conductor pattern of a printed circuit board (PCB) comprises the steps of: 0021 a) Prepare a substrate 10 with a conductive layer 20 at a side thereof. 0022 Please refer to FIG. 2, the substrate 10 is made of base material, such as multi-function epoxy resin etc. The conductive layer 20 is a copper foil fastened on the substrate 10. 0023 b) Form the conductive layer 20 to a conductor pattern 21 having first portions 22 and second portions 23. 0024 Please refer to FIG. 3, the known photochemical processes are applied to the conductive layer 20 to etch the unnecessary parts of the conductive layer 20 out to form the conductor pattern 21 with a specific layout. The conductor pattern 21 has first portions 22 and second portions 23, wherein the first portions 22 like posts standing on the second portions 23, i.e., the first portions 22 and the second portions 23 are different in height and the surfaces of the first portions are higher than the surfaces of the second portions. 0025 The present inventors disclose two ways of disposing the first portions 22 and the second portions 23 of the conductor pattern 21 hereunder: 0026 b1) Please refer to FIG. 5 provide a copper foil with larger thickness on the substrate 10 first, and then remove selective areas (shown as the dot lines in the FIG.) of the copper foil to make it thinner, therefore, the portions of the copper foil being thinned will be the second portions 23 and the unthinned portions thereof will be the first portions 22. 0027 b2) Please refer to FIG. 6, coat a mask layer 15 (such as dry film) onto the substrate 10, and then conformal opening the mask layer 15 to dispose vias 16 (FIG. 7). Next, plate copper to fill the vias 15 (FIG. 8). At last, please refer to FIG. 9, remove the mask layer 15, such that the plated coppers will be the first portions 22 and the rest will be the second portions 23. 0028 It has to be mentioned here, the first portions 22 and the second portions 23 can be disposed before patterning the conductor pattern 21, it also can be done by disposing the first portions 22 and the second portions 23 after the conductor pattern 21 had been patterned. 0029 c) Please refer to FIG. 4, apply an insulating layer 30 onto the substrate 10 for sheltering the second portions 23 of the conductor pattern 21 but exposing the distal ends of the first portions 22 of the conductor pattern 21. 0030 The insulating layer 30 can be made from masking material, such as multi-function epoxy resin etc. The insulating layer 30 can be disposed on the substrate 10 by coating and laminating etc. The insulating layer 30 also can be disposed by attaching a resin coated copper foil (RCC) as the inventors' earlier invention (U.S. Pat. No. 6,395,625) disclosed. 0031 The methods of exposing the first portions 22 after the insulating layer 30 had been set are: 0032 1. Scrub the surface of the insulating layer 30. 0033 2. Plasma etch the surface of the insulating layer 30. 0034 3. Conformal open the insulating layer 30 at the portions above the first portion 22 by laser shot or by plasma etching. 0035 4. Carefully control the thickness of the insulating layer 30 when coating or laminating to make the insulating layer 30 unsheltered the first portion 22 directly. 0036 FIG. 10 to FIG. 12 show the perspective views of the exposed first portions 22 of the PCB of the present invention made from the methods above. Method 1, 2 and 4 might make the first portion 22 like FIG. 10 (the distal ends of the first portions 22 located at the same level of the surface of the insulating layer 30). Method 2 and 4 might make the first portion 22 like FIG. 11 (the distal ends of the first portions 22 extruded out of the insulating layer 30). Method 3 will make the first portion 22 like FIG. 12 (the distal ends of the first portions 22 under the surface of the insulating layer 30). 0037 It has to be mentioned that the drawings of the preferred embodiment of the present invention shows the substrate 10 is provided with a conductor pattern 21 only at one side thereof In practice, it should prepare a substrate with a conductor pattern at both sides thereof (not shown) and with plated through holes (PTHS) (not shown) in the substrate to electrically connect the circuits on the opposite sides. Aforementioned step b and step c are applied to the conductive layers on the opposite sides of the substrate to form a double sided PCB. 0038 If the method of the present invention is applied to a build-up process, please refer to FIG. 13 to FIG. 15, it would chemical plate and electrically plate (depends on the requirement) a second conductive layer 40 onto the surface of the insulating layer 30 for electrical connection with the first portions 22 of the conductor pattern 21. Then, aforementioned step b and step c are applied to the second conductive layer 40 such that there will be a second conductor pattern 41 and a second insulating layer 50 on the insulating layer 30. Similarly, the second conductor pattern 41 has first portions 42 and second portions 43 and the second insulating layer 50 shelters the second portions 43 but exposing the first portions 42. It can repeatedly apply the step b and step c to form a third layer, a fourth layer and more on the PCB. The first portions 22 and 42 will be interfacial connections for electrically connection the conductor patterns on different layers. 0039 The methods of forming the second conductor pattern 41, the first and the second portions 42 and 43 and the second insulating layer 60 and the methods of exposing the first portions 42 of the second conductor pattern 41 out of the second insulating layer 60 are as same as the methods described above, so I will not describe the detail again. 0040 If the method of the present invention were applied to make interconnections, such as golden fingers or bonding pads, please refer to FIG. 16, it would simply plate NiAu layers 60 on the exposed parts of the first portions 22. 0041 The advantages of the present invention are: 0042 1. The dimensions of the vias at the insulating layer 30 for receiving the first portions 22 therein is smaller than the dimensions of the conventional plated vias (such as blind via, buried via or plated through hole) and no land is needed on the conductor pattern to connect the plated via with the conductor pattern, i.e., there will be a landless conductor pattern being provided on the PCB of the present invention, so that the PCB can be designed as smaller as possible. 0043 2. The solid first portions have fewer problems to overcome in connection with the conductor pattern and in registration such that the PCB will has lower proportion of defective. In addition, we also found the solid first portions have well capacity of thermal strength such that they are not easily broken and they also have well adhesion with the conductor pattern and the insulating layer. Most of all, the present method provides a higher reliability in manufacture. 0044 3. The method of the present invention is very simple and it can be applied to both in build-up processes and making the interconnections.