CROSS-REFERENCE TO RELATED APPLICATION 0001 This application claims the benefit of U.S. provisional application No. 60/281,146, filed on Apr. 3, 2001, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION 0002 1. Field of the Invention 0003 The invention relates to gold plating of conductor traces on printed circuit boards and the like. More particularly, the invention relates to electroless gold plating of copper conductors on printed circuit boards and the like for use in connection with bare die attach integrated circuit devices. 0004 2. Description of the Related Art 0005 Printed circuit boards (PCBs) upon which integrated circuits (ICs) are mounted are well known. Printed circuit boards can be made of various materials, including, but not limited to, epoxy glass and polyimide glass. Traditionally, encapsulated IC chips are mounted on substrates such as PCBs with lead fingers, which protrude from the encapsulated ICs, attached to conductive bond sites on the PCB in order to provide electrical paths between the PCB and circuitry within the IC chips. The bond sites on the PCB are electrically part of or are coupled to conductive traces that lead to other circuitry on the PCB and/or to contacts on the edges of the PCB for coupling to off-PCB circuitry. More recently, however, fabrication techniques are being used in which bare dies (i.e., not encapsulated) are bonded directly to PCBs. The bond pads on the top surface of the dies are then wire bonded to the bond sites on the PCB in essentially the same fashion that bond pads on dies are wire bonded to lead frames in traditional, encapsulated IC chips. 0006 There are several well known bare die attach techniques and assemblies, including assemblies commonly known as multichip (MCMs) and chip-on-board (COB) assemblies. FIG. 1 is a cross-sectional side view of an exemplary chip-on-board assembly 1. The assembly comprises a PCB 2 on which a bare die 3 has been adhered. Bond pads on the top die surface have been wirebonded to contacts on the PCB by wirebonds 4. Finally the die, including the wirebonds 4, has been encapsulated within encapsulant 5 right on the PCB. 0007 These direct die attach assemblies as well as others typically require that the conductive traces, contact points and vias on the PCB be formed of gold plated copper. The gold plating must be of sufficient quality (having fine, uniform grains) and thickness (nominally 0.5 microns, which is about 20 micro-inches) to ensure excellent wire bondability and reliability during long term operation. 0008 Further, for bare die attach techniques, the copper on the PCB must be patterned prior to the gold plating process since gold and copper generally cannot be etched simultaneously with the same etchant. Consequently, performing the copper etching after the gold etching would undermine the gold layer and leave gold cantilevered over the copper, which is not an acceptable condition. Since the boards are patterned before the gold plating process, there typically will not be a continuous circuit path comprising all of the copper on the PCB and, thus, it is impossible, or at least impractical, to gold plate the copper by electroplating techniques. Accordingly, for bare die attach integrated circuits (as well as other integrated circuits), the gold plating process typically is an electroless process, i.e., either immersion, autocatalytic or both. In addition, it typically is desirable to form a barrier layer between the copper and the gold to prevent migration of the copper into the gold and also to ensure excellent adhesion of the gold to the copper. 0009 Multi-layer printed circuit boards commonly include conductively plated through holes to provide interconnection between conductive traces on the various layers of the board. Such through holes may run completely through the PCB assembly from one surface to the opposite surface and, thus, be open at both ends. However, techniques are now well established for providing blind vias in multi-layer printed circuit boards. Blind vias are open at one end but terminate short of the opposite surface of the PCB at one of the intermediate layers. Blind vias conserve real-estate on the circuit board since they do not consume space on layers on which they do not serve an electrical function. Also in furtherance of the ever present desire to reduce the size of circuitry, it is desirable for the through holes and blind vias to have as small a diameter as possible. Particularly, blind vias with diameter to depth aspect ratios of 1:1 up to 1:5 or greater are known in the prior art. However, it has been found to be rather difficult to electrolessly gold plate blind vias with aspect ratios of 1:1 or greater. Particularly, it is difficult to guarantee that sufficient exchange of the electroless nickel and/or gold plating solutions into and out of the blind vias to fully plate the surfaces of the blind vias. 0010 Therefore, it is an object of the present invention to provide a new and/or improved technique for electroless gold plating of conductive traces on printed circuit boards and the like.

SUMMARY OF THE INVENTION 0011 The invention is a technique for electrolessly gold plating copper patterns on a PCB or the like that is particularly suited for use in connection with the manufacture of PCBs upon which bare dies will be mounted. Starting with a printed circuit board (PCB) with patterned copper on its surface and in any vias, one particular, complete process in accordance with the current embodiment of the present invention comprises the following steps: 0012 1. Cleaning the PCB in a bath of cleaning solution with the application of ultrasonic agitation with the PCB initially oriented vertically and gradually moved to a 45 angle to the ground followed by rinsing in a high pressure rinse with de-ionized water; 0013 2. Immersing the PCB in a 10% solution of sulfuric acid with the application of ultrasonic and mechanical agitation (if the conductor spacing is less then 5 mils, the solution is reduced to approximately 1 to 5% sulfuric acid); 0014 3. Rinsing in overflowing de-ionized water; 0015 4. Immersing the PCB in a 5% solution of sulfuric acid with the application of ultrasonic and mechanical agitation. This second sulfuric acid wash preferably is not followed by a rinse; 0016 5. Plating the copper with palladium by immersing the PCB in a palladium activation solution at approximately 30 C. with the application of ultrasonic agitation for 5 seconds at 30 second intervals. The PCB should be initially positioned at a 45 angle and be flipped approximately half way through the process to the opposing 45 angle; 0017 6. Rinsing with de-ionized water in an overflowing beaker for approximately 30 seconds; 0018 7. Post dipping in a 1% solution of sulfuric acid to help eliminate bridge plating; 0019 8. Rinsing in overflowing de-ionized water; 0020 9. Immersing in a bath of electroless nickel at approximately 80 C. without ultrasonic agitation, but with mechanical agitation; 0021 10. Rinsing in overflowing de-ionized water; 0022 11. Nitrogen blow drying; 0023 12. Visually inspecting for full nickel coverage of the copper; 0024 13. Immersing in an approximately 30% solution of hydrochloric acid with manual agitation, followed by a overflowing de-ionized water rinse 0025 14. If full nickel coverage was not achieved, repeating steps 4 through 13; 0026 15. Immersing in a gold flash plating solution at approximately 90 and a pH of 4.5 to 4.7 to establish a first thin layer of electroless gold; 0027 16. Rinsing in overflowing de-ionized water; 0028 17. Immersing in an autocatalytic gold plating bath at approximately 70 C. for sufficient time to achieve the desired over all gold thickness; 0029 18. Rinsing in overflowing de-ionized water; 0030 19. Blow drying with dry nitrogen.

BRIEF DESCRIPTION OF THE DRAWINGS 0031 FIG. 1 is a cross-sectional side view of a chip-on-board integrated circuit device of the prior art. 0032

FIG. 2

a is a cross-sectional side view of a printed circuit board during a first phase of fabrication in accordance with the present embodiment of the invention. 0033

FIG. 2

b is a cross-sectional side view of a printed circuit board during a second phase of fabrication in accordance with the present embodiment of the invention. 0034

FIG. 2

c is a cross-sectional side view of a printed circuit board during a third phase of fabrication in accordance with the present embodiment of the invention. 0035

FIG. 2

d is a cross-sectional side view of a printed circuit board during a fourth phase of fabrication in accordance with the present embodiment of the invention. 0036

FIG. 2

e is a cross-sectional side view of a printed circuit board during a fifth phase of fabrication in accordance with the present embodiment of the invention. 0037 FIG. 3 is a flow diagram illustrating steps in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION 0038 The process of electrolessly gold plating the copper patterns on a printed board in accordance with the present invention comprises three broad steps. They are (1) nickel plating to achieve good adherence of the gold to the copper, (2) immersion plating with a thin layer of gold, and (3) building up the thickness of the gold by autocatalytic gold plating with a second layer of gold. The primary goal of the process is to obtain a complete and uniform layer of gold of the desired thickness, typically 40-60 micro-inches, that is well adhered to the copper, and is of sufficient quality (fine, uniform grains) to provide an excellent gold ball bonding surface. 0039 Each of the three general steps mentioned above comprise a plurality of substeps. 0040 Described below is one particular embodiment of the present invention. It should be understood that many, if not all, of the specific process parameters and steps can be modified without departing from the spirit of the present invention. Furthermore, the process described below is presented with various headings and subheadings with the intent of making this specification more easily readable and better organized. However, the headings and subheadings are not intended to suggest any particular necessary relationships of the steps to each other and are merely for organizational purposes. 0041 The process of the present invention assumes that a printed circuit board (PCB) with patterned copper plating and including blind vias has been prepared by a suitable technique and is essentially ready for gold plating in accordance with the present invention. FIG. 2A is a cross-sectional side view of a portion of such a PCB 10. It comprises multiple dielectric layers 12, 16 containing various copper patterns. Shown in FIG. 2A is a copper conductor 14 on dielectric layer 12 and a blind via 11 through dielectric layer 16 to the copper conductor 14 on underlying dielectric layer 12. The via is plated with copper 18. 0042 FIG. 3 is a flow diagram outlining the steps set forth below and can be referenced as needed. However, the flowchart is not specifically referenced below. 0043 In most, if not all, known techniques for forming copper traces on a PCB, the copper has likely been etched and developed one or more times using different etching and developing solutions which should be thoroughly removed from the PCB prior to adding any additional plating materials. 0044 1. Nickel Plating 0045 Before the copper can be plated with nickel, it should be cleaned, rinsed and activated. Activation involves replacement of any copper oxide layer that has formed on top of the copper with a palladium layer (the palladium layer will then eventually be replaced with the nickel layer). 0046 1.1 Clean and Rinse 0047 1.1.1 The printed circuit board with patterned copper is placed in a beaker containing a cleaning solution. In a preferred embodiment of the invention, the cleaning solution comprises a 25% solution of LAC-81 cleaning solution manufactured by Dynachem Products, Inc. of B.C., Canada and 75% de-ionized water. The solution should be maintained at about 55 C. In a preferred embodiment, the PCB is immersed in the cleaning solution for about 5 minutes during which time ultrasonic agitation is applied to the solution. In a preferred embodiment of the invention, the ultrasonic agitation is applied through an ultrasonic water jacket bath essentially comprising a metal tub within which the beaker containing the PCB is submerged. 0048 1.1.2 The ultrasonic cleaning is followed by a high pressure spray rinse of nitrogen and de-ionized water. Preferably, the board initially is oriented vertically (i.e., with the planar surfaces of the PCB oriented at a 90 angle to the floor) and gradually rotated to a 45 angle during the course of the rinse. The pressure spray can be at a pressure of approximately 30 pounds per square inch for approximately 1 minute. 0049 1.1.3 The PCB is then further rinsed for 30 seconds in a beaker with overflowing de-ionized water flowing at a rate of approximately 1 gallon per minute. 0050 1.1.4 The copper is then activated (i.e., any copper oxide layer that has formed on the copper is removed) in a solution of sulfuric acid and de-ionized water. If the copper spacing on the PCB is greater than or equal to 5 mils (1 mil{fraction (1/1000)} of an inch), the solution may be 10% sulfuric acid to 90% de-ionized water. If the line spacing is less than 5 mil, the solution should be between 1 and 5% sulfuric acid. The printed circuit board is immersed in the solution at a 90 angle to the floor for approximately 2 minutes at room temperature. The board is mechanically agitated as well as ultrasonically agitated for the duration of the immersion. 0051 1.1.5 The board is then rinsed again with a combination of nitrogen and de-ionized water for approximately 1 minute with the pressure of approximately 30 pounds per square inch. The board is initially oriented at 90 and gradually rotated to 45. 0052 1.1.6 Next, the board is again immersed in sulfuric acid, this time a 5% solution, for approximately 1 minute at room temperature. No rinse is performed after this step. 0053 1.2 Palladium Activation 0054 1.2.1 In a preferred embodiment of the invention, directly after the 5% sulfuric acid immersion, the PCB is immersed in a solution of KAT 450, which is a palladium activation solution manufactured for the semiconductor fabrication industry by Uyemura International Corporation of Ontario, Calif., USA. However, other palladium activation solutions are available and can be used. For fine line PCBs (i.e., generally less than 5 mil spacing) a solution of 3 ml of KAT 450 per liter of de-ionized water and 10% sulfuric acid is preferred. 0055 The palladium layer is needed because nickel will not bond well to bare copper because bare copper is extremely reactive with oxygen and begins oxidizing immediately even in low oxygen environments. The palladium layer essentially replaces the copper oxide layer and then the palladium layer will eventually be replaced by the nickel layer. 0056 The process is carried out preferably at a controlled temperature of approximately 30 C. and with application of ultrasonic agitation. The ultrasonic agitation helps solution exchange in the blind vias, which has been a particular problem in the prior art, especially with respect to vias with high aspect ratios. However, the ultrasonic agitation should be precisely controlled since too much ultrasonic agitation provides too much palladium activation, which could lead to bridge plating of the palladium (i.e., palladium bridging the gap between two adjacent copper traces that are not intended to be electrically connected). If not enough ultrasonic agitation is applied, the palladium plating will be insufficient, particularly in the blind vias. 0057 In a preferred embodiment of the invention, the ultrasonic agitation is applied for the first 5 seconds of immersion of the board followed by 25 seconds with the ultrasonic agitation turned off, followed by another 5 seconds of ultrasonic agitation, followed by 25 seconds of no ultrasonic agitation. This pattern is repeated for the duration of the immersion. 0058 In a preferred embodiment of the invention, the PCB is immersed in the palladium activation solution with the PCB oriented at 45 to the floor. Half way through the process, the board is flipped to the opposing 45 angle to the floor. This flipping allows blind vias on opposing surfaces of the PCB to receive essentially equal treatment. In a preferred embodiment, the PCB is immersed in the palladium activation solution for approximately 3 minutes. 0059 1.2.2 The palladium activation is followed by 30 seconds of flowing de-ionized water rinse at a rate of approximately one gallon per minute. 0060 1.2.3 Next, in order to thin out the palladium layer and make it uniform, the PCB immersed in a sulfuric acid post dip for about one minute. The solution for this step is preferably 1% sulfuric acid to 99% de-ionized water. The board is oriented at a 90 angle. 0061 1.2.4 The post dip is followed by 30 seconds of rinsing with over flowing de-ionized water at a rate of approximately 1 gal. per minute. 0062 FIG. 2B shows the PCB after the palladium activation portion of the process. As shown, a thin layer of palladium 20 has been plated on top of the copper layer 18. 0063 1.3 Immersion Electroless Nickel Plating 0064 The PCB is now activated and prepared for electroless nickel plating. 0065 1.3.1 The board is immersed into a bath of electroless nickel plating solution. In one preferred embodiment of the invention, the solution is Nimuden NPR-4 produced by Uyemura International Corporation. The solution should be heated to 80 C. and the immersion should last approximately 30 minutes. In a preferred embodiment of the present invention, the board is oriented at a 45 angle and is coupled to a cathode rocker arm which continuously mechanically moves the board to and for in the solution. (Note that the term cathode rocker arm describes a well known device in the art and that the term cathode should not be taken to indicate that the process is electrolytic; as noted, the process is an electroless plating process). Preferably, no ultrasonics are applied during this step. 0066 Tiny hydrogen gas bubbles tend to form in the electroless nickel plating solution. Such bubbles have a tendency to become trapped in blind vias and, hence, prevent the nickel solution from achieving full penetration into such blind vias and prevent spent solution from exiting the blind vias. It is believed that the mechanical agitation and the 45 orientation of the board are instrumental in preventing such hydrogen bubbles from becoming trapped in the blind vias. 0067 1.3.2 The electroless nickel plating is followed by a one minute flowing de-ionized water rinse at a rate of one gallon per minute. 0068 1.3.3 The rinse is then followed by a dry nitrogen blow dry. 0069 1.3.4 At this point, the PCB is removed from processing for visual inspection to determine if the nickel plating has fully covered the copper on the PCB. Preferably, this is done under about 10 magnification. 0070 1.3.5 Whether or not the part passes this inspection, it may be immersed in a solution of 30% hydrochloric acid (HCl) to 70% de-ionized water for three minutes with mechanical agitation of the board. The purpose of the hydrochloric acid wash is to reactivate the palladium for additional nickel plating, if full coverage has not been achieved, or to reactivate the nickel for the electroless gold plating, as the case may be. Particularly, because the Palladium and/or nickel plating has a tendency to begin oxidizing immediately, it is generally believed necessary that, upon completion of the nickel plating step, the part must immediately be gold plated to minimize the amount of oxidation of the nickel that occurs before the gold is plated. This step reactivates the nickel (or any exposed palladium), thereby providing the ability to take the time necessary to remove the part from the fabrication process for the visual inspection of step 1.3.4. 0071 1.3.6 Again, regardless whether or not the part passed visual inspection, the hydrochloric acid wash is followed by one minute of flowing de-ionized water rinse. 0072 1.3.7 If it is determined in step 1.3.4 that the nickel plating did not fully cover the copper on the PCB, then steps 1.1.6 through 1.3.6 are repeated. 0073 FIG. 2C shows the PCB after the nickel plating portion of the process is completed. As shown, the thin layer of palladium 20 from FIG. 2B has been replaced with a layer of nickel 22. 0074 2. Immersion Gold Plating 0075 The PCB is now ready for the first, immersion gold plating step. 0076 2.1 While the first immersion gold plating step can be carried out using any number of available immersion gold plating solutions, in a preferred embodiment of the invention, the solution is Aruna 511 immersion gold produced by Uyemura International Corporation. Preferably, the solution is heated to 90 C. However, on the way up to 90 C., its pH is checked at approximately 70 C. It is preferable to check the pH at 70 C. because most pH meters will be rendered inoperable or, at least, adversely affected, if exposed to 90 C. temperatures. Also, pH testing at room temperature will not give an accurate reading of the pH of the solution at 90 C. 0077 The pH should be in the range of approximately 4.5 to 4.7. If it is not within that range, it needs to be adjusted. Preferably, if the pH is too low, it is raised by adding to the solution a one to one mixture of 30% ammonium hydroxide and de-ionized water. If the pH is too high, preferably, it is lowered with Aruna acid salts or a citric acid solution. 0078 The plating rate for Aruna 511 at 90 C. is approximately 0.2 to 0.4 micro-inches per minute. A layer of approximately 6 to 8 micro-inches of the immersion gold is preferred. Accordingly, this first gold plating step preferably is carried out for approximately 15 minutes. Preferably, no ultrasonic agitation is applied during this step. 0079 2.2 The immersion is then followed by a one minute flowing de-ionized water rinse. 0080 FIG. 2D shows the PCB after this step. As shown, a thin layer of gold 24 has been plated on top of the nickel layer 22. 0081 3. Autocatalytic Gold Plating 0082 The PCB is now ready for the second, autocatalytic gold plating step. 0083 3.1 Again, any number of autocatalytic gold plating solutions that are suitable for use in the present invention are available on the market. In one preferred embodiment of the invention, the solution is NEORUM TWB produced by Uyemura International Corporation. The NEORUM TWB bath should be heated to approximately 70 C. The board should be oriented at a 90 angle to the floor. No mechanical or ultrasonic agitation should be applied during this step. Particularly, it has been found that there is a tendency for comet tailing to occur during autocatalytic gold plating. Comet tailing is a phenomenon in which the gold plating leaves a streak of unplated, or at least much more thinly plated, gold near through holes and vias in the PCB. The name comes from the fact that the appearance under magnification when this occurs looks like a comet tail flowing away from the via. 0084 The plating rate for NEORUM TWB at 70 is approximately 40 micro-inches per hour. In order to provide sufficient gold for the formation of high reliability wirebonding, a gold layer of at least 20 micro-inches is desired, and preferably about 40-50 micro-inches. Accordingly, the PCB should be processed in the autocatalytic bath for approximately one hour. 0085 3.2 The autocatalytic gold bath is followed by 5 minutes of over flowing de-ionized water rinse. 0086 3.3 The process is completed with a dry nitrogen blow dry of the part. 0087 FIG. 2E shows the PCB after the autocatalytic gold plating step. As shown, additional gold layer 26 has been plated on top of the first gold layer 24.

Conclusion 0088 Empirical testing has established that the above identified technique provides a highly suitable surface for wirebonding. For instance, Table 1 shows the results of destructive pull tests of wirebonds on a PCB fabricated generally in accordance with the embodiment of the present invention described above. Tests were performed for various gold layer thicknesses, namely, 0.4 microns, 0.65 microns and 0.9 microns. 1Failures inDestructive Pull Test PullnondestructiveStrength in gramsAuNumber ofpull test at 2.48Post ThermalThickness, PMBondsgrams forceAs BondedAging0.40129110.69.80.65149010.010.10.9013809.410.6

0089 The destructive pull test data is based on the average of approximately 70 bonds. Standard deviations are about 10-12% for all samples. The aging employed for the post thermal aging test comprised heating at 150 C. for 160 hours prior to the destructive pull test. 0090 It is believed that the ultrasonic agitation and/or the vigorous cleaning and rinsing steps are instrumental in achieving these excellent pull strength results. 0091 Having thus described a few particular embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.