BACKGROUND OF THE INVENTION 0001 1. Field of the Invention 0002 The present invention relates to an isolation technology employed in the semiconductor process, and more particularly to a method for forming polysilicon-filled trench isolations. 0003 2. Description of the Prior Art 0004 Shallow trench isolation (STI) has replaced LOCOS as the dominant isolation technique for CMOS at the 0.25 m technology node. To date STI has facilitated the continued scaling of device and isolation widths commensurate with the design rule. While the channel edge effect, such as the fringing gate-to-channel electric field, will strongly increase with reducing feature size. The fringing gate-to-channel electric field significantly lowers the threshold voltage at the edge of the channel on the 100-nm scale size. This results in increased off-state current and threshold voltage roll-off in narrow devices, which would increase the stand-by power consumption, both undesirable impacts on IC product design. A method for inserting a conductive field plate into the trench, such as a polysilicon field plate, is proposed to minimize the gate-to-channel fringing effect. FIG. 1 shows schematically the gate-to-channel fringing fields indicated by the dotted line 1 and the mechanism by which the polysilicon-filled trench 2 reduces the impact of these fields. In general, a silicon dioxide layer 3 is formed over the polysilicon-filled trench 2, whereby when an operational voltage is applied on the polysilicon gate 4, the generated electric field is partially directed to the space between the polysilicon gate 4 and the polysilicon-filled trench 2. Therefore, the gate-to-channel fringing field effect is reduced. 0005 FIG. 2A to FIG. 2D shows various steps for forming a prior polysilicon-filled shallow trench isolation device. In FIG. 2A, a silicon substrate 100 with a pad oxide layer 101 formed thereon is firstly provided. Next, a silicon nitride layer 102 is formed on the pad oxide layer 101. Then, forming a plurality of shallow trench isolations in the silicon substrate 100 by way of anisotropically etching. Following, forming an oxide liner layer 103 on the surface of each of the shallow trench isolations. Thereafter, depositing a polysilicon layer 104 on the silicon nitride layer 102 to fill each of the shallow trench isolations. Planarizing the polysilicon layer 104 until the silicon nitride layer 102 by way of chemical mechanical polishing method. Then, referring to FIG. 2A, etching back the polysilicon 104 filled in the shallow trench isolation to further recess the polysilicon 104. Subsequently, in FIG. 2B, proceeding polysilicon oxidation process to form a silicon dioxide cap layer 105 on the top of the polysilicon 104 filled in the shallow trench isolation. Then, sequentially removing the silicon nitride layer 102 and the pad oxide layer 101 to form polysilicon-filled shallow trench isolation with a silicon dioxide cap layer 105, as shown in FIG. 2C. 0006 Continuously, referring to FIG. 2C, forming a photoresist layer 106 on the silicon substrate 100 and then performing channel implantation to adjust the threshold voltage. Following, referring to FIG. 2D, forming a gate oxide layer 107 on the silicon substrate 100 and then, a polysilicon gate layer 108 on the gate oxide layer 107 and the silicon dioxide cap layer 105. Finally, performing ion implantation to form a source/drain (not shown) beside each side of the polysilicon gate 108 in the silicon substrate 100 between each pair of the shallow trench isolations. 0007 However, there are some disadvantages existing in the prior method for forming polysilicon-filled shallow trench isolations, as follows: 0008 1. The time for the polysilicon oxidation to form the silicon dioxide cap layer 105 is long, and thus the lateral oxidation of the channel 109 is easily happened to narrow the width of the channel 109. 0009 2. The silicon dioxide cap layer 105 on the polysilicon-filled shallow trench isolation is easily etched away by acidic solutions for stripping away photoresist layers used for several wells/Vth implantations, and even exposing the polysilicon 104 filled in the shallow trench isolation. As a result, the polysilicon gate 108 will contact with the polysilicon 104 filled in the shallow trench isolation. 0010 Accordingly, it is an intention to provide a method for forming polysilicon-filled shallow trench isolation with a protective cap layer formed thereon to overcome the drawbacks encountered in the prior method.

SUMMARY OF THE INVENTION 0011 It is an objective of the present invention to provide a method for forming polysilicon-filled trench isolations, in which using nitrogen implantation to amorphize the top portion of polysilicon filled in the trench isolation to form a nitrogen-implanted region. The nitrogen-implanted region reduces the polysilicon oxidation time for forming an oxynitride cap layer from the nitrogen-implanted region than a silicon dioxide cap layer, and thus reduces the channel edge narrowing effect during the polysilicon oxidation. 0012 Another objective of the present invention is to provide a method for forming polysilicon-filled trench isolation with an oxynitride cap layer formed thereon. The oxynitride cap layer provides better erosive resistance to acidic solutions for stripping away photoresist layers used for several wells/Vth implantations than a silicon dioxide cap layer. And, the oxynitride cap layer reduces the gate-to-channel fringing field because its dielectric constant is higher than that of silicon dioxide. 0013 In order to achieve the above objectives, the present invention provides a method for forming polysilicon-filled trench isolations. At first, a silicon substrate having a pad dielectric layer formed thereon is provided. Next, forming a polishing stopping layer over the pad dielectric layer. Anisotropically etching the polishing stopping layer, the pad dielectric layer and the silicon substrate to form a trench isolation in the silicon substrate. Subsequently, forming a liner layer over the surface of the trench isolation. Afterward, forming a polysilicon layer over the polishing stopping layer and the liner layer. Then, planarizing the polysilicon layer until exposing the polishing stopping layer. Following, etching back a partial portion of the polysilicon layer. Subsequently, performing ion implantation to form an ion-implanted layer on the polysilicon layer. Proceeding a first thermal oxidation so that the ion-implanted layer forms a cap oxide layer. Finally, sequentially removing said polishing stopping layer and said pad dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS 0014 The present invention can be best understood through the following description and accompanying drawings, wherein: 0015 FIG. 1 shows a schematic cross-sectional view of a MOSFET device perpendicular to the direction of current flow. The gate-to-channel fringing field is illustrated. 0016 FIG. 2A to FIG. 2D shows schematic cross-sectional views of various steps for forming a prior polysilicon-filled shallow trench isolation device; and 0017 FIG. 3A to FIG. 3H shows schematic cross-sectional views of various steps for forming polysilicon-filled trench isolation according to one embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 0018 Referring to FIG. 3A, a silicon substrate 300 is firstly provided. Then, forming a pad dielectric layer 301 on the substrate 300. The pad dielectric layer 301 can be formed of a silicon dioxide layer by way of thermal oxidation. Next, a polishing stopping layer 302 is formed on the pad dielectric layer 301. The polishing stopping layer 302 can be formed of silicon nitride by way of low pressure chemical vapor deposition method (LPCVD) using the reaction gases of SiH2Cl2 and NH3 at the temperature of about 700800 C. under the operational pressure of about 0.11 torr. Alternately, the polishing stopping layer 302 of silicon nitride can be formed of plasma enhanced chemical vapor deposition method (PECVD) using the reaction gases of SiH4, NH3 and N2 at the temperature of about 250400 C. under the operational pressure of about 15 torr. Thereafter, anisotropically etching the polishing stopping layer of silicon nitride 302, the pad dielectric layer of silicon dioxide 301 and the silicon substrate 300 to form a plurality of trench isolations 303 in the silicon substrate 300. 0019 Referring to FIG. 3B, a liner layer 304 is formed on the surface of each of the trench isolations 303. The liner layer 304 can be formed of silicon dioxide by way of thermal oxidation. Then, referring to FIG. 2C, a polysilicon layer 305 is formed on the polishing stopping layer of silicon nitride 302 to fill each of the trench isolations 303. The polysilicon layer 305 can be formed of low pressure chemical vapor deposition method using SiH4 (silane) as the reaction gas at the temperature of about 600650 C. under the operational pressure of about 0.30.6 torr. The polysilicon layer 305 also can be formed of in-situ N polysilicon by way of low pressure chemical vapor deposition method using the reaction gases of SiH4 and 1 Vol. % AsH3. 0020 Referring to FIG. 3D, planarizing the polysilicon layer 305 by way of chemical mechanic polishing method until the polishing stopping layer of silicon nitride 302. Then, referring to FIG. 3E, etching back the polysilicon layer 305 to further recess the polysilicon layer 305 while maintaining the level of the polysilicon layer 305 to exceed the surface of the silicon substrate 300. The process for etching back the polysilicon layer 305 can be performed by way of reactive ion etching method using the source gas selected from the group consisting of Cl2, HCl and SiCl4. 0021 Referring to FIG. 3F, proceeding nitrogen implantation to amorphize the top portion of the polysilicon layer 305 to form a nitrogen-implanted region 306. The nitrogen implantation can be performed using the source gas, such as N2 and NH3, with the dosage of about 51014 to about 51016 ions/cm2, at the implanting energy of about 10 KeV. 0022 Referring to FIG. 3G, proceeding polysilicon oxidation by way of thermal oxidation, such as dry oxidation at the temperature of about 1000 C. to form an oxynitride cap layer 307 from the nitrogen-implanted region 306. Then, removing the polishing stopping layer of silicon nitride 302 by way of wet dip etching with aqueous H3PO4 solution. Following, removing the pad dielectric layer of silicon dioxide 301 by wet dip etching with aqueous HF solution. Thereby, polysilicon-filled trench isolation with an oxynitride cap layer 307 is provided. 0023 Referring to FIG. 3H, forming a photoresist layer on the silicon substrate 300 to proceed channel implantation so as to adjust the threshold voltage Vth. Thereafter, the photoresist layer is stripped away with acidic solution. Subsequently, forming a gate oxide layer 308 on the silicon substrate 300, and then forming a polysilicon gate layer 309 on the gate oxide layer 308 and the oxynitride cap layer 307. Finally, using ion implantation to form a source/drain beside each side of the polysilicon gate layer 309 in the silicon substrate 300. Thereby, a plurality of polysilicon-filled STI devices are obtained. 0024 In view of the foregoing, the top portion of the polysilicon layer 305 is amorphized to form a nitrogen-implanted region 306. Therefore, the polysilicon oxidation time to oxidize the nitrogen-implanted region 306 is reduced, and thus the lateral oxidation of the channel edge is also reduced to prevent the channel width from narrowing. The oxynitride cap layer 307 provides better erosive resistance to the acidic solution used for stripping away the photoresist layer than that of silicon dioxide. Thus, the oxynitride cap layer 307 acts as a protection layer of the polysilicon layer 305 filled in the trench isolation to prevent it from being exposed. Besides, the oxynitride cap layer 307 also reduces the gate-to-channel fringing field because its dielectric constant is higher than that of silicon dioxide. 0025 In the preferred embodiments of the present invention, using nitrogen implantation to amorphize the top portion of the polysilicon layer 305, so as to reduce its oxidation time. However, any kind of ion source which can amorphize the top portion of the polysilicon layer 305, and the subsequent oxidized cap layer provides a higher dielectric constant than silicon dioxide to reduce the gate-to-channel fringing effect, is suitable for the present ion implantation except for nitrogen implantation. 0026 The preferred embodiments are only used to illustrate the present invention, not intended to limit the scope thereof. Many modifications of the preferred embodiments can be made without departing from the spirit of the present invention.