CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part of U.S. patent application Ser. No. 11/075,395, filed Mar. 7, 2005, which claims the benefit of U.S. Provisional Application No. 60/550,668, filed Mar. 5, 2004 and U.S. Provisional Application No. 60/575,595, filed May 28, 2004. The present application also claims the benefit of U.S. Provisional Application No. 60/588,244, filed Jul. 15, 2004, which is incorporated in its entirety by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to memory modules of a computer system, and more specifically to devices and methods for improving the performance, the memory capacity, or both, of memory modules.

2. Description of the Related Art

Certain types of memory modules comprise a plurality of dynamic random-access memory (DRAM) devices mounted on a printed circuit board (PCB). These memory modules are typically mounted in a memory slot or socket of a computer system (e.g., a server system or a personal computer) and are accessed by the processor of the computer system. Memory modules typically have a memory configuration with a unique combination of rows, columns, and banks which result in a total memory capacity for the memory module.

For example, a 512-Megabyte memory module (termed a â€œ512-MBâ€ memory module, which actually has 2²⁹or 536,870,912 bytes of capacity) will typically utilize eight 512-Megabit DRAM devices (each identified as a â€œ512-Mbâ€ DRAM device, each actually having 2²⁹or 536,870,912 bits of capacity). The memory cells (or memory locations) of each 512-Mb DRAM device can be arranged in four banks, with each bank having an array of 2²⁴(or 16,777,216) memory locations arranged as 2¹³rows and 2¹¹columns, and with each memory location having a width of 8 bits. Such DRAM devices with 64M 8-bit-wide memory locations (actually with four banks of 2²⁷or 134,217,728 one-bit memory cells arranged to provide a total of 2²⁶or 67,108,864 memory locations with 8 bits each) are identified as having a â€œ64 MbÃ—8â€ or â€œ64MÃ—8-bitâ€ configuration, or as having a depth of 64M and a bit width of 8. Furthermore, certain commercially-available 512-MB memory modules are termed to have a â€œ64MÃ—8-byteâ€ configuration or a â€œ64MÃ—64-bitâ€ configuration with a depth of 64M and a width of 8 bytes or 64 bits.

Similarly, a 1-Gigabyte memory module (termed a â€œ1-GBâ€ memory module, which actually has 2³⁰or 1,073,741,824 bytes of capacity) can utilize eight 1-Gigabit DRAM devices (each identified as a â€œ1-Gbâ€ DRAM device, each actually having 2³⁰or 1,073,741,824 bits of capacity). The memory locations of each 1-Gb DRAM device can be arranged in four banks, with each bank having an array of memory locations with 2¹⁴rows and 2¹¹columns, and with each memory location having a width of 8 bits. Such DRAM devices with 128M 8-bit-wide memory locations (actually with a total of 2²⁷or 134,217,728 memory locations with 8 bits each) are identified as having a â€œ128 MbÃ—8â€ or â€œ128MÃ—8-bitâ€ configuration, or as having a depth of 128M and a bit width of 8. Furthermore, certain commercially-available 1-GB memory modules are identified as having a â€œ128MÃ—8-byteâ€ configuration or a â€œ128MÃ—64-bitâ€ configuration with a depth of 128M and a width of 8 bytes or 64 bits.

The commercially-available 512-MB (64MÃ—8-byte) memory modules and the 1-GB (128MÃ—8-byte) memory modules described above are typically used in computer systems (e.g., personal computers) which perform graphics applications since such â€œÃ—8â€ configurations are compatible with data mask capabilities often used in such graphics applications. Conversely, memory modules with â€œÃ—4â€ configurations are typically used in computer systems such as servers which are not as graphics-intensive. Examples of such commercially available â€œÃ—4â€ memory modules include, but are not limited to, 512-MB (128MÃ—4-byte) memory modules comprising eight 512-Mb (128 MbÃ—4) memory devices.

The DRAM devices of a memory module are generally arranged as ranks or rows of memory, each rank of memory generally having a bit width. For example, a memory module in which each rank of the memory module is 64 bits wide is described as having an â€œÃ—64â€ organization. Similarly, a memory module having 72-bit-wide ranks is described as having an â€œÃ—72â€ organization.

The memory capacity of a memory module increases with the number of memory devices. The number of memory devices of a memory module can be increased by increasing the number of memory devices per rank or by increasing the number of ranks. For example, a memory module with four ranks has double the memory capacity of a memory module with two ranks and four times the memory capacity of a memory module with one rank. Rather than referring to the memory capacity of the memory module, in certain circumstances, the memory density of the memory module is referred to instead.

During operation, the ranks of a memory module are selected or activated by control signals that are received from the processor. Examples of such control signals include, but are not limited to, rank-select signals, also called chip-select signals. Most computer and server systems support one-rank and two-rank memory modules. By only supporting one-rank and two-rank memory modules, the memory density that can be incorporated in each memory slot is limited.

SUMMARY OF THE INVENTION

In certain embodiments, a memory module is connectable to a computer system. The memory module comprises a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.

In certain embodiments, a method utilizes a memory module in a computer system. The method comprises coupling the memory module to the computer system. The memory module comprises a plurality of memory devices arranged in a first number of ranks. The method further comprises inputting a first set of control signals to the memory module. The first set of control signals corresponds to a second number of ranks smaller than the first number of ranks. The method further comprises generating a second set of control signals in response to the first set of control signals. The second set of control signals corresponds to the first number of ranks.

In certain embodiments, a memory module is connectable to a computer system. The memory module comprises a plurality of memory devices arranged in a first number of ranks. The memory module comprises means for coupling the memory module to the computer system. The memory module further comprises means for inputting a first set of control signals to the memory module. The first set of control signals corresponds to a second number of ranks smaller than the first number of ranks. The memory module further comprises means for generating a second set of control signals in response to the first set of control signals. The second set of control signals corresponds to the first number of ranks.

In certain embodiments, a memory module is connectable to a computer system. The memory module comprises a first memory device having a first data signal line and a first data strobe signal line. The memory module further comprises a second memory device having a second data signal line and a second data strobe signal line. The memory module further comprises a common data signal line connectable to the computer system. The memory module further comprises an isolation device electrically coupled to the first data signal line, to the second data signal line, and to the common data signal line. The isolation device selectively alternates between electrically coupling the first data signal line to the common data signal line and electrically coupling the second data signal line to the common data signal line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A

schematically illustrates an exemplary memory module with four ranks of memory devices compatible with certain embodiments described herein.

FIG. 1B

schematically illustrates an exemplary memory module with two ranks of memory devices compatible with certain embodiments described herein.

FIG. 1C

schematically illustrates another exemplary memory module in accordance with certain embodiments described herein.

FIG. 2A

schematically illustrates an exemplary memory module which doubles the rank density in accordance with certain embodiments described herein.

FIG. 2B

schematically illustrates an exemplary logic element compatible with embodiments described herein.

FIG. 3A

schematically illustrates an exemplary memory module which doubles number of ranks in accordance with certain embodiments described herein.

FIG. 3B

schematically illustrates an exemplary logic element compatible with embodiments described herein.

FIG. 4A

shows an exemplary timing diagram of a gapless read burst for a back-to-back adjacent read condition from one memory device.

FIG. 4B

shows an exemplary timing diagram with an extra clock cycle between successive read commands issued to different memory devices for successive read accesses from different memory devices.

FIG. 5

shows an exemplary timing diagram in which the last data strobe of memory device â€œaâ€ collides with the pre-amble time interval of the data strobe of memory device â€œb.â€

FIG. 6A

schematically illustrates a circuit diagram of a conventional memory module showing the interconnections between the DQ data signal lines of two memory devices and their DQS data strobe signal lines.

FIG. 6B

schematically illustrates a circuit diagram of an exemplary memory module comprising an isolation device in accordance with certain embodiments described herein.

FIG. 6C

schematically illustrates an isolation device comprising a logic element which multiplexes the DQS data strobe signal lines from one another.

FIG. 6D

schematically illustrates an isolation device which multiplexes the DQS data strobe signal lines from one another and which multiplexes the DQ data signal lines from one another.

FIG. 6E

schematically illustrates an isolation device which comprises the logic element on the DQ data signal lines but not a corresponding logic element on the DQS data strobe signal lines.

FIG. 7

schematically illustrates an exemplary memory module in which a data strobe (DQS) pin of a first memory device is electrically connected to a DQS pin of a second memory device while both DQS pins are active.

FIG. 8

is an exemplary timing diagram of the voltages applied to the two DQS pins due to non-simultaneous switching.

FIG. 9

schematically illustrates another exemplary memory module in which a DQS pin of a first memory device is connected to a DQS pin of a second memory device.

FIG. 10

schematically illustrates an exemplary memory module in accordance with certain embodiments described herein.

FIGS. 11A and 11B

schematically illustrate a first side and a second side, respectively, of a memory module with eighteen 64MÃ—4 bit, DDR-1 SDRAM FBGA memory devices on each side of a 184-pin glass-epoxy printed circuit board.

FIGS. 12A and 12B

schematically illustrate an exemplary embodiment of a memory module in which a first resistor and a second resistor are used to reduce the current flow between the first DQS pin and the second DQS pin.

FIG. 13

schematically illustrates another exemplary memory module compatible with certain embodiments described herein.

FIG. 14

schematically illustrates a particular embodiment of the memory module schematically illustrated by

FIG. 13

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Most high-density memory modules are currently built with 512-Megabit (â€œ512-Mbâ€ ) memory devices wherein each memory device has a 64MÃ—8-bit configuration. For example, a 1-Gigabyte (â€œ1-GBâ€ ) memory module with error checking capabilities can be fabricated using eighteen such 512-Mb memory devices. Alternatively, it can be economically advantageous to fabricate a 1-GB memory module using lower-density memory devices and doubling the number of memory devices used to produce the desired word width. For example, by fabricating a 1-GB memory module using thirty-six 256-Mb memory devices with 64MÃ—4-bit configuration, the cost of the resulting 1-GB memory module can be reduced since the unit cost of each 256-Mb memory device is typically lower than one-half the unit cost of each 512-Mb memory device. The cost savings can be significant, even though twice as many 256-Mb memory devices are used in place of the 512-Mb memory devices.

Market pricing factors for DRAM devices are such that higher-density DRAM devices (e.g., 1-Gb DRAM devices) are much more than twice the price of lower-density DRAM devices (e.g., 512-Mb DRAM devices). In other words, the price per bit ratio of the higher-density DRAM devices is greater than that of the lower-density DRAM devices. This pricing difference often lasts for months or even years after the introduction of the higher-density DRAM devices, until volume production factors reduce the costs of the newer higher-density DRAM devices. Thus, when the cost of a higher-density DRAM device is more than the cost of two lower-density DRAM devices, there is an economic incentive for utilizing pairs of the lower-density DRAM devices to replace individual higher-density DRAM devices.

FIG. 1A

schematically illustrates an exemplary memory module 10 compatible with certain embodiments described herein. The memory module 10 is connectable to a computer system (not shown). The memory module 10 comprises a printed circuit board 20 and a plurality of memory devices 30 coupled to the printed circuit board 20. The plurality of memory devices 30 has a first number of memory devices. The memory module 10 further comprises a logic element 40 coupled to the printed circuit board 20. The logic element 40 receives a set of input control signals from the computer system. The set of input control signals correspond to a second number of memory devices smaller than the first number of memory devices. The logic element 40 generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.

In certain embodiments, as schematically illustrated in

FIG. 1A

, the memory module 10 further comprises a phase-lock loop device 50 coupled to the printed circuit board 20 and a register 60 coupled to the printed circuit board 20. In certain embodiments, the phase-lock loop device 50 and the register 60 are each mounted on the printed circuit board 20. In response to signals received from the computer system, the phase-lock loop device 50 transmits clock signals to the plurality of memory devices 30, the logic element 40, and the register 60. The register 60 receives and buffers a plurality of control signals, including address signals (e.g., bank address signals, row address signals, column address signals, gated column address strobe signals, chip-select signals), and transmits corresponding signals to the appropriate memory devices 30. In certain embodiments, the register 60 comprises a plurality of register devices. While the phase-lock loop device 50, the register 60, and the logic element 40 are described herein in certain embodiments as being separate components, in certain other embodiments, two or more of the phase-lock loop device 50, the register 60, and the logic element 40 are portions of a single component. Persons skilled in the art are able to select a phase-lock loop device 50 and a register 60 compatible with embodiments described herein.

In certain embodiments, the memory module 10 further comprises electrical components which are electrically coupled to one another and are surface-mounted or embedded on the printed circuit board 20. These electrical components can include, but are not limited to, electrical conduits, resistors, capacitors, inductors, and transistors. In certain embodiments, at least some of these electrical components are discrete, while in other certain embodiments, at least some of these electrical components are constituents of one or more integrated circuits.

Various types of memory modules 10 are compatible with embodiments described herein. For example, memory modules 10 having memory capacities of 512-MB, 1-GB, 2-GB, 4-GB, 8-GB, as well as other capacities, are compatible with embodiments described herein. In addition, memory modules 10 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits), are compatible with embodiments described herein. Furthermore, memory modules 10 compatible with embodiments described herein include, but are not limited to, single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs), small-outline DIMMs (SO-DIMMs), unbuffered DIMMs (UDIMMs), registered DIMMs (RDIMMs), fully-buffered DIMM (FBDIMM), mini-DIMMs, and micro-DIMMs.

In certain embodiments, the printed circuit board 20 is mountable in a module slot of the computer system. The printed circuit board 20 of certain such embodiments has a plurality of edge connections electrically coupled to corresponding contacts of the module slot and to the various components of the memory module 10, thereby providing electrical connections between the computer system and the components of the memory module 10.

Memory devices 30 compatible with embodiments described herein include, but are not limited to, random-access memory (RAM), dynamic random-access memory (DRAM), synchronous DRAM (SDRAM), and double-data-rate DRAM (e.g., DDR-1, DDR-2, DDR-3). In addition, memory devices 30 having bit widths of 4, 8, 16, 32, as well as other bit widths, are compatible with embodiments described herein. Memory devices 30 compatible with embodiments described herein have packaging which include, but are not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (Î¼BGA), mini-BGA (mBGA), and chip-scale packaging (CSP). Memory devices 30 compatible with embodiments described herein are available from a number of sources, including but not limited to, Samsung Semiconductor, Inc. of San Jose, Calif., Infineon Technologies AG of San Jose, Calif., and Micron Technology, Inc. of Boise, Id. Persons skilled in the art can select appropriate memory devices 30 in accordance with certain embodiments described herein.

In certain embodiments, the plurality of memory devices 30 are arranged in a first number of ranks. For example, in certain embodiments, the memory devices 30 are arranged in four ranks, as schematically illustrated by

FIG. 1A

. In other embodiments, the memory devices 30 are arranged in two ranks, as schematically illustrated by

FIG. 1B

. Other numbers of ranks of the memory devices 30 are also compatible with embodiments described herein.

In certain embodiments, the logic element 40 comprises a programmable-logic device (PLD), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a custom-designed semiconductor device, or a complex programmable-logic device (CPLD). In certain embodiments, the logic element 40 is a custom device. Sources of logic elements 40 compatible with embodiments described herein include, but are not limited to, Lattice Semiconductor Corporation of Hillsboro, Oreg., Altera Corporation of San Jose, Calif., and Xilinx Incorporated of San Jose, Calif. In certain embodiments, the logic element 40 comprises various discrete electrical elements, while in certain other embodiments, the logic element 40 comprises one or more integrated circuits. Persons skilled in the art can select an appropriate logic element 40 in accordance with certain embodiments described herein.

As schematically illustrated by

FIGS. 1A and 1B

, in certain embodiments, the logic element 40 receives a set of input control signals, which includes address signals (e.g., bank address signals, row address signals, column address signals, gated column address strobe signals, chip-select signals) and command signals (e.g., refresh, precharge) from the computer system. In response to the set of input control signals, the logic element 40 generates a set of output control signals which includes address signals and command signals.

In certain embodiments, the set of output control signals corresponds to a first number of ranks in which the plurality of memory devices 30 of the memory module 10 are arranged, and the set of input control signals corresponds to a second number of ranks per memory module for which the computer system is configured. The second number of ranks in certain embodiments is smaller than the first number of ranks. For example, in the exemplary embodiment as schematically illustrated by

FIG. 1A

, the first number of ranks is four while the second number of ranks is two. In the exemplary embodiment of

FIG. 1B

, the first number of ranks is two while the second number of ranks is one. Thus, in certain embodiments, even though the memory module 10 actually has the first number of ranks of memory devices 30, the memory module 10 simulates a virtual memory module by operating as having the second number of ranks of memory devices 30. In certain embodiments, the memory module 10 simulates a virtual memory module when the number of memory devices 30 of the memory module 10 is larger than the number of memory devices 30 per memory module for which the computer system is configured to utilize.

In certain embodiments, the computer system is configured for a number of ranks per memory module which is smaller than the number of ranks in which the memory devices 30 of the memory module 10 are arranged. In certain such embodiments, the computer system is configured for two ranks of memory per memory module (providing two chip-select signals CS₀, CS₁) and the plurality of memory modules 30 of the memory module 10 are arranged in four ranks, as schematically illustrated by

FIG. 1A

. In certain other such embodiments, the computer system is configured for one rank of memory per memory module (providing one chip-select signal CS₀) and the plurality of memory modules 30 of the memory module 10 are arranged in two ranks, as schematically illustrated by

FIG. 1B

In the exemplary embodiment schematically illustrated by

FIG. 1A

, the memory module 10 has four ranks of memory devices 30 and the computer system is configured for two ranks of memory devices per memory module. The memory module 10 receives row/column address signals or signal bits (A₀-A_n+1), bank address signals (BA₀-BA_m), chip-select signals (CS₀and CS₁), and command signals (e.g., refresh, precharge, etc.) from the computer system. The A₀-A_nrow/column address signals are received by the register 60, which buffers these address signals and sends these address signals to the appropriate ranks of memory devices 30. The logic element 40 receives the two chip-select signals (CS₀, CS₁) and one row/column address signal (A_n+1) from the computer system. Both the logic element 40 and the register 60 receive the bank address signals (BA₀-BA_m) and at least one command signal (e.g., refresh, precharge, etc.) from the computer system.

Logic Tables

Table 1 provides a logic table compatible with certain embodiments described herein for the selection among ranks of memory devices 30 using chip-select signals.

TABLE 1StateCS₀CS₁A_n+1CommandCS_0ACS_0BCS_1ACS_1B1010Active01112011Active1011301xActive00114100Active11015101Active1110610xActive1100711xx1111Note:1. Cs₀, CS₁, CS_0A, CS_0B, CS_1A, and CS_1Bare active low signals.2. A_n+1is an active high signal.3. â€˜xâ€™ is a Don't Care condition.4. Command involves a number of command signals that define operations such as refresh, precharge, and other operations.

In Logic State 1: CS₀is active low, A_n+1is non-active, and Command is active. CS_0Ais pulled low, thereby selecting Rank 0.

In Logic State 2: CS₀is active low, A_n+1is active, and Command is active. CS_0Bis pulled low, thereby selecting Rank 1.

In Logic State 3: CS₀is active low, A_n+1is Don't Care, and Command is active high. CS_0Aand CS_0Bare pulled low, thereby selecting Ranks 0 and 1.

In Logic State 4: CS₁is active low, A_n+1is non-active, and Command is active. CS_1Ais pulled low, thereby selecting Rank 2.

In Logic State 5: CS₁is active low, A_n+1is active, and Command is active. CS_1Bis pulled low, thereby selecting Rank 3.

In Logic State 6: CS₁is active low, A_n+1is Don't Care, and Command is active. CS_1Aand CS_1Bare pulled low, thereby selecting Ranks 2 and 3.

In Logic State 7: CS₀and CS₁are pulled non-active high, which deselects all ranks, i.e., CS_0A, CS_0B, CS_1A, and CS_1Bare pulled high.

The â€œCommandâ€ column of Table 1 represents the various commands that a memory device (e.g., a DRAM device) can execute, examples of which include, but are not limited to, activation, read, write, precharge, and refresh. In certain embodiments, the command signal is passed through to the selected rank only (e.g., state 4 of Table 1). In such embodiments, the command signal (e.g., read) is sent to only one memory device or the other memory device so that data is supplied from one memory device at a time. In other embodiments, the command signal is passed through to both associated ranks (e.g., state 6 of Table 1). In such embodiments, the command signal (e.g., refresh) is sent to both memory devices to ensure that the memory content of the memory devices remains valid over time. Certain embodiments utilize a logic table such as that of Table 1 to simulate a single memory device from two memory devices by selecting two ranks concurrently.

Table 2 provides a logic table compatible with certain embodiments described herein for the selection among ranks of memory devices 30 using gated CAS signals.

TABLE 2CS*RAS*CAS*WE*Density BitA₁₀CommandCAS0*CAS1*1xxxxxNOPxx0111xxNOP1100110xACTIVATE1100111xACTIVATE1101010xREAD0101011xREAD1001000xWRITE0101001xWRITE10001000PRECHARGE11001010PRECHARGE110010x1PRECHARGE110000xxMODE REG SET000001xxREFRESH00

In certain embodiments in which the density bit is a row address bit, for read/write commands, the density bit is the value latched during the activate command for the selected bank.

Serial-Presence-Detect Device

Memory modules typically include a serial-presence detect (SPD) device 70 (e.g., an electrically-erasable-programmable read-only memory or EEPROM device) comprising data which characterize various attributes of the memory module, including but not limited to, the number of row addresses the number of column addresses, the data width of the memory devices, the number of ranks, the memory density per rank, the number of memory devices, and the memory density per memory device. The SPD device 70 communicates this data to the basic input/output system (BIOS) of the computer system so that the computer system is informed of the memory capacity and the memory configuration available for use and can configure the memory controller properly for maximum reliability and performance.

For example, for a commercially-available 512-MB (64MÃ—8-byte) memory module utilizing eight 512-Mb memory devices each with a 64MÃ—8-bit configuration, the SPD device contains the following SPD data (in appropriate bit fields of these bytes):

- Byte 3: Defines the number of row address bits in the DRAM device in the memory module [13 for the 512-Mb memory device].
- Byte 4: Defines the number of column address bits in the DRAM device in the memory module [11 for the 512-Mb memory device].
- Byte 13: Defines the bit width of the primary DRAM device used in the memory module [8 bits for the 512-Mb (64MÃ—8-bit) memory device].
- Byte 14: Defines the bit width of the error checking DRAM device used in the memory module [8 bits for the 512-Mb (64MÃ—8-bit) memory device].
- Byte 17: Defines the number of banks internal to the DRAM device used in the memory module [4 for the 512-Mb memory device].

In a further example, for a commercially-available 1-GB (128MÃ—8-byte) memory module utilizing eight 1-Gb memory devices each with a 128MÃ—8-bit configuration, as described above, the SPD device contains the following SPD data (in appropriate bit fields of these bytes):

- Byte 3: Defines the number of row address bits in the DRAM device in the memory module [14 for the 1-Gb memory device].
- Byte 4: Defines the number of column address bits in the DRAM device in the memory module [11 for the 1-Gb memory device].
- Byte 13: Defines the bit width of the primary DRAM device used in the memory module [8 bits for the 1-Gb (128MÃ—8-bit) memory device].
- Byte 14: Defines the bit width of the error checking DRAM device used in the memory module [8 bits for the 1-Gb (128MÃ—8-bit) memory device].
- Byte 17: Defines the number of banks internal to the DRAM device used in the memory module [4 for the 1-Gb memory device].

In certain embodiments, the SPD device 70 comprises data which characterize the memory module 10 as having fewer ranks of memory devices than the memory module 10 actually has, with each of these ranks having more memory density. For example, for a memory module 10 compatible with certain embodiments described herein having two ranks of memory devices 30, the SPD device 70 comprises data which characterizes the memory module 10 as having one rank of memory devices with twice the memory density per rank. Similarly, for a memory module 10 compatible with certain embodiments described herein having four ranks of memory devices 30, the SPD device 70 comprises data which characterizes the memory module 10 as having two ranks of memory devices with twice the memory density per rank. In addition, in certain embodiments, the SPD device 70 comprises data which characterize the memory module 10 as having fewer memory devices than the memory module 10 actually has, with each of these memory devices having more memory density per memory device. For example, for a memory module 10 compatible with certain embodiments described herein, the SPD device 70 comprises data which characterizes the memory module 10 as having one-half the number of memory devices that the memory module 10 actually has, with each of these memory devices having twice the memory density per memory device.

FIG. 1C

schematically illustrates an exemplary memory module 10 in accordance with certain embodiments described herein. The memory module 10 comprises a pair of substantially identical memory devices 31, 33. Each memory device 31, 33 has a first bit width, a first number of banks of memory locations, a first number of rows of memory locations, and a first number of columns of memory locations. The memory module 10 further comprises an SPD device 70 comprising data that characterizes the pair of memory devices 31, 33. The data characterize the pair of memory devices 31, 33 as a virtual memory device having a second bit width equal to twice the first bit width, a second number of banks of memory locations equal to the first number of banks, a second number of rows of memory locations equal to the first number of rows, and a second number of columns of memory locations equal to the first number of columns.

In certain such embodiments, the SPD device 70 of the memory module 10 is programmed to describe the combined pair of lower-density memory devices 31, 33 as one virtual or pseudo-higher-density memory device. In an exemplary embodiment, two 512-Mb memory devices, each with a 128MÃ—4-bit configuration, are used to simulate one 1-Gb memory device having a 128MÃ—8-bit configuration. The SPD device 70 of the memory module 10 is programmed to describe the pair of 512-Mb memory devices as one virtual or pseudo-1-Gb memory device.

For example, to fabricate a 1-GB (128MÃ—8-byte) memory module, sixteen 512-Mb (128MÃ—4-bit) memory devices can be used. The sixteen 512-Mb (128MÃ—4-bit) memory devices are combined in eight pairs, with each pair serving as a virtual or pseudo-1-Gb (128MÃ—8-bit) memory device. In certain such embodiments, the SPD device 70 contains the following SPD data (in appropriate bit fields of these bytes):

- Byte 3: 13 row address bits.
- Byte 4: 12 column address bits.
- Byte 13: 8 bits wide for the primary virtual 1-Gb (128MÃ—8-bit) memory device.
- Byte 14: 8 bits wide for the error checking virtual 1-Gb (128MÃ—8-bit) memory device.
- Byte 17: 4 banks.

In this exemplary embodiment, bytes 3, 4, and 17 are programmed to have the same values as they would have for a 512-MB (128MÃ—4-byte) memory module utilizing 512-Mb (128MÃ—4-bit) memory devices. However, bytes 13 and 14 of the SPD data are programmed to be equal to 8, corresponding to the bit width of the virtual or pseudo-higher-density 1-Gb (128MÃ—8-bit) memory device, for a total capacity of 1-GB. Thus, the SPD data does not describe the actual-lower-density memory devices, but instead describes the virtual or pseudo-higher-density memory devices. The BIOS accesses the SPD data and recognizes the memory module as having 4 banks of memory locations arranged in 2¹³rows and 2¹²columns, with each memory location having a width of 8 bits rather than 4 bits.

In certain embodiments, when such a memory module 10 is inserted in a computer system, the computer system's memory controller then provides to the memory module 10 a set of input control signals which correspond to the number of ranks or the number of memory devices reported by the SPD device 70. For example, placing a two-rank memory module 10 compatible with certain embodiments described herein in a computer system compatible with one-rank memory modules, the SPD device 70 reports to the computer system that the memory module 10 only has one rank. The logic element 40 then receives a set of input control signals corresponding to a single rank from the computer system's memory controller, and generates and transmits a set of output control signals corresponding to two ranks to the appropriate memory devices 30 of the memory module 10. Similarly, when a two-rank memory module 10 compatible with certain embodiments described herein is placed in a computer system compatible with either one- or two-rank memory modules, the SPD device 70 reports to the computer system that the memory module 10 only has one rank. The logic element 40 then receives a set of input control signals corresponding to a single rank from the computer system's memory controller, and generates and transmits a set of output control signals corresponding to two ranks to the appropriate memory devices 30 of the memory module 10. Furthermore, a four-rank memory module 10 compatible with certain embodiments described herein simulates a two-rank memory module whether the memory module 10 is inserted in a computer system compatible with two-rank memory modules or with two- or four-rank memory modules. Thus, by placing a four-rank memory module 10 compatible with certain embodiments described herein in a module slot that is four-rank-ready, the computer system provides four chip-select signals, but the memory module 10 only uses two of the chip-select signals.

Memory Density Multiplication

In certain embodiments, two memory devices having a memory density are used to simulate a single memory device having twice the memory density, and an additional address signal bit is used to access the additional memory. Similarly, in certain embodiments, two ranks of memory devices having a memory density are used to simulate a single rank of memory devices having twice the memory density, and an additional address signal bit is used to access the additional memory. As used herein, such simulations of memory devices or ranks of memory devices are termed as â€œmemory density multiplication,â€ and the term â€œdensity transition bitâ€ is used to refer to the additional address signal bit which is used to access the additional memory.

In certain embodiments utilizing memory density multiplication embodiments, the memory module 10 can have various types of memory devices 30 (e.g., DDR1, DDR2, DDR3, and beyond). The logic element 40 of certain such embodiments utilizes implied translation logic equations having variations depending on whether the density transition bit is a row, column, or internal bank address bit. In addition, the translation logic equations of certain embodiments vary depending on the type of memory module 10 (e.g., UDIMM, RDIMM, FBDIMM, etc.). Furthermore, in certain embodiments, the translation logic equations vary depending on whether the implementation multiplies memory devices per rank or multiplies the number of ranks per memory module.

Table 3A provides the numbers of rows and columns for DDR-1 memory devices, as specified by JEDEC standard JESD79D, â€œDouble Data Rate (DDR) SDRAM Specification,â€ published February 2004, and incorporated in its entirety by reference herein.

TABLE 3A128-Mb256-Mb512-Mb1-Gb

Number of banks4444Number of row address bits12131314Number of column address bits for11111212â€œÃ—4â€ configurationNumber of column address bits for10101111â€œÃ—8â€ configurationNumber of column address bits for991010â€œÃ—16â€ configuration

As described by Table 3A, 512-Mb (128MÃ—4-bit) DRAM devices have 2¹³rows and 2¹²columns of memory locations, while 1-Gb (128MÃ—8-bit) DRAM devices have 2¹⁴rows and 2¹¹columns of memory locations. Because of the differences in the number of rows and the number of columns for the two types of memory devices, complex address translation procedures and structures would typically be needed to fabricate a 1-GB (128MÃ—8-byte) memory module using sixteen 512-Mb (128MÃ—4-bit) DRAM devices.

Table 3B shows the device configurations as a function of memory density for DDR2 memory devices.

TABLE 3BNumber ofNumber ofNumber ofPage SizeRowsColumnsInternal Banks(Ã—4s or Ã—8s)

256Mb131041 KB512Mb141041 KB1Gb141081 KB2Gb151081 KB4Gbto beto be81 KBdetermineddetermined

Table 4 lists the corresponding density transition bit for the density transitions between the DDR2 memory densities of Table 3B.

TABLE 4Density TransitionDensity Transition Bit256 Mb to 512 MbA₁₃512 Mb to 1 GbBA₂â€ƒ1 Gb to 2 GbA₁₄â€ƒ2 Gb to 4 Gbto be determined

Because the standard memory configuration of 4-Gb DDR2 SDRAM modules is not yet determined by the appropriate standards-setting organization, Tables 3B and 4 have â€œto be determinedâ€ in the appropriate table entries.

In certain embodiments, the logic translation equations are programmed in the logic element 40 by hardware, while in certain other embodiments, the logic translation equations are programmed in the logic element 40 by software. Examples 1 and 2 provide exemplary sections of Verilog code compatible with certain embodiments described herein. As described more fully below, the code of Examples 1 and 2 includes logic to reduce potential problems due to â€œback-to-back adjacent read commands which cross memory device boundaries or â€œBBARX.â€ Persons skilled in the art are able to provide additional logic translation equations compatible with embodiments described herein.

An exemplary section of Verilog code compatible with memory density multiplication from 512 Mb to 1 Gb using DDR2 memory devices with the BA₂density transition bit is listed below in Example 1. The exemplary code of Example 1 corresponds to a logic element 40 which receives one chip-select signal from the computer system and which generates two chip-select signals.

EXAMPLE 1

always @(posedge clk_in)â€ƒbeginâ€ƒâ€ƒrs0N_R <= rs0_in_N; â€ƒâ€ƒ// cs0â€ƒâ€ƒrasN_R <= ras_in_N;â€ƒâ€ƒcasN_R <= cas_in_N;â€ƒâ€ƒweN_R <= we_in_N;â€ƒend// Gated Chip Selects

assignpcs0a_1 = (~rs0_in_N & ~ras_in_N & ~cas_in_N)// ref,md reg set| (~rs0_in_N & ras_in_N & cas_in_N)// ref exit, pwr dn| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & a10_in)// pchg all

| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & ~a10_in & ~ba2_in)// pchg single bnk

| (~rs0_in_N & ~ras_in_N & cas_in_N & we_in_N â€ƒâ€ƒ& ~ba2_in)// activate| (~rs0_in_N & ras_in_N & ~cas_in_N â€ƒâ€ƒ& ~ba2_in)// xfr;assignpcs0b_1 = (~rs0_in_N & ~ras_in_N & ~cas_in_N)// ref,md reg set| (~rs0_in_N & ras_in_N & cas_in_N)// ref exit, pwr dn| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & a10_in)// pchg all

| (~rs0_in_N & ~ras_in_N & cas_in_N & ~we_in_N & ~a10_in & ba2_in)// pchg single bnk

| (~rs0_in_N & ~ras_in_N & cas_in_N & we_in_N â€ƒâ€ƒ& ba2_in)// activate| (~rs0_in_N & ras_in_N & ~cas_in_N â€ƒâ€ƒ& ba2_in)// xfr;

//-------------------------------------â€‚always @(posedge_clk_in)â€ƒbeginâ€ƒâ€ƒa4_r <= a4_in ;â€ƒâ€ƒa5_r <= a5_in ;â€ƒâ€ƒa6_r <= a6_in ;â€ƒâ€ƒa10_r <= a10_in ;â€ƒâ€ƒba0_r <= ba0_in ;â€ƒâ€ƒba1_r <= ba1_in ;â€ƒâ€ƒba2_r <= ba2_in ;â€ƒâ€ƒq_mrs_cmd_cyc1 <= q_mrs_cmd ;â€ƒend////////////////////////////////////////////////////////////////////////// determine the cas latency////////////////////////////////////////////////////////////////////////assign q_mrs_cmd_r = (!rasN_R & !casN_R & !weN_R)â€ƒâ€ƒ& !rs0N_Râ€ƒâ€‚& (!ba0_r & !ba1_r)â€ƒâ€ƒ; â€ƒâ€ƒ// md reg set cmdâ€‚always @(posedge clk_in)â€ƒif (~reset_N) â€ƒâ€ƒ// lmrâ€ƒâ€ƒcl3 <= l â€²b1 ;â€ƒelse if (q_mrs_cmd_cyc1) â€ƒâ€ƒ// load mode reg cmdâ€ƒbeginâ€ƒâ€ƒcl3 <= (~a6_r & a5_r & a4_r ) ;â€ƒendâ€‚always @(posedge clk_in)â€ƒif (~reset_N) â€ƒâ€ƒ// resetâ€ƒâ€ƒcl2 <= l â€²b0 ;â€ƒelse if (q_mrs_cmd_cyc1) â€ƒâ€ƒ// load mode reg cmdâ€ƒbeginâ€ƒâ€ƒcl2 <= (~a6_r & a5_r & ~a4_r ) ;â€ƒendalways @(posedge clk_in)â€ƒif (~reset_N) â€ƒâ€ƒ// resetâ€ƒâ€ƒcl4 <= l â€²b0 ;â€ƒelse if (q_mrs_cmd_cyc1) â€ƒâ€ƒ// load mode reg cmdâ€ƒbeginâ€ƒâ€ƒcl4 <= (a6_r & ~a5_r & ~a4_r ) ;â€ƒendalways @(posedge clk_in)â€ƒif (~reset_N) â€ƒâ€ƒcl5 <= l â€²b0 ;â€ƒelse if (q_mrs_cmd_cyc1) â€ƒâ€ƒ// load mode reg cmdâ€ƒbeginâ€ƒâ€ƒcl5 <= (a6_r & ~a5_r & a4_r ) ;â€ƒend

assignpre_cyc2_enfet = (wr_cmd_cyc1 & acs_cyc1 & cl3)// wr brst cl3 preambleâ€ƒâ€ƒ;assignpre_cyc3_enfet = (rd_cmd_cyc2 &