BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit having dummy patterns.

2. Description of the Related Art

When a semiconductor integrated circuit of a large scale is to be manufactured, the density of circuit wires may vary from position to position on the substrate. If this happens, optimum etching conditions vary depending on the positions, so that the etching processing will have varying effects. At the positions where the wire density is small, a resist pattern may disappear, resulting in a severance of a wire, or resulting in a thinning of the wire width that will dramatically increase the wire resistance. If the thinning of the wire is significant, the wire may fall down as a result of such thinning. In order to avoid these defectives, semiconductor integrated circuits of today have wire dummies arranged at positions of small wire densities, thereby insuring a constant wire density allover the substrate.

FIG. 1 is a plan view showing a portion of a semiconductor integrated circuit having a constant wire density created by wire dummies.

FIG. 1 shows a plan view of wires provided at the nth layer on a semiconductor substrate. Wires 10 through 12 of the nth layer are arranged as circuit wires (n is a positive integer). There is no circuit wire between the wires 10 and 11, so that the severance or thinning of wires may develop if the semiconductor integrated circuit is manufactured by etching processes without taking any counter measures. In order to avoid this, as shown in FIG. 1, a circuit is designed such that wire dummies 13 are arranged in the blank area between the wires of the nth layer. These wire dummies 13 are not electrically connected to the circuit, but are provided merely for the purpose of achieving a constant wire density and constant etching conditions.

The arrangement of the wire dummies 13 makes it possible to avoid the severance and thinning of wires caused by varying etching conditions.

The wire dummies 13 do not have any direct electrical connection with the real circuitry, but create undesirable capacitance.

FIG. 2 is a drawing for explaining the generation of capacitance by the wire dummies 13.

As shown in FIG. 2, the n1th layer atop the nth layer has wires 14 and 15 arranges as part of the real circuitry, and the n1th layer beneath the nth layer has wires 16 and 17 arranged as part of the real circuitry. Capacitance comes into existence between the wires 14 through 17 and the wire dummies 13.

FIG. 3 is a drawing for explaining the effect of capacitance by the wire dummies 13.

On the left-hand side in FIG. 3, a cross-sectional view taken along the line AA in FIG. 2 is shown. On the right-hand side in FIG. 3, a illustrative drawing is shown to demonstrate a coupling capacitance that develops at a position encircled by a dotted circle in the cross-sectional view. As shown in these illustrations, capacitances C1 and C2 are generated between the wires 14 and 15 and a wire dummy 13. When a circuit simulation is conducted as part of the circuit designing process, wires of the real circuitry can be incorporated into the simulation by identifying the capacitance between the wire. The wire dummies 13, however, are automatically generated after the circuit designing process. Because of this, the capacitances C1 and C2 between the wires and the wire dummy 13 cannot be identified and incorporated into the simulation. As a result, these capacitances surface as simulation errors, thereby degrading the accuracy of simulation analysis.

In the method of generating related-art wire dummy patterns, unit dummy patterns each having a constant size and a constant shape are arranged at predetermined intervals to fill a blank area where no wires are present. According to this method, however, no dummy pattern is inserted at areas where the interval between wires is smaller than the size of the dummy pattern. If the interval between wires is wider, a single row of dummy patterns may be inserted. Even when the wire interval is further widened, however, only a single row of dummy patterns may be arranged if the wire interval is not sufficient to accommodate the second row of dummy patterns while keeping the predetermined interval with the first row. In this manner, if the dummy patterns having the predetermined size are to be arranged at the predetermined intervals, the arrangement of dummy patterns exhibits stepped, discreet changes whereas the wire interval exhibits a gradual, continuous change. Because of this, a blank area is likely to be generated, resulting in a failure to increase the area of resist patterns and a failure to achieve a constant area ratio for the resist patterns.

Accordingly, there is a need for a semiconductor integrated circuit which has a reduced capacitance between wires of the real circuitry and wire dummies, thereby improving the accuracy of simulation analysis.

Further, there is a need for a semiconductor integrated circuit which has dummy patterns arranged therein such as to increase the area ratio of resist patterns and to make the area ratio constant regardless of the length of wire intervals.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a semiconductor integrated circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.

It is another and more specific object of the present invention to provide a semiconductor integrated circuit which has a reduced capacitance between wires of the real circuitry and wire dummies, thereby improving the accuracy of simulation analysis.

It is yet another object of the present invention to provide a semiconductor integrated circuit which has dummy patterns arranged therein such as to increase the area ratio of resist patterns and to make the area ratio constant regardless of the length of wire intervals.

In order to achieve the above objects according to the present invention, a semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

With this provision, it is possible to reduce capacitance between circuit wires and wire dummies provided in different layers, thereby improving the accuracy of simulation at the time of circuit design. Further, parasitic capacitance associated with wires can be reduced in actual devices, so that signal delays along the wires can be reduced.

According to another aspect of the present invention, the semiconductor integrated circuit as described above is such that the wires are signal wires excluding power supply wires. Further, the wire dummies are further provided in areas overlapping positions of the power supply wires that are provided in the first layer.

In this configuration, restrictions prohibiting the generation of wire dummies are not imposed with respect to power supply wires that are not affected by coupling capacitance. This avoids a situation in which the wire dummies are significantly reduced in number due to the presence of circuit wires in layers situated on or beneath the layer of concern, and avoids the undermining of an objective that is to achieve a constant wire density by use of the wire dummies.

According to another aspect of the present invention, the semiconductor integrated circuit as described above is such that the wire dummies have the arrangement that further avoids areas overlapping positions of polysilicon or diffusion layers.

With this provision, it is possible to reduce capacitance between wire dummies and polysilicon or diffusion layers that are susceptible to coupling capacitance, thereby improving the accuracy of simulation at the time of circuit design. Further, parasitic capacitance associated with wires can be reduced in actual devices, so that signal delays along the wires can be reduced.

According to another aspect of the present invention, a semiconductor integrated circuit includes a wire layer, wires provided in the wire layer, and dummy patterns provided in the wire layer and having different sizes.

In this configuration, use of the plurality of dummy pattern sizes makes it possible to generate small-sized dummy patterns in areas where no dummy pattern could be generated in the related art, thereby increasing the area ratio of resist patterns and making the area ratio constant regardless of the length of wire intervals.

With this provision, use of dummy patterns having different shapes conforming to patterns of wires makes it possible to generate dummy patterns in areas where no dummy pattern could be generated in the related art, thereby increasing the area ratio of resist patterns and making the area ratio constant regardless of the length of wire intervals.

According to another aspect of the present invention, a semiconductor integrated circuit includes a plurality of wire layers stacked one over another, a plurality of wires including first wires and second wires and arranged in a first wire layer that is one of the wire layers, the plurality of wires being arranged at various intervals, a shortest of which is a predetermined interval, the first wires having wires on both sides thereof at a distance equal to the predetermined interval, and the second wires having no wires on both sides thereof at a distance equal to the predetermined interval, and dummy patterns provided in a second wire layer immediately above or below the first wire layer, the dummy patterns being arranged in areas overlapping positions of the first wires and being absent in areas overlapping positions of the second wires.

In the semiconductor integrated circuit described above, no dummy pattern is provided in the layers above and below the wires that have adjacent grids vacant on both sides thereof since dummy patterns for such wires have relatively large parasitic capacitance. Here, grids are an imaginary structure of grids arranged at intervals that correspond to a minimum space between the wires. Further, dummy patterns are provided in the layers above and below the wires that have adjacent grids filled on both sides thereof since dummy patterns for such wires have relatively small parasitic capacitance.

According to another aspect of the present invention, a semiconductor integrated circuit includes a plurality of wire layers stacked one over another, a plurality of wires including first wires, second wires, and third wires, and arranged in a first wire layer that is one of the wire layers, the first wires being narrower than a predetermined width, the second wires being equal to or wider than the predetermined width and carrying a power supply potential, and the third wires being equal to or wider than the predetermined width and carrying a clock signal, and dummy patterns provided in a second wire layer immediately above or below the first wire layer, the dummy patterns being arranged in areas overlapping positions of the second wires and being absent in areas overlapping positions of the third wires.

In the semiconductor integrated circuit as described above, dummy patterns are present in layers above and below with respect to wide-width wires that are power supply wires, whereas dummy patterns are absent in layers above and below with respect to wide-width wires that are clock wires carrying varying signal levels. This provision makes it possible to arrange dummy patterns while taking into account the presence of wide-width wires that carry varying signal levels.

A method of arranging dummy patterns according to the present invention includes the steps of providing sets of dummy patterns, each of the sets including patterns of a corresponding size arranged in rows and columns, and arranging the sets of dummy patterns in a descending order of size on a wire layout.

Further, a method of arranging dummy patterns according to the present invention includes the steps of providing dummy patterns arranged at varying intervals inclusive of first intervals and second intervals that are longer than the first intervals, arranging the dummy patterns on a wire layout, combining the dummy patterns spaced at the first intervals by expanding size of the dummy patterns, and shrinking the size of the combined dummy patterns.

Moreover, a method of arranging dummy patterns according to the present invention includes expanding width of first wire patterns arranged in a first wire layer at various intervals, a shortest of which is a predetermined interval, so as to combine the first wire patterns spaced at the predetermined interval, shrinking width of the expanded wire patterns including the combined wire patterns, generating second wire patterns by superimposing the shrunk wire patterns on the first wire patterns, and arranging dummy patterns in a second layer immediately above or below the first layer while avoiding areas overlapping positions of the second wire patterns, except for positions of the shrunk wire patterns.

Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a portion of a semiconductor integrated circuit having a constant wire density created by wire dummies;

FIG. 2 is a drawing for explaining the generation of capacitance by the wire dummies;

FIG. 3 is a drawing for explaining the effect of capacitance by the wire dummies;

FIG. 4 is a drawing showing a portion of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 5 is a drawing showing a portion of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 6 is a drawing showing a portion of a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 7 is a drawing showing a portion of a semiconductor integrated circuit according to a fourth embodiment of the present invention;

FIG. 8 is a drawing showing a portion of a semiconductor integrated circuit according to a fifth embodiment of the present invention;

FIG. 10 shows a case in which the related-art dummy patterns are applied to wires used in the sixth embodiment;

FIG. 11 is a flowchart of a method of arranging dummy patterns according to the sixth embodiment of the present invention;

FIGS. 12A through 12C are drawings for explaining a method of arranging dummy patterns and a semiconductor integrated circuit according to a seventh embodiment of the present invention;

FIG. 13 is a flowchart of a method of arranging dummy patterns according to the seventh embodiment of the present invention;

FIGS. 14A and 14B are cross-sectional views of an LSI that shows an area where dummy patterns are permitted according to the eighth embodiment of the present invention;

FIG. 15 is a flowchart of a method of arranging dummy patterns according to the eighth embodiment of the present invention;

FIG. 16 is a plan view of a layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 17 is a plan view of the layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 18 is a plan view of the layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 19 is a plan view of the layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 20 is a plan view of the layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 21 is a plan view of the layout at one stage of the method of arranging dummy patterns according to the eighth embodiment;

FIG. 22 is a drawing for explaining a method of arranging dummy patterns and a semiconductor integrated circuit according to a ninth embodiment of the present invention;

FIG. 23 is a flowchart of a method of arranging dummy patterns according to the ninth embodiment of the present invention; and

FIG. 24 is a CAD system that performs the method of arranging dummy patterns according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a drawing showing a portion of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 4 shows a plan view of wires of the n1th layer through the n1th layer on a semiconductor substrate. The wires 10 through 12 of the nth layer are arranged as circuit wires. There is no circuit wire between the wires 10 and 11, so that the wire dummies 13 are arranged in the same nth layer in the blank area between the wires of the nth layer. These wire dummies 13 are not electrically connected to the circuit, but are provided merely for the purpose of achieving a constant wire density and constant etching conditions.

When the wire dummies 13 are to be arranged, provision is made to refrain from arranging the wire dummies 13 in areas that overlap circuit wires arranged in the n1th layer and/or the n1th layer stacked on or beneath the nth layer. In an example of FIG. 4, wires 21 and 22 of the real circuit are arranged in the n1th layer, so that the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 21 and 22. By the same token, wires 23 and 24 of the real circuit are arranged in the n1th layer, so that the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 23 and 24.

In this manner, capacitance between the circuit wires of the n1th layer and/or the n1th layer and the wire dummies 13 of the nth layer can be reduced, thereby improving the accuracy of simulation at the time of circuit designing. Further, the parasitic capacitance of wires can be reduced in real devices, thereby reducing signal delays along the wires.

FIG. 5 is a drawing showing a portion of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 shows a plan view of wires of the n1th layer through the n1th layer on a semiconductor substrate. In FIG. 5, the same elements as those of FIG. 4 are referred to by the same numerals.

There is no circuit wire between the wires 10 and 11, so that the wire dummies 13 are arranged in the same nth layer in the blank area between the wires. When the wire dummies 13 are to be arranged, provision is made to refrain from arranging the wire dummies 13 in areas that overlap circuit wires arranged in the n1th layer and/or the n1th layer stacked on or beneath the nth layer. In an example of FIG. 5, the wires 23 and 24 of the real circuit are arranged in the n1th layer, so that the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 23 and 24.

As an exception, if the wires of real circuitry arranged in the n1th layer and/or the n1th layer are the wires for power supply, the wire dummies 13 are arranged in areas that overlap the wires for power supply. In the example of FIG. 5, a wire 25 of real circuitry is arranged in the n1th layer. Since the wire 25 is a wire for power supply, the wire dummies 13 are provided at the nth layer in areas that overlap the wire for power supply.

A voltage supplied to the wires for power supply is not a signal voltage but a power supply voltage, so that capacitance generated by the wire dummies 13 does not pose any problem. Accordingly, no restriction is imposed when arranging the wire dummies 13 with respect to wires for power supply. This avoids a situation in which the wire dummies 13 are significantly reduced in number due to the presence of circuit wires in layers situated on or beneath the layer of concern, and avoids the undermining of an objective that is to achieve a constant wire density by use of the wire dummies 13.

In order to discriminate power supply wires from other wires, the width of wires may be checked. Power supply wires are tend to be designed to have a wider width W, compared with signal wires for signal transfer. When the width W of wires is wider than a predetermined width, therefore, these wires are identified as power supply wires, and the restriction prohibiting the arrangement of wire dummies 13 may be lifted. The wire width threshold for discriminating signal wires from power supply wires varies depending on the fineness of semiconductor integrated circuits, and will become smaller as the semiconductor manufacturing process develops technologically. Thus, the wire width threshold cannot be defined with a definite fixed value. In detail, the wire width threshold may be changed according to the degree of fineness of semiconductor integrated circuits.

FIG. 6 is a drawing showing a portion of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 shows a plan view of wires of the n1th layer through the n1th layer on a semiconductor substrate. In FIG. 6, the same elements as those of FIG. 5 are referred to by the same numerals.

In the third embodiment shown in FIG. 6, a circuit is designed in the same manner as in the second embodiment shown in FIG. 5. That is, if the wires of real circuitry arranged in the n1th layer and/or the n1th layer are the wires for power supply, the wire dummies 13 are arranged in areas that overlap the wires for power supply. In the second embodiment of FIG. 5, the wire width W is checked in order to identify the wire 25 of the n1th layer as a power supply wire. In the third embodiment of FIG. 6, on the other hand, a wire layout is created during a wire layout designing process in such a manner that a power supply wire 25A is drawn in a different layer than wires 26 and 27 of the n1th layer. For example, a layer n1th layer different from the n1th layer is provided at the time of wire layout designing, and all power supply wires are laid out in this n1th layer. This makes the wire 25A of FIG. 6 readily recognizable as a power supply wire.

FIG. 7 is a drawing showing a portion of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 7 shows a plan view of wires of the n1th layer through the n1th layer on a semiconductor substrate. In FIG. 7, the same elements as those of FIG. 4 are referred to by the same numerals. As shown in FIG. 7, the wires 10 through 12 of the nth layer are arranged as circuit wires. There is no circuit wire between the wires 10 and 11, so that the wire dummies 13 are arranged in the same nth layer in the blank area between the wires.

When the wire dummies 13 are to be arranged, provision is made to refrain from arranging the wire dummies 13 in areas that overlap polysilicon layers or diffusion layers formed on the semiconductor substrate in the layers provided on or beneath the nth layer. In an example of FIG. 7, polysilicon or diffusion layers 30 are provided in the n1th layer, so that the wire dummies 13 are not arranged at the nth layer in areas that overlap the polysilicon or diffusion layers 30.

In this manner, capacitance between the polysilicon or diffusion layers of the n1th layer and the wire dummies 13 of the nth layer can be reduced, thereby improving the accuracy of simulation at the time of circuit designing. Further, the parasitic capacitance of wires can be reduced in real devices, thereby reducing signal delays along the wires.

FIG. 8 is a drawing showing a portion of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 8 shows a plan view of wires of a plurality of layers on a semiconductor substrate, and the same elements as those of FIG. 4 are referred to by the same numerals.

The wires 10 through 12 of the nth layer are arranged as circuit wires. There is no circuit wire between the wires 10 and 11, so that the wire dummies 13 are arranged in the same nth layer in the blank area between the wires of the nth layer. Since the wires 21 and 22 of real circuitry are arranged in the n1th layer, the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 21 and 22. By the same token, the wires 23 and 24 of real circuitry are arranged in the n1th layer, so that the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 23 and 24.

In the fifth embodiment, further, when the wire dummies 13 are to be arranged, provision is made to refrain from arranging the wire dummies 13 at the nth layer in areas that overlap circuit wires arranged in the nmth layer and/or the nmth layer stacked above or below the nth layer (m is a positive integer). In the example of FIG. 8, wires 31 and 32 of real circuitry are arranged in the nmth layer, so that the wire dummies 13 are not provided at the nth layer in areas that overlap these wires 31 and 32.

In this manner, capacitance between the circuit wires of the nmth through nmth layers and the wire dummies 13 of the nth layer can be reduced, thereby improving the accuracy of simulation at the time of circuit designing. In the fifth embodiment, the wire dummies 13 are not provided in areas that overlap circuit wires arranged in any one of the nmth layer through the nmth layer. In addition, provision may be made such as to refrain from arranging the wire dummies 13 in areas that overlap polysilicon or diffusion layers as in the fourth embodiment.

In the following, further embodiments of the present invention will be described with reference to the accompanying drawings.

In the following, an embodiment will be described by taking a single layer as an example among a plurality of layers of an LSI device. When there is a need to take into consideration more than one layer, this single layer and adjacent layers situated above and below the single layer will be used as an example.

FIGS. 9A through 9C are plan views of a wire layout for explaining a method of arranging dummy patterns and a semiconductor integrated circuit according to a sixth embodiment of the present invention. The wire layout of FIGS. 9A through 9C includes a first wire 101, a second wire 102, a third wire 103, and a fourth wire 104. The wires 101 through 104 are situated in the same layer.

As shown in FIG. 9A, first dummy patterns 105 are generated at a first step. The dummy patterns 105 are of the largest size among the three dummy patterns having different sizes used in the sixth embodiment. The size of the dummy patterns 105 is 9 m, for example, and the interval between the adjacent dummy patterns 105 is 1 m, for example. In this case, the occupancy ratio of wires in an area where the dummy patterns 105 are arranged in rows and columns will be 81% ((9*9)/((91)*(91))*100), thereby achieving a high occupancy ratio. Since the dummy pattern 105 is that of the largest size, the dummy patterns 105 are generated only in areas of wide wire intervals as in the area between the wire 101 and the wire 102.

FIG. 9B shows the generation of dummy patterns at a second step. Dummy patterns 106 are of the middle size among the three dummy patterns having different sizes used in the sixth embodiment. The size of the dummy patterns 106 is 2 m, for example, and the interval between the adjacent dummy patterns 106 is 1 m, for example. In this case, the occupancy ratio of wires in an area where the dummy patterns 106 are arranged in rows and columns will be 45% ((2*2)/((21)*(21))*100). Since the dummy patterns 105 have already been arranged, the dummy patterns 106 are not generated between the wire 101 and the wire 102. Since the interval between the wire 103 and the wire 104 is too narrow, the dummy patterns 106 are not generated between the wire 103 and the wire 104.

FIG. 9C shows the generation of dummy patterns at a third step. Dummy patterns 107 are of the smallest size among the three dummy patterns having different sizes used in the sixth embodiment. The size of the dummy patterns 107 is 1 m, for example, and the interval between the adjacent dummy patterns 107 is 1 m, for example. In this case, the occupancy ratio of wires in an area where the dummy patterns 107 are arranged in rows and columns will be 25% ((1*1)/((11)*(11))*100).

Since the dummy patterns 105 and 106 have already been arranged, the dummy patterns 107 are not generated between the wire 101 and the wire 102 and between the wire 102 and the wire 103.

In this embodiment as described above, a plurality of dummy patterns having different sizes are provided, and are arranged successively in the descending order of size at spatial intervals according to the pattern size. In this embodiment, the size of dummy patterns having the smallest size may be reduced without any regard to the area occupancy ratio of wires. This can be explained as follows.

In the related-art method which uses dummy patterns of a single size, it is assumed for the sake of argument that the dummy size is 2 m, and that the dummy pattern interval is 1 m. Such dummy patterns are the same as the dummy patterns 106 used in the sixth embodiment. When this dummy pattern is used, the area occupancy ratio of the dummy patterns is 45%, thereby achieving a proper resist area ratio. It should be noted that the resist area ratio is regarded as appropriate if it falls within the range substantially between 30% and 80%.

FIG. 10 shows a case in which the related-art dummy patterns as described above are applied to the wires 101 through 104 used in the sixth embodiment. Dummy patterns 108 are generated between the wire 101 and the wire 102 and between the wire 102 and the wire 103, but are not generated between the wire 103 and the wire 104.

If only dummy patterns are taken into account in calculating the area occupancy ratio, the area occupancy ratio is 45% between the wire 101 and the wire 102 and between the wire 102 and the wire 103, and is 0% between the wire 103 and the wire 104. If the wires 101 through 103 are also taken into account in calculating the area occupancy ratio, a significant tract of blank areas exists between the dummy patterns 108 and the wire 102 in the proximity of the wires 101 and 102, so that the area occupancy ratio is significantly lower than 45% in reality.

In the case of FIG. 9C according to the sixth embodiment of the present invention, if only the dummy patterns are taken into account in calculating the area occupancy ratio, the area occupancy ratio is 81% between the wire 101 and the wire 102, 45% between the wire 102 and the wire 103, and 25% between the wire 103 and the wire 104. Use of a plurality of dummy pattern sizes in this manner makes it possible to increase the area occupancy ratio. If the wires 101 through 103 are also taken into account in calculating the area occupancy ratio, the area occupancy ratio in reality is less than 81% in the proximity of the wires 101 and 102, and is more than 25% in the proximity of the wires 103 and 104. Accordingly, the area occupancy ratio can be increased all across the areas, and, also, a proper area occupancy ratio can be achieved. In this embodiment, further, dummy patterns are successively arranged in the descending order of dummy pattern size, so that dummy patterns having large size are inserted into areas of wide wire intervals, thereby increasing the area occupancy ratio at their localities. If dummy patterns are arranged in the ascending order of dummy pattern size, the dummy pattern of the smallest size will occupy all the areas between the wires 101, 102, 103, and 104. Because of this, there is no space for larger dummy patterns, thereby failing to improve the area occupancy ratio. It should be noted, however, that even if the dummy patterns are successively arranged in the ascending order of dummy pattern size, proper arrangement of dummy patterns may be attained by making it sure to leave areas for larger dummy patterns when arranging smaller dummy patterns.

In this embodiment, use of the plurality of dummy pattern sizes makes it possible to use dummy patterns smaller than the single-sized dummy patterns used in the related art. Use of such small size dummy patterns makes it possible to generate dummy patterns in areas such as between the wire 103 and the wire 104 where no dummy pattern could be generated in the related art as shown in FIG. 10.

The intervals of dummy patterns cannot be reduced in proportion to the size of dummy patterns due to design rule constraints, and are bounded by a certain lower limit. If the size of the single-sized dummy patterns of the related art is selected such as to provide dummy patterns between the wire 103 and the wire 104, it is not possible to maintain a proper area occupancy ratio in the areas of wider wire intervals such as between the wire 101 and the wire 102. In the present embodiment, on the other hand, dummy patterns matching the wire intervals in size are used as shown in FIG. 9C, so that the dummy patterns 107 usable for areas of narrow wire intervals can be used while maintaining a proper area occupancy ratio.

FIG. 11 is a flowchart of a method of arranging dummy patterns according to the sixth embodiment of the present invention.

At step S1, data of imaginary dummy patterns of the largest size and data of layouts are retrieved, and the imaginary dummy patterns of the largest size are superimposed on the layout data. At step S2, a rule file is retrieved, and a check is made as to whether the minimum interval between each of the largest imaginary dummy patterns and wires is proper. If it is proper, the largest imaginary dummy patterns remain at step S3. If there are imaginary dummy patterns that are not proper, the largest imaginary dummy patterns that are not proper are selected and removed at step S4. After these steps, the arrangement of the first dummy pattern set is fixed at step S5.

At step S6, data of imaginary dummy patterns of the middle size is retrieved, and the imaginary dummy patterns of the middle size are superimposed on the sum of the layout data and the first dummy patterns. At step S7, a rule file is retrieved, and a check is made as to whether the minimum interval between each of the middle-sized imaginary dummy patterns and either one of wires and first dummy patterns is proper. If it is proper, the middle-sized imaginary dummy patterns remain at step S8. If there are imaginary dummy patterns that are not proper, the middle-sized imaginary dummy patterns that are not proper are selected and removed at step S9. After these steps, the arrangement of the second dummy pattern set is fixed at step S10.

At step S11, data of imaginary dummy patterns of the smallest size is retrieved, and the imaginary dummy patterns of the smallest size are superimposed on the sum of the layout data, the first dummy patterns, and the second dummy patterns. At step S12, a rule file is retrieved, and a check is made as to whether the minimum interval between each of the smallest imaginary dummy patterns and either one of the wires, the first dummy patterns, and the second dummy patterns is proper. If it is proper, the smallest imaginary dummy patterns remain at step S13. If there are imaginary dummy patterns that are not proper, the smallest imaginary dummy patterns that are not proper are selected and removed at step S14. After these steps, the arrangement of the third dummy pattern set is fixed at step S15.

At step S16, the wires, the first dummy patterns, the second dummy patterns, and the third dummy patterns are combined together, thereby generating mask data for use in the resist exposure process.

In the sixth embodiment described above, the dummy patterns having three different sizes are used. Alternatively, dummy patterns having two different sizes or four or more different sizes may be used.

In the following, a seventh embodiment of the present invention will be described.

FIGS. 12A through 12C are drawings for explaining a method of arranging dummy patterns and a semiconductor integrated circuit according to a seventh embodiment of the present invention. As shown in FIG. 12A, the wire layout includes a first wire 108, a second wire 109, and a third wire 110. The wires 108 through 110 are situated in the same layer.

As shown in FIG. 12A, dummy patterns 112 are generated at a first step. A plurality of the dummy patterns 112 forms a group 112A. The dummy patterns 112 are arranged at two different intervals such that the dummy patterns are provided at a first interval D1 within the group 112A and at a second interval D2 that is a dummy pattern interval between the groups. The size of the dummy patterns 112 is 1 m, for example. The interval D1 of the dummy patterns 112 is 0.8 m, for example, and the interval D2 is 1 m, for example.

FIG. 12B shows a template of the dummy patterns 112 according to the seventh embodiment of the present invention. This template is superimposed on the wire layout of FIG. 12A, and the dummy patterns 112 that interfere with the wires are removed, resulting in the arrangement of dummy patterns as shown in FIG. 12A. In this example, 9 dummy patterns are arranged in a 33 matrix at intervals of 0.8 m to form a group 112A, and the intervals between the groups are 1 m.

FIG. 12C shows the generation of dummy patterns at a second step according to the seventh embodiment. In FIG. 12C, dummy patterns 113 are generated by combining together the dummy patterns 112 of FIG. 12A. The combining of the dummy patterns 112 is performed as follows.

First, the dummy patterns 112 are expanded by 0.44 m in all four directions, i.e., upward, downward, to the left, and to the right. That is, a 1-m dummy size is expanded to a 1.88-m dummy size. The dummy patterns arranged at 0.8-m intervals overlap each other, filling the gaps therebetween. Since the dummy patterns arranged at 1-m intervals that are intervals between the groups 112A still have 0.12-m gaps therebetween, these dummy patterns do not overlap, and are not combined together.

Then, the expanded and combined dummy patterns are shrunk by 0.44 m in all the four directions, i.e., upward, downward, to the left, and to the right. As a result, the 0.12-m intervals that are intervals between the groups 112A are returned to 1 m, thereby producing the dummy patterns 113 as shown in FIG. 12C.

In the seventh embodiment as described above, the dummy patterns having only a single size are used, and are arranged at different intervals. The narrower intervals are filled by expanded dummy patterns, so tha