TECHNICAL FIELD

The present invention relates to the field of computer systems. More specifically, the present invention relates to the field of connecting internal components of a computer system.

BACKGROUND ART

A computer system can be fabricated from a wide variety of individual components and devices which enable it to operate and perform many desirable functions. Some of the internal components of a computer system can include a central processing unit (CPU), a computer readable volatile memory unit (e.g., random access memory, static RAM, dynamic RAM, etc.), a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.), a computer readable mass data storage device such as a magnetic or optical disk, modem device, graphics hardware, sound hardware, and the like. Furthermore, some of the peripheral devices of a computer system, which increase its overall functionality, can include a display device, a keyboard for inputting alphanumeric characters, a cursor control device (e.g., mouse), a printer, a scanner, speakers, and the like.

In order for the many internal components and peripheral devices which constitute a computer system to interact and perform desirable functions, they are interconnected by communication buses. These communication buses can be point-to-point buses, which are typically used between two components. Or they can be buses which are shared by several components. The advantages of the shared bus approach is that not as many wires are needed to implement communication between components. Furthermore, the routing conditions of the computer system are reduced.

In order for a component or circuit block to communicate over a shared bus within a prior art computer system, a bus interface unit is typically implemented internally within the circuit block. The bus interface unit controls the manner in which the circuit block can access the bus. FIG. 1A is a block diagram of a bus interface unit 104 located within a circuit block 102. This type of implementation is commonly used when connecting an integrated circuit (IC) chip to an external shared bus system, such as a peripheral component interconnect (PCI) bus system. Typically, a bus interface unit of a circuit block is designed to conform to the bus standard for which it will be communicating over. For example, bus interface unit 104 is designed to operate in a particular manner to conform to the bus standard of shared bus 114. Specifically, bus interface unit 104 is designed with an input 112 that is always enabled, meaning that it cannot be switched on or off. Furthermore, output 110 of bus interface unit 104 is controlled by circuit block 102 through the use of a tri-state buffer 106 and an output enable signal 108. Moreover, when circuit block 102 desires to drive a signal on external shared bus 114, it first has to transmit signals requesting permission from an external controller (not shown). Once permission is granted by the external controller, circuit block 102 is commanded to assert output enable signal 108 which controls tri-state buffer 106, thereby enabling output 110 to drive shared bus 114. Therefore, when bus interface unit 104 is designed to conform to the bus standard of shared bus 114, circuit block 102 is able to utilize share bus 114 with other circuit blocks. For example, FIG. 1B is a block diagram showing circuit blocks 102, 120, and 122 having the ability to utilize shared external bus 114 when bus interface units 104, 126, and 128 are designed to conform to the bus standard of shared bus 114.

There is a disadvantage associated with the prior art technique of utilizing an internal bus interface unit within a circuit block in order to communicate over a shared bus. The disadvantage is that the internal bus interface unit circuitry of each circuit block is designed and fabricated specifically to be connected in a fixed manner to a single shared bus 114, as shown in FIG. 1B. An additional constraint of this interconnect scheme is that the bandwidth of shared bus 114 should be greater that the sum of the bandwidth required by circuit blocks 102, 120, and 122. This limitation also dictates that the additional connection of any new circuit block to shared bus 114 typically requires a change in the bandwidth of shared bus 114. Since bandwidth is directly proportional to frequency and width of the bus, a change in bandwidth normally cannot be accomplished without changing either frequency or width. Consequently, either or both of these changes usually requires a redesign of the existing circuit blocks 102, 120, and 122.

Therefore, it would be advantageous to provide a system which enables circuit components of a computer system to be connected in a wide variety of shared bus schemes while remaining substantially unchanged. The present invention provides this advantage.

DISCLOSURE OF THE INVENTION

The present invention includes a system which enables existing circuit blocks of a computer system to be connected in a wide variety of shared bus standards while their internal circuitry remains unchanged. Specifically, within an embodiment of the present invention, the sharing of signals over a shared bus scheme is exclusively controlled by external bus control circuits which are controlled by an external control unit. As such, the circuit blocks are designed to operate as if they have dedicated (e.g., point-to-point) lines to the other circuit blocks with which they communicate. By implementing the circuit blocks and external control of the shared signals in this fashion, the bus interconnection scheme of the circuit blocks can be changed to fit desired performance levels or expected traffic levels, while the circuit blocks themselves remain unchanged. Consequently, little or no time is required redesigning existing circuit blocks when bus modifications are implemented within future computer systems which still utilize the existing circuit blocks. Instead, only modifications are required to the external circuitry which controls the shared signals of the circuit blocks, which is substantially easier than redesigning existing circuit blocks.

One embodiment of the present invention is an apparatus for providing communication which comprises a secondary communication bus. Furthermore, the apparatus comprises a plurality of circuit blocks coupled to the secondary communication bus. Each circuit block comprises a bus interface unit and other functional circuitry. Additionally, each bus interface unit communicates with a portion of the secondary communication bus through external bus control circuits. Each bus interface unit facilitates communication between the other functional circuitry and the secondary communication bus. Each bus interface unit internally comprises a duplicated master port unit for establishing a communication of information over the secondary communication bus. Furthermore, each bus interface unit also internally comprises a duplicated slave port unit for responding to a master port in transmitting or receiving information from the secondary communication bus. The apparatus also comprises an external arbitration control unit coupled to control the external bus control circuits of the plurality of bus interface units with control signals to establish dedicated communication pathways between a duplicated master port and a duplicated slave port.

These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:

FIG. 1A is a block diagram of a prior art circuit block having a bus interface unit located internally to the circuit block.

FIG. 1B is a prior art block diagram showing circuit blocks having the ability to share a bus when their bus interface units are designed to conform to the bus standard of the shared bus.

FIG. 2 is a simplified block diagram of one embodiment of a North Bridge design divided into two distinct regions, in accordance with an embodiment of the present invention.

FIG. 3 is a block diagram of a module, which can function as both a master and slave, that would be connected to the secondary bus of FIG. 2.

FIG. 4 is a timing diagram showing the address group signals as seen by a master module during an address phase.

FIG. 5 is a timing diagram showing the address group signals as seen by a slave module for address decoding when the `module select` signal is sampled as asserted in the same clock signal as the `transfer start` signal.

FIG. 6 is a timing diagram showing the address group signals as seen by a slave module for address decoding when the `module select` signal is sampled as de-asserted in the same clock signal as the `transfer start` signal.

FIG. 7 is a table of the types of address space of the secondary bus within the present embodiment.

FIG. 8 is a table of the supported signal description of the `transfer type` signal.

FIG. 9 is a table of an exemplary encoding for the number of beats for the `beats` signal.

FIG. 10 is a table of an exemplary encoding for the number of bytes for the transfer size signal (tsiz).

FIG. 11 is a timing diagram showing the data bus signals for masters for a data phase of a write cycle.

FIG. 12 is a timing diagram showing the data bus group as seen by a target slave for the same write cycle of FIG. 11.

FIG. 13 is a table that is specific for an example of a burst transfer order for 32 byte cache line size.

FIG. 14 is a table showing the stages of power management on the secondary bus within the present embodiment.

FIG. 15 is a timing diagram showing a module requesting a wake up from the quiescent state.

FIG. 16 is a timing diagram showing a module being requested to come back to a power up state by the power management control block.

FIG. 17 is a timing diagram showing an example of a write operation with the slave inserting wait states.

FIG. 18 is a timing diagram showing an example of a write operation with the master inserting wait states by delaying the assertion of the `master ready` signal.

FIG. 19 is a timing diagram showing a read cycle with the slave inserting wait states.

FIG. 20 is a timing diagram showing a read cycle with the master inserting wait states by delaying assertion of the `master ready` signal.

FIG. 21 is a block diagram of an embodiment of a North Bridge chip implementation using the design reuse scheme in accordance with the present invention.

FIG. 22 is a block diagram of a bridge module interfacing between two modules "a" and "b" each having a respective master port and a respective slave port.

FIG. 23 is a timing diagram showing the manner in which bridge module of FIG. 22 controls the address cycles on the secondary bus.

FIG. 24 is a timing diagram showing the data phase associated with the address cycle established in FIG. 23.

FIG. 25 is a timing diagram showing the bridge module of FIG. 22 controlling address cycles between three modules "a", "b", and "c".

FIG. 26 is a block diagram showing several different address decoding schemes, in accordance with the present invention, that can be used to generate the module select signals on an address bus of the secondary bus.

FIG. 27 is a timing diagram showing a module parked on the bus, and the fastest rate of issuing addresses.

FIG. 28 is a block diagram showing the communication traffic which is possible between the various modules over the primary bus of the present invention.

FIG. 29 is a block diagram showing the interconnect scheme of the primary bus of the present invention.

FIG. 30 is a block diagram of an Apple.RTM. PowerPC (PPC) chip set implemented using a North Bridge chip embodiment in accordance with the present invention.

FIG. 31 is a diagram of a CPU bus and a memory bus used to illustrate a snoop cycle.

FIG. 32A is a block diagram of one embodiment of the internal components of the PCI module of FIG. 21, in accordance with the present invention.

FIG. 32B is a block diagram of the secondary bus slave and the PCI bus master, which are both located within the PCI module of FIG. 32A.

FIG. 32C is a block diagram of the secondary bus master and the PCI bus slave, which are both located within the PCI module of FIG. 32A.

FIG. 33 is a block diagram of a bus interface unit, in accordance with the present invention, located within a circuit block.

FIG. 34 is a block diagram of one interconnection scheme in accordance with the present invention.

FIG. 35 is a block diagram of an interconnection scheme, where the sharing of the signals over an external off-chip bus is controlled by an external arbitration control unit, in accordance with the present invention.

FIG. 36 is a block diagram of another interconnection scheme, where the sharing of the signals over an external off-chip bus is controlled by an external arbitration control unit, in accordance with the present invention.

FIG. 37 is a block diagram of an interconnection scheme which includes a shared input bus, a shared output bus, and the sharing of the signals is controlled by an external arbitration control unit, in accordance with the present invention.

FIG. 38 is a block diagram of an interconnection scheme which includes a dedicated output bus and a shared input bus for each circuit block and the sharing of the signals is controlled by an external arbitration control unit, in accordance with the present invention.

FIG. 39A is a block diagram of an interconnection scheme in accordance with an embodiment of the present invention.

FIG. 39B is a block diagram of another interconnection scheme in accordance with an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following detailed description of the present invention, a centrally controlled interface scheme for promoting design reusable blocks, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

A computer system can be fabricated from a wide variety of individual components and devices which enable it to operate and perform many desirable functions. Some of the internal components of a computer system can include a central processing unit (CPU), a computer readable volatile memory unit (e.g., random access memory, static RAM, dynamic RAM, etc.), a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.), a computer readable mass data storage device such as a magnetic or optical disk, modem device, graphics hardware, sound hardware, and the like. Furthermore, some of the peripheral devices of a computer system, which increase its overall functionality, can include a display device, a keyboard for inputting alphanumeric characters, a cursor control device (e.g., mouse), a printer, a scanner, speakers, and the like. Of all the many and diverse components and devices that constitute a computer system, the CPU is its most important functional component. The CPU is made up of circuitry which receives and interprets instructions and then controls their execution within itself or within the other internal components and peripheral devices of the computer system.

Since the CPU is so critical to the operation of the other internal components and peripheral devices of the computer system, it is necessary to couple the CPU to these various components. Within the present invention, there are techniques for coupling the CPU to the various components that constitute the computer system. One embodiment of the present invention is a scaleable, high performance architecture for North Bridge chips which promotes design reuse of various modules located within North Bridge chips.

The advantages of the present invention is that its architecture is able to adapt to different CPUs with minimal changes. Furthermore, the architecture is flexible enough to enable redesign and improvement of the CPU to memory path without affecting the other modules within a North Bridge chip. Moreover, the architecture has the ability to easily add new modules with minimal change to the rest of the design. It should be appreciated that the present invention is not limited to use within North Bridge chips. The present invention is also well suited to interconnect a CPU(s) of a computer system to its other internal components and peripheral devices.

Dual Bus Approach

FIG. 2 is a simplified block diagram of one embodiment of a North Bridge chip 200, in accordance with the present invention, divided into two distinct regions. A primary bus 218 connects a CPU 202 to memory module 204, while a secondary bus 216 connects modules 206-212 to a bridge module 214. Secondary bus 216 is scaleable and enables the addition of new modules, while only requiring changes within bridge module 214. In this way, the modules connected to secondary bus 216 are isolated from any change in the frequency or width of primary bus 218. Furthermore, primary bus 218 is isolated from any required changes due to the addition of new modules to secondary bus 216.

Modules 206-212 of FIG. 2, which are connected to secondary bus 216, are all designed to follow the specification of secondary bus 216 and are designed to act as a single port master and a single port slave device. In this way, if a new module is connected to secondary bus 216, the design of the existing modules (e.g., 206-212) to which the new module is capable of communicating with do not need to change.

Based on the requirements of modules 206-212 of FIG. 2, an embodiment of secondary bus 216 can be flexibly designed in accordance with the present invention. For example, within an embodiment of secondary bus 216, modules 206-212 are made to share common tri-state (separate) address and data buses. At a more complex level, an embodiment of secondary bus 216 can be implemented as a crossbar switch. Any changes to secondary bus 216 are transparent to modules 206-212, and changing the connection scheme is achieved by changing the design of bridge module 214. It should be appreciated that any one of modules 206-212 can also act as a bridge to another bus, e.g., peripheral component interconnect (PCI) bus. In this manner, components and devices that interface with that bus can be connected to secondary bus 216, which makes the architecture more scaleable.

SECONDARY BUS DEFINITION

One embodiment of the definition of secondary bus 216 of FIG. 2, in accordance with the present invention, provides a high performance bus having a high bandwidth. Furthermore, it also enables design reusability of the modules.

Protocol Description

Each module (e.g., 206-212 of FIG. 2) connected to secondary bus 216 is defined within the present embodiment to have as many as two ports, which include a master port and a slave port. Furthermore, each module is defined to only interface with bridge module 214. Bridge module 214 is responsible for forwarding cycles from primary bus 218 to modules 206-212, which are connected to secondary bus 216. Furthermore, bridge module 214 is responsible for forwarding address and data cycles from one module to another module connected to secondary bus 216. Moreover, bridge module 214 is responsible for forwarding address and data cycles from modules 206-212 on secondary bus 216 to primary bus 218. The bridge module 214 provides point-to-point communication paths between the modules for control handshake signals.

Within the present embodiment, as shown in FIG. 3 a master port of a module 300 is defined as one which is capable of generating read or write cycles to another module. A slave port of a module is one which is capable of accepting a read and/or write cycle from another module. It should be appreciated that each module only has one master port, irrespective of the number of modules it is capable of accessing. The slave port only interfaces with bridge module 214, thus making it unaware of the identify of the generating master of any transaction.

Within the present embodiment, the secondary bus interface signals for modules are categorized as input or output signals and are further divided into five sections which include address group signals for a master, address group signals for slaves, data group signals for a master, data group signal for a slave, and data group signal for both a master and a slave. It should be appreciated that the 3 digit number which follows each signal name abbreviation below is used to identify these signals within figures which will be described later.

Signal Description

The following signal descriptions are one embodiment, in accordance with the present invention, of the definitions of the address group signals for a master port.

Output Signal Name: Transfer Start (ts.sub.-- o.sub.--) 328

Active: Low

Output: 0

State Meaning: This signal indicates that a master port has started a bus transaction and that the address and other parameters on the address group are valid.

Timing: Driven valid on the cycle with all other address group signals. Asserted for one clock. The reason that it is a strobe is to allow transfers having no wait states. If it was a steady high signal that remained high, it would not be possible to have transfers having no wait states. This signal cannot be driven again until the `aerr.sub.-- `, `retry.sub.-- `, or `aack.sub.-- ` signal is sampled.

Output Signal Name: Address (add.sub.-- o) 330

Active: Not applicable

Output: 0

State Meaning: This signal specifies the address of the transaction. The width is dependent on the master. Master cannot assume any address translation by the slave based on the source of the transaction. The transaction can however be assumed if the slave is known to support it independent of the source of the transaction.

Timing: Driven valid on the same cycle as `ts.sub.-- ` is asserted and remains valid during the address phase of the transaction. Invalid one bus clock after `aack.sub.-- ` is asserted.

Output Signal Name: Cycle Type (write.sub.-- o) 332

Active: High

Output: 0

State Meaning: When this signal is asserted, it indicates a write cycle. Conversely, when this signal is negated, it indicates a read cycle.