The terms “high level” (or alternatively, “high voltage level”) and “low level” (or alternatively, “low voltage level”) are relative terms describing levels of voltages which, when applied to a transistor described herein, may activate a transistor (e.g., turn “ON” the transistor) or deactivate a transistor (e.g., turn “OFF” the transistor) based on transistor type (e.g., P-type, N-type, or the like). The terms “active level” and “inactive level” describe levels of voltages which, when applied to a transistor described herein, may activate a transistor (e.g., turn “ON” the transistor) or deactivate a transistor (e.g., turn “OFF” the transistor) based on transistor type (e.g., P-type, N-type, or the like)

Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be appreciated that various embodiments of the disclosure and the terms used therein are not intended to limit the technological features set forth herein to particular embodiments and include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B, or C”, “at least one of A, B, and C”, and “at least one of A, B, or C”, may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases.

It is to be understood that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with”, “coupled to”, “connected with”, or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wiredly), wirelessly, or via a third element.

FIG. 1 is a block diagram illustrating a display apparatus according to an embodiment of the present disclosure.

Referring to FIG. 1, the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500 and an emission driver 600.

For example, the driving controller 200 and the data driver 500 may be integrally formed (i.e., integrated into a single circuit or component). For example, the driving controller 200, the gamma reference voltage generator 400 and the data driver 500 may be integrally formed. A driving module including at least the driving controller 200 and the data driver 500 which are integrally formed may be referred to a timing controller embedded data driver (“TED”).

The display panel 100 has a display region AA on which an image is displayed and a peripheral region PA adjacent to the display region AA.

The display panel 100 includes a plurality of gate lines GWL, GIL and GRL, a plurality of data lines DL, a plurality of emission lines EL1 and EL2 and a plurality of pixels electrically connected to the gate lines GWL, GIL and GRL, the data lines DL and the emission lines EL1 and EL2. The gate lines GWL, GIL and GRL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1 and the emission lines EL1 and EL2 may extend in the first direction D1.

The driving controller 200 may receive input image data IMG and an input control signal CONT from an external apparatus. For example, the driving controller 200 may receive the input image data IMG and the input control signal CONT from a host or an application processor. For example, the input image data IMG may include red image data, green image data and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronizing signal and a horizontal synchronizing signal.

The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4 and a data signal DATA based on the input image data IMG and the input control signal CONT.

The driving controller 200 may generate the first control signal CONT1 for controlling an operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

The driving controller 200 may generate the second control signal CONT2 for controlling an operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

The driving controller 200 may generate the data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

The driving controller 200 may generate the third control signal CONT3 for controlling an operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400.

The driving controller 200 generates the fourth control signal CONT4 for controlling an operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600.

The gate driver 300 may generate gate signals driving the gate lines GWL, GIL and GRL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signals to the gate lines GWL, GIL and GRL. For example, the gate driver 300 may be integrated on the peripheral region PA of the display panel 100. For example, the gate driver 300 may be mounted on the peripheral region PA of the display panel 100.

The gamma reference voltage generator 400 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to a level of the data signal DATA.

In an embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200, or in the data driver 500.

The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltages VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into data voltages having an analog type using the gamma reference voltages VGREF. The data driver 500 may output the data voltages to the data lines DL.

The emission driver 600 may generate emission signals to drive the emission lines EL1 and EL2 in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signals to the emission lines EL1 and EL2. For example, the emission driver 600 may be integrated on the peripheral region PA of the display panel 100. For example, the emission driver 600 may be mounted on the peripheral region PA of the display panel 100.

Although the gate driver 300 is disposed at a first side of the display panel 100 and the emission driver 600 is disposed at a second side of the display panel 100 opposite to the first side in FIG. 1 for convenience of explanation, embodiments of the present disclosure are not limited thereto. For example, both of the gate driver 300 and the emission driver 600 may be disposed at the first side of the display panel 100. For example, both of the gate driver 300 and the emission driver 600 may be disposed both sides of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be integrally formed.

FIG. 2 is a circuit diagram illustrating a pixel of the display panel 100 of FIG. 1.

Referring to FIGS. 1 and 2, the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

The pixel receives a writing gate signal GW, an initialization gate signal GI, a first reference gate signal GR(n), a second reference gate signal GR(n−1), the data voltage VDATA, a first emission signal EM1 and a second emission signal EM2 and the light emitting element EE emits a light according to a level of the data voltage VDATA to display an image.

In the present embodiment, the switching elements of the pixel may be oxide semiconductor thin film transistors. For example, the switching elements of the pixel may be N-type transistors.

For example, the pixel may include a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, a first capacitor CST1, a second capacitor CST2 and the light emitting element EE.

The first switching element T1 includes a control electrode connected to a first node N1, a first electrode connected to a second node N2 and a second electrode connected to a third node N3. The first switching element T1 may be referred to as a driving switching element.

The first capacitor CST1 includes a first electrode connected to the first node N1 and a second electrode connected to a fourth node N4.

The second capacitor CST2 includes a first electrode connected to the fourth node N4 and a second electrode connected to the third node N3.

The second switching element T2 applies the data voltage VDATA to the first capacitor CST1.

The third switching element T3 applies a reference voltage VREF to the first node N1.

The fourth switching element T4 includes a control electrode receiving the initialization gate signal GI, a first electrode receiving an initialization voltage VAINT and a second electrode connected to an anode electrode of the light emitting element EE.

The fifth switching element T5 includes a control electrode receiving the first emission signal EM1, a first electrode receiving a first power voltage ELVDD and a second electrode connected to the second node N2.

The sixth switching element T6 includes a control electrode receiving the second emission signal EM2, a first electrode connected to the third node N3 and a second electrode connected to the anode electrode.

The seventh switching element T7 applies the reference voltage VREF to the fourth node N4.

The light emitting element EE may include the anode electrode and a cathode electrode receiving a second power voltage ELVSS. For example, the first power voltage ELVDD may be greater than the second power voltage ELVSS.

For example, the initialization voltage VAINT may be less than the first power voltage ELVDD and may be greater than the second power voltage ELVSS.

In the present embodiment, the second switching element T2 may include a control electrode receiving the writing gate signal GW, a first electrode receiving the data voltage VDATA and a second electrode connected to the first node N1.

In the present embodiment, the seventh switching element T7 may include a control electrode receiving the first reference gate signal (e.g., GR(n)), a first electrode receiving the reference voltage VREF and a second electrode connected to the fourth node N4.

In the present embodiment, the third switching element T3 may include a control electrode receiving the second reference gate signal (e.g., GR(n−1)), a first electrode receiving the reference voltage VREF and a second electrode connected to the first node N1.

In the present embodiment, a white data voltage may be greater than a black data voltage. In the present embodiment, a data voltage representing a high grayscale value may be greater than a data voltage representing a low grayscale value. For example, the reference voltage VREF may be less than the white data voltage and greater than the black data voltage. For example, the reference voltage VREF may be less than the first power voltage ELVDD.

In the present embodiment, the first reference gate signal GR(n) may be a reference gate signal of an n-th stage. The second reference gate signal GR(n−1) may be a reference gate signal of one of previous stages with respect to the n-th stage. Herein, n may be a natural number equal to or greater than two. For example, the second reference gate signal GR(n−1) may be a reference gate signal of a stage immediately preceding the n-th stage. The n-th stage may mean a stage of a gate driving circuit corresponding to an n-th pixel row of the display panel 100.

The writing gate signal GW, the initialization gate signal GI, the first emission signal EM1 and the second emission signal EM2 which do not include (n) in FIG. 2 may be signals of the n-th stage. For example, the writing gate signal GW in FIG. 2 and the writing gate signal GW(n) in FIG. 3 may have the same meaning. For example, the initialization gate signal GI in FIG. 2 and the initialization gate signal GI(n) in FIG. 3 may have the same meaning. For example, the first emission signal EM1 in FIG. 2 and the first emission signal EM1(n) in FIG. 3 may have the same meaning. For example, the second emission signal EM2 in FIG. 2 and the second emission signal EM2 (n) in FIG. 3 may have the same meaning.

With reference to an example in which the first reference gate signal GR(n) is the reference gate signal of the n-th stage and the second reference gate signal GR(n−1) is the reference gate signal of one of the previous stages with respect to the n-th stage, the first reference gate signal GR(n) and the second reference gate signal GR(n−1) are generated from the same gate driving circuit such that a manufacturing cost of the display apparatus may be reduced and a dead space of the display apparatus may be reduced.

FIG. 3 is a timing diagram illustrating an example of input signals applied to the pixel of FIG. 2.

Referring to FIGS. 1 to 3, a driving timing of the pixel may include an initialization period, a compensation period, a writing period and a light emission period.

In the initialization period P2 and P3 of FIG. 3, the first emission signal EM1 may have an inactive level, the second emission signal EM2 may have an active level, the initialization gate signal GI may have an active level and the writing gate signal GW may have an inactive level.

With reference to an example in which the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW are applied to P-type transistors, active levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be low levels and inactive levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be high levels.

In contrast, with reference to an example in which the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW are applied to N-type transistors, active levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be high levels and inactive levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be low levels.

In FIG. 2, the first to seventh switching elements T1 to T7 may be N-type transistors such that active levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be high levels and inactive levels of the first emission signal EM1, the second emission signal EM2, the second reference gate signal GR(n−1), the first reference gate signal GR(n), the initialization gate signal GI and the writing gate signal GW may be low levels.

In the initialization period P2 and P3 of FIG. 3, the fourth switching element T4 may turn on in response to the initialization gate signal GI such that the initialization voltage VAINT is applied to the anode electrode of the light emitting element EE.

In some aspects, in the initialization period P2 and P3 of FIG. 2, the sixth switching element T6 may turn on in response to the second emission signal EM2 such that the initialization voltage VAINT is applied to the third node N3.

In the compensation period P5 of FIG. 3 subsequent to the initialization period P2 and P3 of FIG. 3, the first emission signal EM1 may have an active level, the second emission signal EM2 may have an inactive level, the second reference gate signal GR(n−1) may have an active level, the first reference gate signal GR(n) may have an active level, the initialization gate signal GI may have an inactive level and the writing gate signal GW may have the inactive level.

In the compensation period P5 of FIG. 3, the third switching element T3 may turn on in response to the second reference gate signal GR(n−1) such that the reference voltage VREF is applied to the first node N1.

In the compensation period P5 of FIG. 3, the seventh switching element T7 may turn on in response to the first reference gate signal GR(n) such that the reference voltage VREF is applied to the fourth node N4.

In the compensation period P5 of FIG. 3, the fifth switching element T5 may turn on in response to the first emission signal EM1(n) such that a voltage level of the third node N3 is a sum of the reference voltage VREF and an absolute value of a threshold voltage of the first switching element T1.

For example, in the compensation period P5 of FIG. 3, the threshold voltage of the first switching element T1 may be written to the second capacitor CST2.

In the writing period P7 of FIG. 3 subsequent to the compensation period P5 of FIG. 3, the first emission signal EM1 may have the inactive level, the second emission signal EM2 may have the inactive level, the second reference gate signal GR(n−1) may have an inactive level, the first reference gate signal GR(n) may have the active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have an active pulse (i.e., the writing gate signal GW may transition to the active level and back to the inactive level during the writing period P7).

In the writing period P7 of FIG. 3, the seventh switching element T7 may turn on in response to the first reference gate signal GR(n) such that the reference voltage VREF is applied to the fourth node N4.

In the writing period P7 of FIG. 3, the second switching element T2 may turn on in response to the writing gate signal GW such that the data voltage VDATA is applied to the first node N1.

In the writing period P7 of FIG. 3 of the present embodiment, the second switching element T2 and the seventh switching element T7 may turn on such that the data voltage VDATA is written to the first capacitor CST1 with respect to the reference voltage VREF. In the light emission period P12 of FIG. 3 subsequent to the writing period P7 of FIG. 3, the first emission signal EM1 may have the active level, the second emission signal EM2 may have the active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have the inactive level.

In the light emission period P12 of FIG. 3, the light emitting element EE may emit a light through a current path formed along the fifth switching element T5 turned on in response to the first emission signal EM1, the first switching element T1 turned on according to the data voltage VDATA and the sixth switching element T6 turned on in response to the second emission signal EM2.

The driving timing of the pixel of the present embodiment may further include a second initialization period P10 of FIG. 3.

In the present embodiment, in the second initialization period P10 of FIG. 3 between the writing period P7 of FIG. 3 and the light emission period P12 of FIG. 3, the first emission signal EM1 may have the inactive level, the second emission signal EM2 may have the active level, the initialization gate signal GI may have the active level and the writing gate signal GW may have the inactive level.

In the second initialization period P10 of FIG. 3, the fourth switching element T4 may turn on in response to the initialization gate signal GI such that the initialization voltage VAINT is applied to the anode electrode of the light emitting element EE.

In some aspects, in the second initialization period P10 of FIG. 3, the sixth switching element T6 may turn on in response to the second emission signal EM2 such that the initialization voltage VAINT is applied to the third node N3.

FIG. 4 is a timing diagram illustrating an example of input signals applied to the pixel of FIG. 2.

The driving timing of the pixel of FIG. 4 may be substantially the same as the driving timing of the pixel of FIG. 3 except that the driving timing does not include the second initialization period. For example, the driving timing of the pixel of FIG. 4 may be substantially the same as the driving timing of the pixel of FIG. 3 except that the waveform of the initialization gate signal GI does not include the second active period. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 to 3 and any repetitive explanation concerning the above elements will be omitted.

Referring to FIGS. 1, 2 and 4, a driving timing of the pixel may include an initialization period, a compensation period, a writing period and a light emission period.

In the initialization period P2 and P3 of FIG. 4, the first emission signal EM1 may have an inactive level, the second emission signal EM2 may have an active level, the initialization gate signal GI may have an active level and the writing gate signal GW may have an inactive level.

In the compensation period P5 of FIG. 4 subsequent to the initialization period P2 and P3 of FIG. 4, the first emission signal EM1 may have an active level, the second emission signal EM2 may have an inactive level, the second reference gate signal GR(n−1) may have an active level, the first reference gate signal GR(n) may have an active level, the initialization gate signal GI may have an inactive level and the writing gate signal GW may have the inactive level.

In the writing period P7 of FIG. 4 subsequent to the compensation period P5 of FIG. 4, the first emission signal EM1 may have the inactive level, the second emission signal EM2 may have the inactive level, the second reference gate signal GR(n−1) may have an inactive level, the first reference gate signal GR(n) may have the active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have an active pulse (i.e., the writing gate signal GW may have an active level in a portion of the writing period P7). In the light emission period P10 of FIG. 4 subsequent to the writing period P7 of FIG. 4, the first emission signal EM1 may have the active level, the second emission signal EM2 may have the active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have the inactive level.

According to the present embodiment, the pixel includes the first capacitor CST1 and the second capacitor CST2 connected in series between the control electrode of the first switching element T1 and the second electrode of the first switch element T1 and includes the seventh switching element T7 applying the reference voltage VREF to the node between the first capacitor CST1 and the second capacitor CST2. The data voltage VDATA may be directly applied to the control electrode N1 of the first switching element T1.

The threshold voltage of the first switching element T1 may be applied to the second capacitor CST2 and the data voltage VDATA which is based on the reference voltage VREF may be directly applied to the first capacitor CST1 such that the swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 may become similar.

The swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 are similar such that a slope of the current-voltage curve of the first switching element T1 may be set low, and accordingly, the sensitivity of the first switching element T1 may be reduced.

Based on the decrease of the sensitivity of the first switching element T1, a decrease in the display quality due to the crosstalk and the touch noise and the cycle mura may be prevented such that the display quality of the display panel 100 may be enhanced.

In some aspects, the second capacitor CST2 may be initialized in the initialization period of the pixel (and the first capacitor CST1 is not initialized in the initialization period) such that an amount of the voltage for initialization may be reduced.

FIG. 5 is a circuit diagram illustrating a pixel of a display panel 100 of a display apparatus according to an embodiment of the present disclosure. FIG. 6 is a timing diagram illustrating an example of input signals applied to the pixel of FIG. 5.

The display apparatus according to the present embodiment is substantially the same as the display apparatus of the previous embodiment explained referring to FIGS. 1 to 4 except that the first reference gate signal and the second reference gate signal are independent signals generated from independent gate driving circuits. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 to 4 and any repetitive explanation concerning the above elements will be omitted.

Referring to FIGS. 1, 5 and 6, for example, the pixel may include a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, a first capacitor CST1, a second capacitor CST2 and the light emitting element EE.

In the present embodiment, the seventh switching element T7 may include a control electrode receiving a first reference gate signal (e.g., GR1(n)), a first electrode receiving the reference voltage VREF and a second electrode connected to the fourth node N4.

In the present embodiment, the third switching element T3 may include a control electrode receiving a second reference gate signal (e.g., GR2(n)), a first electrode receiving the reference voltage VREF and a second electrode connected to the first node N1.

In the present embodiment, the first reference gate signal GR1(n) and the second reference gate signal GR2(n) are independent signals generated from independent gate driving circuits unlike the embodiment of FIGS. 1 to 4.

According to the present embodiment, the pixel includes the first capacitor CST1 and the second capacitor CST2 connected in series between the control electrode of the first switching element T1 and the second electrode of the first switch element T1 and includes the seventh switching element T7 applying the reference voltage VREF to the node between the first capacitor CST1 and the second capacitor CST2. The data voltage VDATA may be directly applied to the control electrode N1 of the first switching element T1.

The threshold voltage of the first switching element T1 may be applied to the second capacitor CST2 and the data voltage VDATA which is based on the reference voltage VREF may be directly applied to the first capacitor CST1 such that the swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 may become similar.

The swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 are similar such that a slope of the current-voltage curve of the first switching element T1 may be set low, and accordingly, the sensitivity of the first switching element T1 may be reduced.

According to the decrease of the sensitivity of the first switching element T1, the display quality decreases due to the crosstalk and the touch noise and the cycle mura may be prevented such that the display quality of the display panel 100 may be enhanced.

In some aspects, only the second capacitor CST2 may be initialized in the initialization period of the pixel such that an amount of the voltage for initialization may be reduced.

FIG. 7 is a circuit diagram illustrating a pixel of a display panel 100 of a display apparatus according to an embodiment of the present disclosure. FIG. 8 is a timing diagram illustrating an example of input signals applied to the pixel of FIG. 7.

The display apparatus according to the present embodiment is substantially the same as the display apparatus of the previous embodiment explained referring to FIGS. 1 to 4 except that the pixel further includes an eighth switching element. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 to 4 and any repetitive explanation concerning the above elements will be omitted.

Referring to FIGS. 1, 7 and 8, for example, the pixel may include a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, a first capacitor CST1, a second capacitor CST2 and the light emitting element EE. The pixel may further include an eighth switching element T8.

The fourth switching element T4 includes a control electrode receiving the initialization gate signal GI, a first electrode receiving an initialization voltage VAINT and a second electrode connected to an anode electrode of the light emitting element EE.

The sixth switching element T6 includes a control electrode receiving the second emission signal EM2, a first electrode connected to the third node N3 and a second electrode connected to the anode electrode.

The eighth switching element T8 includes a control electrode receiving the initialization gate signal GI, a first electrode receiving a second initialization voltage VINT and a second electrode connected to the third node N3.

For example, the initialization voltage VAINT may be less than the first power voltage ELVDD and greater than the second power voltage ELVSS. For example, the second initialization voltage VINT may be less than the first power voltage ELVDD and greater than the second power voltage ELVSS. For example, the second initialization voltage VINT may be greater than the initialization voltage VAINT.

An optimal voltage for initializing the anode electrode of the light emitting element EE may be different from an optimal voltage for initializing the second electrode (the third node N3) of the second capacitor CST2. In the present embodiment, the initialization voltage VAINT initializing the anode electrode of the light emitting element EE and the second initialization voltage VINT initializing the second electrode (the third node N3) of the second capacitor CST2 may be differently set such that the display quality of the display panel 100 may be further enhanced.

A driving timing of the pixel may include an initialization period, a compensation period, a writing period and a light emission period.

In the initialization period P2 and P3 of FIG. 8, the first emission signal EM1 may have an inactive level, the second emission signal EM2 may have an inactive level, the initialization gate signal GI may have an active level and the writing gate signal GW may have an inactive level.

In the initialization period P2 and P3 of FIG. 8, the fourth switching element T4 may turn on in response to the initialization gate signal GI such that the initialization voltage VAINT is applied to the anode electrode of the light emitting element EE.

In the initialization period P2 and P3 of FIG. 8, the eighth switching element T8 may turn on in response to the initialization gate signal GI such that the second initialization voltage VINT is applied to the third node N3.

In the compensation period P4 of FIG. 8 subsequent to the initialization period P2 and P3 of FIG. 8, the first emission signal EM1 may have an active level, the second emission signal EM2 may have the inactive level, the second reference gate signal GR(n−1) may have an active level, the first reference gate signal GR(n) may have an active level, the initialization gate signal GI may have an inactive level and the writing gate signal GW may have the inactive level.

In the writing period P6 of FIG. 8 subsequent to the compensation period P4 of FIG. 8, the first emission signal EM1 may have the inactive level, the second emission signal EM2 may have the inactive level, the second reference gate signal GR(n−1) may have an inactive level, the first reference gate signal GR(n) may have the active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have an active pulse. In the light emission period P8 of FIG. 8 subsequent to the writing period P6 of FIG. 8, the first emission signal EM1 may have the active level, the second emission signal EM2 may have an active level, the initialization gate signal GI may have the inactive level and the writing gate signal GW may have the inactive level.

According to the present embodiment, the pixel includes the first capacitor CST1 and the second capacitor CST2 connected in series between the control electrode of the first switching element T1 and the second electrode of the first switch element T1 and includes the seventh switching element T7 applying the reference voltage VREF to the node between the first capacitor CST1 and the second capacitor CST2. The data voltage VDATA may be directly applied to the control electrode N1 of the first switching element T1.

The threshold voltage of the first switching element T1 may be applied to the second capacitor CST2 and the data voltage VDATA which is based on the reference voltage VREF may be directly applied to the first capacitor CST1 such that the swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 may become similar.

The swing range of the data voltage VDATA and the range of the gate-source voltage of the first switching element T1 are similar such that a slope of the current-voltage curve of the first switching element T1 may be set low, and accordingly, the sensitivity of the first switching element T1 may be reduced.

According to the decrease of the sensitivity of the first switching element T1, the display quality decreases due to the crosstalk and the touch noise and the cycle mura may be prevented such that the display quality of the display panel 100 may be enhanced.

In some aspects, only the second capacitor CST2 may be initialized in the initialization period of the pixel such that an amount of the voltage for initialization may be reduced.

FIG. 9 is a circuit diagram illustrating a pixel of a display panel of a display apparatus according to an embodiment of the present disclosure.

The display apparatus according to the present embodiment is substantially the same as the display apparatus of the previous embodiment explained referring to FIGS. 1 to 4 except that the second switching element is connected to the fourth node, the first reference gate signal is applied to the control electrode of the third switching element and the second reference gate signal is applied to the control electrode of the seventh switching element. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous embodiment of FIGS. 1 to 4 and any repetitive explanation concerning the above elements will be omitted.

Referring to FIGS. 1, 3, 4 and 9, for example, the pixel may include a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, a first capacitor CST1, a second capacitor CST2 and the light emitting element EE.