In this embodiment, when the specific instruction slot is selected in S2, the multiple instruction slots may be sorted, and the first instruction slot is used in the first tick; in the second tick, if the first instruction slot still has a vacant position, the first instruction slot will be used; if the first instruction slot does not have a vacant position, the second instruction slot will be used; in the third tick, the specific instruction slot is selected in the same way until all the ticks are completed or all the instruction slots are used. In one tick, if none of the instruction slots has a vacant position and an instruction is transmitted in the previous tick, the instruction in this tick can be stored in the position of the instruction transmitted in the previous tick.

S3, non-transmitted instructions in the multiple instruction slots in S2 are sorted according to a sequence in which the instructions enter the reservation station to recognize an earliest instruction, a second earliest instruction, etc. Whether there is an instruction that is not blocked in the non-transmitted instructions is determined; if there is not an instruction that is not blocked in the non-transmitted instructions, it indicates all the instructions are blocked, no instruction will be transmitted, and a block is set by a hold signal set in a tick before the current tick; if there is an instruction that is not blocked in the non-transmitted instructions, a specific instruction that enters the reservation station at the earliest and is not blocked is determined from the earliest instruction according to a sorting result, the specific instruction is transmitted to the vector execution unit to be executed, and a prewrite-back signal is sent out.

In this embodiment, when one instruction is transmitted from the instruction slot to the execution unit, an address to which the instruction will be written back and the number of ticks for executing the instruction will be transmitted to the reservation station, and the address and number of ticks transmitted to the reservation station are both prewrite-back signals. In case of multiple reservation stations, addresses transmitted to other reservation stations when instructions are transmitted are also prewrite-back signals.

S4, hold signals are set, wherein the hold signals include a write conflict block signal, a division block signal and a write-back bubble block signal, each signal corresponds to one signal instruction, and the write-back bubble block signal is also referred to as a block signal requesting write-back bubbles. The write conflict block signal generates a block signal by means of the shift register to block an instruction that may cause a write conflict, the division block signal also generates a block signal by means of the shift register, and the block signal generated by the division block signal is combined with the block signal generated by the write conflict block signal to block the transmission of the instruction. All instructions stored in the instruction slots are detected by means of the three hold signals to distinguish instructions to be blocked from instructions not to be blocked, instructions that may cause a write conflict and a division conflict are blocked, and a block position is set according to the number of ticks; and before the block position, the blocked instruction will not be transmitted. The division block signal adopts a division instruction, and when the division instruction is executed, it takes some time to complete the operation, so the write-back bubble block signal is used to stop other operations; after the division instruction is executed and the block position is set, the division instruction will write a result back to the register file; in this process, the processor will generate bubbles, that is to say, some vacant periods will be introduced to the pipeline of the processor to ensure that the division result can be written back correctly.

It should be noted that the bubbles of the processor are vacant periods introduced into the pipeline of the processor to ensure that instructions or operations can be performed smoothly.

In this embodiment, “prewrite-back” is an operation of sending, before the calculation result of an instruction is about to be, but not have been, written back to the register file, a corresponding control signal to the reservation station to allow the instruction to get data ready in advance to improve execution efficiency.

Because the division instruction can be executed in variable ticks, the number of ticks written back is not fixed. The specific write-back logic is as follows: when an operation corresponding to the division instruction is completed, the division instruction is stored in an internal register, a prewrite-back signal will be provided in a tick before the calculation result of the division instruction is obtained, and the prewrite-back signal is sent to the reservation station; when receiving the prewrite-back signal, the reservation station will find a vacant position in the shift register for solving write conflicts, the vacant position is pulled up to prevent the instruction from being transmitted, and at the same time, the block position is marked and sent to a multi-tick execution unit; and when a multi-tick instruction finds the marked position, it will write back the division result. When a fixed-point division instruction and a floating-point division instruction generate both prewrite-back requests, the reservation station will find two vacant positions in the shift register, and the division results are sequentially written back to the vacant positions.

The operation of the division block signal is an operation based on a module that is used cyclically rather than a pipelined operation, so a new division instruction cannot be transmitted in the operation of the division block signal. In addition, all instruction slots with instructions need to be detected in each tick; if a fixed-point division block or a floating-point division block is detected, it indicates that a conflict occurs, and the corresponding instruction cannot be transmitted. By means of the division block signal, transmission of the instruction in the current tick can be stopped in time when necessary to avoid a conflict.

In this embodiment, in S4, in a case where a fixed-point division block or a floating-point division block is detected when the multiple instruction slots are detected by means of the hold signals, transmission of the instruction will be stopped instantly to avoid a write conflict between two instructions; when a write conflict block is detected, the instruction will also be blocked; and when a block signal requesting write-back bubbles is detected, a prewrite-back request will be sent to the reservation station when the operation of a division instruction corresponding to the division block signal is about to be completed, to send a flag to be written back to the vector execution unit to perform write-back.

As shown in FIG. 4 which is a principle diagram of a shift operation performed by the shift register to solve a write conflict. Bits corresponding the instruction in the shift register are 10110, it is set by the write conflict block signal that one shift to the right by one bit is performed in each tick, and then tick counting and shifting are performed, that is, the bits turn into 01011 after the shift in one tick; and the selected instruction needs to be executed for two ticks, the least significant digit of the shift register indicates that there is an instruction that needs to be written back instantly, and the serial number is 0. The instruction needs to be executed for two ticks, which means that the instruction will be written back two ticks later, and the position corresponding to the serial number 2 should be pulled up, so the bits corresponding the instruction in the shift register are finally 01111.