120 and external networks, such as local area networks (LANs) or the Internet, and includes both hardware and software components that handle data transmission, reception, and protocol management. The network interfaces 108 may include one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each allowing the electronic system 100 to exchange data with an external source, and participate in networked applications, such as IoT (Internet of Things), mobile communications, or cloud computing.

In some implementations, the memory modules 104 include high-speed random-access memory, such as static random-access memory (SRAM), double data rate (DDR) dynamic random-access memory (DRAM), or other random-access solid state memory devices. In some implementations, the memory modules 104 include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. In some implementations, the memory modules 104, or alternatively the non-volatile memory device(s) within the memory modules 104, include a non-transitory computer readable storage medium. In an example, a memory module 104 includes a high bandwidth memory (HBM) configured to provide a data bandwidth greater than a bandwidth threshold to support GPUs 102G. The HBM includes a plurality of memory dies that are stacked vertically on top of each other. In some implementations, the electronic system 100 further includes a memory controller 122 coupled to manage memory access requests for the memory modules 104.

FIGS. 2A and 2B are a top perspective view and a bottom perspective view of an example electronic system 100, in accordance with some implementations, respectively. The electronic system 100 includes an SoC 120 having a substrate 202. The substrate 202 includes a first surface 202A and a second surface 202B that is opposite to the first surface 202A. The substrate 202 may be one of a silicon substrate, a polymeric substrate, a glass substrate, or a PCB. Examples of the polymeric substrate include, but are not limited to, PI, PET, and PDMS. In some implementations, each electronic component of the electronic system 100 corresponds to a region of the substrate 202, and includes a portion of an integrated circuit of the SoC 120. Alternatively, in some implementations, each electronic component of the electronic system 100 includes one or more chips that are mounted onto the substrate 202, e.g., with or without an intermediate support structure 210. In an example, the substrate 202 is made of a polymeric material, and the intermediate support structure 210 is made of silicon and applied to mechanically support a plurality of components (e.g., including an IO chip 206, a memory chip 208, a processor chip 212).

In some implementations not shown, all electronic components included in the electronic system 100 are disposed on the first surface 202A of the substrate 202. Alternatively, in some implementations, a first subset of electronic components of the electronic system 100 are disposed on the first substrate 202A of the substrate 202, and a second subset of electronic components of the electronic system 100 are disposed on the second substrate 202B of the substrate 202. In an example, one or more chips corresponding to a subset of the electronic components 102-108, 118, and 122 are disposed on the second surface 202B. In another example, one or more chips corresponding to the PMIC module 112 are disposed on the second surface 202B.

In some implementations, the PMIC module 112 includes a plurality of distinct PMIC chips 204, which further include a first set of PMIC chips 204A and a second set of PMIC chips 204B. The first set of PMIC chips 204A are disposed on the first surface 202A of the substrate 202, e.g., jointly with all or a subset of remainder components of the SoC 120 distinct form the PMIC module 112. The second set of PMIC chips 204B are disposed on the second surface 202B of the substrate 202. A rail voltage outputted by the first set of PMIC chips 204A is routed on or under the first surface 202A, e.g., by way of a configurable power plane, to access a power rail 116 of the remainder components of the SoC 120. In some implementations, a rail voltage is outputted by the second set of PMIC chips 204B and routed vertically across the substrate 202, from the second surface 202B to the first surface 202A, to access an associated power rail 116 located on or under the first surface 202A, e.g., by way of a configurable power plane.

In some implementations, the PMIC module 112 includes a plurality of voltage regulator cells (e.g., voltage regulator cells 406 in FIG. 4B). In an example, a first PMIC chip 204-1 includes a subset of one or more respective voltage regulator cells (e.g., cell 406 in FIG. 4B), and is disposed immediately adjacent to an IO chip 206 including the I/O interface 106, allowing the I/O interface 106 to access a rail voltage provided by the subset of voltage regulator cells of the first PMIC chip 204-1. Alternatively, in some situations, two or more first PMIC chip 204-1 are disposed immediately adjacent to the IO chip 206 to provide the rail voltage to the IO chip 206 jointly. In another example, a memory chip 208 including one of the memory modules 104 is disposed on a location of the first surface 202A, and a second PMIC chip 204-2 is disposed a location of the second surface 202B aligned with (e.g., opposite to) the location of the first surface 202A. The second PMIC chip 204-2 includes a subset of one or more respective voltage regulator cells (e.g., cell 406 in FIG. 4B), and allows the one of the memory modules 104 to access a rail voltage provided by the respective voltage regulator cells vertically. By these means, a component of the SoC 120 may access its associated voltage regulator cell(s) located on a respective PMIC chip 204 that is disposed in proximity to the component without introducing an extended length to access a power rail 116, which helps reduce resistive and capacitive parasitics of the power rail 116 and enhance performance of the SoC 120.

FIGS. 3A and 3B are a top perspective view and a bottom perspective view of another example electronic system 100, in accordance with some implementations, respectively. In some implementations, the first surface 202A of the substrate 202 includes a device region 302 on which a plurality of component chips (e.g., processor chip 212, IO chip 206, memory chips 208) are disposed. One or more first PMIC regions 304A (e.g., two PMIC regions) are located adjacent to the device region 302, and a first set of PMIC chips 204A are disposed on the one or more PMIC regions 304A of the first surface 202A of the substrate 202. For example, two rows of PMIC chips 204A are disposed adjacent to two opposing sides of the device region 302. In another example not shown, four rows of PMIC chips 204A are disposed adjacent to four distinct sides of the device region 302, respectively.

In some implementations not shown, the second surface 202B of the substrate 202 includes an alternative device region on which one or more component chips (e.g., processor chip 212, IO chip 206, memory chips 208) are disposed and one or more PMIC regions on which a second set of PMIC chips 204B are disposed, independently of a chip arrangement of the first surface 202A. Alternatively, in some implementations (FIG. 3B), the second surface 202B of the substrate 202 includes a second PMIC region 304B. Referring to FIG. 3A, the perspective view of the integrated electronic system 100 is depicted from the top angle with a see-through effect (e.g., to see through the substrate 202). In some implementations, the second PMIC region 304B at least partially overlaps the device region 302, allowing a component chip mounted on the device region 302 to access an output of the second PMIC region 304B using a via (e.g., a through silicon via (TSV)).

In some implementations, centers of the second PMIC region 304A and the device region 302 are aligned with one another, i.e., a center of the second PMIC region 304A and a center of the device region 302 are directly opposite to one another on two opposing surfaces 202A and 202B of the substrate 202. Further, in some implementations, sizes of the second PMIC region 304A and the device region 302 are equal to each other. Alternatively, in some implementations, the sizes of the second PMIC region 304A and the device region 302 are different from each other. Alternatively, in some implementations, the second PMIC region 304A and the device region 302 are independent from one another in size and/or in position.

In other words, the PMIC module 112 includes a plurality of voltage regulator cells distributed in a subset of the plurality of PMIC chips 204. Each PMIC chip 204 is located at a respective position on the first surface 202A or the second surface 202B of the substrate 202. In some implementations, the plurality of voltage regulator cells is grouped based on their locations to provide a plurality of rail voltages to a plurality of power rails 116 coupled to different components of the SoC 120. More specifically, in some implementations, each power rail 116 coupled to a component (e.g., CPU chip, GPU chip, memory chip, IO chip) is coupled to a set of voltage regulator cells, which are selected based on their locations with respect to a location of the component. For example, the set of voltage regulator cells are the closest to the respective component in distance compared with a remainder of the voltage regulator cells, thereby controlling associated resistive and capacitive parasitics. In another example, the set of voltage regulator cells, which coupled to the respective component, provides the lowest parasitic level. Among two voltage regulator cells having equal distances form the respective component, a voltage regulator cell located on the first surface 202A is selected over a voltage regulator cell located on the second surface 202B. In some implementations, a voltage regulator cell located on the first surface 202A and having a larger distance from the respective component is selected over a voltage regulator cell located on the second surface 202B and having a smaller distance from the respective component.

In some implementations, the PMIC module 112 further includes a plurality of reference circuits (e.g., circuit 400 in FIGS. 4A and 4B). The plurality of reference circuits may be formed on the same PMIC chip 204 or distributed on two or more PMIC chips 204. For example, each PMIC region 304A or 304B includes at least one PMIC chip 204 (e.g., chips 204-3, 204-4, and 204-5) dedicated to providing one or more reference circuits. In another example, all of the plurality of reference circuits used within the voltage regulator cells of the PMIC module 112 are consolidated on a single PMIC chip (e.g., chip 204-5).

Alternatively, in some implementations, the plurality of reference circuits used with the voltage regulator cells of the PMIC module 112 are provided by a single chip 306 or distributed among a plurality of chips (e.g., chips 306 and 308), which are mounted on, or integrated in, the device region 302.

FIG. 4A is a high-level block diagram of an example PMIC module 112, in accordance with some implementations, and FIG. 4B is a detailed block diagram of an example PMIC module 112, in accordance with some implementations. The PMIC module 112 includes, or is coupled to, a plurality of power rails 116 configured to provide one or more rail voltages V_RAIL. The PMIC module 112 further includes an array 404 of voltage regulator cells 406 and a plurality of reference circuits 408. The plurality of reference circuits 408 are coupled to, but distinct from, the array 404 of voltage regulator cells 406. The array 404 of voltage regulator cells 406 is coupled to the plurality of power rails 116, and configured to provide a plurality of voltage regulator sets 410. Each voltage regulator set 410 is configured to output a respective rail voltage V_RAILto a respective power rail 116. Each of the plurality of reference circuits 408 is shared by, and configured to provide a respective reference voltage V_REFto, one or more respective voltage regulator cells 406 of a respective voltage regulator set 410. The respective voltage regulator set 410 is configured to generate the respective rail voltage V_RAILbased on the respective reference voltage V_REF.

Stated another way, some implementations of this application include a PMIC module 112 that has an array 404 of voltage regulator cells 406, a plurality of voltage references 408 that are selectable and programmable, and distribution circuits and buses that are selectable. Different numbers of voltage regulator cells 406 may be grouped together to form a voltage regulator set 410 for outputting a rail voltage V_RAIL(also called a power supply voltage). The array 404 of voltage regulator cells 406 may be grouped to form a single voltage regulator set 410 or a plurality of power regulator sets 410, thereby providing a single rail voltage V_RAILor multiple rail voltages V_RAIL. In some implementations, the PMIC module 112 provides a plurality of rail voltages V_RAILcorrespond to a plurality of distinct voltage regulator sets 410, and each voltage regulator set 410 includes a respective number of voltage regulator cells 406, independently of other voltage regulator set(s) 410. For each voltage regulator set 410, outputs of the respective voltage regulator cells 406 are electrically coupled (e.g., shortened) to one another and further to a respective power rail 116. In some implementations, a voltage regulator set 410 is configured to output a variable rail voltage V_RAIL, e.g., to track a respective reference voltage V_REF.

In some implementations, the PMIC module 112 includes, or is coupled to, a single substrate (e.g., substrate 202 in FIGS. 2A and 2B). The array 404 of voltage regulator cells 406 and the plurality of reference circuits 408 are disposed on the substrate 202, separately from one another. In some implementations, the array 404 of voltage regulator cells 406 and the plurality of reference circuits 408 correspond to different sets of PMIC chips 204 disposed on PMIC regions 304A and 304B (FIGS. 3A and 3B) of the substrate 202. Alternatively, in some implementations, the array 404 of voltage regulator cells 406 is distributed in PMIC chips 204 disposed on the PMIC regions 304A and 304B of the substrate 202, and the plurality of reference circuits 408 correspond to chips (e.g., chip 306 or 308 in FIG. 3A) disposed on a device region 302 (FIG. 3A) of the substrate 202.

Referring to FIG. 4B, in some implementations, the plurality of power rails 116 include a first number M of power rails 116, and the plurality of reference circuits 408 include a second number N of reference circuits 408. The second number N is equal to or less than the first number M. Further, in some implementations, each reference circuit 408 and a respective power rail 116 is uniquely associated with each other, and the respective reference circuit 408 is configured to provide the respective reference voltage V_REFto the respective voltage regulator cell set 410 assigned to generate the rail voltage V_RAILfor the power rail 116. A number of voltage regulator cells 406 in the respective voltage regulator cell set 410 may be varied.

In some implementations, rail voltages V_RAILof two power rails 116-1 and 116-2 are equal to each other, and each power rail 116 maintains a consistent voltage. It is required that voltage regulator cells 406 contributing to each respective power rail 116-1 or 116-2 be driven by the same respective reference circuit 408. Further, in some implementations, two voltage regulator sets 410-1 and 410-2 corresponding to the two power rails 116-1 and 116-2 are coupled to two distinct reference circuits 408-1 and 408-2. Alternatively, in some implementations, the two voltage regulator sets 410-1 and 410-2 corresponding to the two power rails 116-1 and 116-2 are coupled to the same reference circuit 408 (e.g., 408-1). As such, the second number N of the reference circuits 408 is equal to or less than the first number M of the power rails 116.

In some implementations, the plurality of power rails 116 include a first number M of power rails 116, and the plurality of reference circuits 408 include a second number N of reference circuits 408. The array 404 of voltage regulator cells 406 includes a third number K of voltage regulator cells 406. The second number N is equal to or less than (≤) the third number K, and the first number M is equal to or less than (≤) the third number K.

In some implementations, the PMIC module 112 includes a first switch array 412 (e.g., having the second number N of rows and the third number K of columns, or the second number N of columns and the third number K of rows). For example, rows of the first switch array 412 are electrically coupled to the second number N of reference circuits 408, and columns of the first switch array 412 are electrically coupled to the third number K of voltage regulator cells 406 of the array 404. Each row-column cross section of the first switch array 412 includes a switch component configured to control coupling of a respective reference circuit 408 and a respective voltage regulator cell 406. For each voltage regulator set 410 (e.g., set 410-1 in FIG. 4B), a respective set of switch components of the first switch array 412 are enabled to couple the respective reference circuit 408 (e.g., circuit 408-1) to the one or more respective voltage regulator cells 406 (e.g., cells 406-1 and 406-2). Note that, in some implementations, lines connecting the reference circuits 408-1 and 408-2 directly to the voltage regulator cells 406 in the voltage regulator sets 410-1 and 410-2 may not correspond to interconnects and are drawn in FIG. 4B merely for illustrative purposes.

Referring back to FIG. 4A, in some implementations, the PMIC module 112 further includes a mapping module 414 coupled to the first switch array 412. The mapping module 414 is configured to control the switch components of the first switch array 412 to group the voltage regulator cells 406 to form the plurality of voltage regulator sets 410. More specifically, the mapping module 414 is configured to determine whether to enable or disable each of the switch components of the first switch array 412.

In some implementations, the PMIC module 112 further includes a plurality of configurable power planes 416 embedded in a module substrate of the PMIC module 112 or a substrate 202 to which the PMIC module 112 is mounted. Each of the plurality of power rails 116 is electrically coupled to a respective power plane 416, and extends to one or more electrical components (e.g., modules 102-108) to provide a respective rail voltage V_RAILto these components. Each output of voltage regulator cells 406 of a respective voltage regulator set 410 is also electrically coupled to the respective power plane 416, providing the power voltage V_RAILto the respective power plane 416.

Further, referring to FIG. 4B, in some implementations, the PMIC module 112 includes a second switch array 418 (e.g., having the first number M of rows and the third number K of columns, or the first number M of columns and the third number K of rows). For example, rows of the first switch array 412 are electrically coupled to the first number M of power rails 116 or configurable power planes 416, and columns of the second switch array 418 are electrically coupled to outputs of the third number K of voltage regulator cells 406 of the array 404. Each row-column cross section of the second switch array 418 includes a switch component configured to control coupling a respective voltage regulator cell 406 to a respective configurable power plane 416 or to a respective power rail 116. For each voltage regulator set 410 (e.g., set 410-1 in FIG. 4B), a respective set of switch components of the first switch array 412 are enabled to couple the one or more respective voltage regulator cells 406 (e.g., cells 406-1 and 406-2) to the a respective configurable power plane 416 or to the respective power rail 116 (e.g., rail 116-1). Additionally, in some implementations, the second switch array 418 and the first switch array 412 are integrated in a single switch array.

Note that, in some implementations, lines connecting the power rails 116-1 and 116-2 directly to the voltage regulator cells 406 in the voltage regulator sets 410-1 and 410-2 may not correspond to interconnects and are drawn in FIG. 4B merely for illustrative purposes.

In some implementations, the plurality of voltage regulator sets 410 include a first voltage regulator set 410-1 that is configured to output a first rail voltage V_RAIL1(e.g., 1.2V, 0.8V) to a first power rail 116-1, and the first rail voltage is equal to a first reference voltage V_REF1provided by a first reference circuit 408-1. Stated another way, an output voltage level of each voltage regulator set 410 is set by its associated reference voltage, and the voltage regulator set 410 is configured to track its associated reference voltage provided by a respective reference circuit 408.

Referring back to FIG. 4A, in some implementations, the PMIC module 112 further includes a voltage controller 420 coupled to the plurality of reference circuits 408. The voltage controller 420 is configured to generate a digital control signal 422 based on the first rail voltage associated with the first power rail 116-1 and provide the digital control signal 422 to the first reference circuit 408-1 defining the first reference voltage V_REF1. The first power rail 116-1 extends to one or more electrical components (e.g., modules 102-108) to provide the first rail voltage to these components. Characteristics of the first power rail 116-1 (e.g., rail current, rail voltage) are determined based on operation of the one or more electrical components. The first reference voltage of the first reference circuit 408-1 is further determined and set based on the characteristics of the first power rail 116-1. In some implementations, the plurality of reference circuits 408 are identical to one another. The digital control signal 422 determines magnitudes of the reference voltages V_REFoutputted by the plurality of reference circuits 408. Conversely, in some implementations, at least two of the plurality of reference circuits 408 are different from one another. In an example, each reference circuit 408 includes a digital-to-analog converter (DAC).

Additionally, in some implementations, the first voltage regulator set 410-1 further includes a target number N_T(e.g., 2) of voltage regulator cells 406 and is configured to deliver up to a predefined rail current I_RAILto the first power rail 116-1. The target number N_Tis determined based on the predefined rail current I_RAIL, e.g., equal to the predefined rail current I_RAILdivided by a regulator current I_VGCthat is deliverable by each voltage regulator cell 406. Additionally, in some implementations, the PMIC module 112 further includes a voltage controller 420 coupled to the array 404 of voltage regulator cells 406. The voltage controller 420 is configured to determine the target number N_Tbased on the predefined rail current I_RAILassociated with the first power rail 116-1, generate one or more select signals 424 based on the target number N_T, and provide the one or more select signals 424 to the array 404 of voltage regulator cells 406 to select the target number N_Tof voltage regulator cells 406 (e.g., cells 406-1 and 406-2) of the first voltage regulator 116-1. In some implementations, the mapping module 414 is part of the voltage controller 420.

In some implementations, voltage regulator cells 406 in the array 404 of voltage regulator cells 406 are identical to each other. An output voltage of each voltage regulator cell 406 is determined based on a respective reference voltage V_REFreceived by the respective voltage regulator cell 406. The higher a rail current I_RAILof a power rail 116, the larger the target number N_Tof the voltage regulator cells 406 grouped to drive the power rail 116.

Conversely, in some implementations, at least two voltage regulator cells 406 in the array 404 of voltage regulator cells 406 are different from one another. For example, an output voltage of each voltage regulator cell 406 is determined based on a respective reference voltage V_REFreceived by the respective voltage regulator cell 406. The two voltage regulator cells 406 may have different driving capabilities (e.g., different regulator currents). Different numbers of the two voltage regulator cells 406 may be selected and combined based on a rail current I_RAILassociated with a power rail 116 and regulator currents I_VGCof the two voltage regulator cells 406.

FIG. 5 is a schematic diagram of an example voltage regulator cell 406, in accordance with some implementations. In some implementations, the voltage regulator cell 406 includes an input reference interface 502 for receiving a target reference voltage V_REF, an input signal interface 504 for receiving an input signal (e.g., rail voltage V_RAIL), an output interface 506 for providing a rail voltage V_RAILto a power rail (e.g., power rail 116-1 in FIG. 4B), a first feedback path 510 coupling the output interface 506 of the voltage regulator cell 406 to the input signal interface 504 of the voltage regulator cell 406, and an inductor 508 electrically coupled between the input signal interface 504 and the output interface 506.

In some implementations, the voltage regulator cell 406 includes an error amplifier 512, a pulse width modulator 514, a power stage 518, and the feedback path 510. The error amplifier 512 is configured to receive a reference voltage V_REFand a rail voltage V_RAILand generate an amplified difference signal 522. The pulse width modulator 514 is coupled to the error amplifier 512 configured to generate a pulse width modulated (PWM) periodic signal 516 having a pulse width and a feature frequency f. In an example, the pulse width modulator 514 includes a comparator, and receives an input signal 515 having a Sawtooth waveform or a triangular waveform. The pulse width modulator 514 is coupled to the error amplifier 512 and configured to modulate the pulse width of the input signal 515. The power stage 518 is coupled to the pulse width modulator 514 and configured to generate the rail voltage V_RAILbased on the PWM periodic signal 516. In an example, the power stage 518 includes one or more power field effect transistors (FETs). The feedback path 510 is configured to couple an output of the power stage 518 to an input of the error amplifier 512, e.g., jointly with an inductor 508.

In some implementations, the voltage regulator cell 406 includes a signal generator 528, a power stage 518, and a first feedback path 510 coupling an output of the power stage to a signal input of the signal generator 528. The signal generator 528 is configured to receive a target reference voltage V_REFand a rail voltage V_RAILand generate a PWM periodic signal 516 having a target pulse width. The power stage 518 is coupled to the signal generator 528 and configured to generate the rail voltage based on the PWM periodic signal 516 having the target pulse width. Further, in some implementations, in the voltage regulator cell 406, a second feedback path 530 couples the output of the power stage 518 to a signal modulator 532 of the signal generator 528. The second feedback path 530 is configured to pull the rail voltage V_RAILback to the target reference voltage V_REFwhen the rail voltage V_RAILdeviates from the target reference voltage V_REFat a deviation rate higher than a characteristic circuit rate of the voltage regulator cell 406.

Further, in some implementations, the second feedback path 530 further includes a change detector 534 and an amplification and modulation circuit 536. The change detector 534 is coupled to the output of the power stage 518, and configured to detect the rail voltage V_RAILdeviating from the target reference voltage V_REFat the deviation rate. The amplification and modulation circuit 536 is coupled to the change detector 534 and the signal modulator 532, and configured to adjust a pulse width of the PWM periodic signal 516 in real-time, when the rail voltage V_RAILdeviates from the target reference voltage V_REFat the deviation rate. In other words, in some implementations, the change detector 534 is configured to sense fast voltage changes in the feedback voltage signal in the first feedback path 510 (e.g., corresponding to fast voltage changes in an output of the voltage regulator cell 406). The change detector 534 generates a modulation signal to modulate the signal modulator 532, thereby preventing an output of the voltage regulator cell 406 from deviating from the reference voltage V_REF.

State another way, in some implementations, the voltage regulator cell 406 is implemented based on a regulation control loop using one or more of a power stage 518, an integrated on-chip inductor 508, and a feedback voltage signal (e.g., carrying rail voltage V_RAILin a first feedback path 510). The regulation control loop tracks a difference between voltage feedback signal and the selected reference voltage V_REF, and generates pulse width modulated signals (e.g., PWM periodic signal 516) driving the power stage 518. The output of the power stage 518 may drive an integrated on-chip inductor 508.

In some implementations, an inductor 508 and an output filter capacitor 538 forms an output filter. The output filter may be part of, or external to, a respective voltage regulator cell 406. The output filter may partially belong to a respective voltage regulator cell 406. The output filter capacitor 538 may be embedded in a GPU or CPU package substrate, a substrate of the SoC 120 (e.g., substrate 202), or a processor chip 212 (FIG. 2A). In some implementations, for a voltage regulator set 410, output terminals of on-chip inductors 508 of voltage regulator cells 406 of the voltage regulator set 410 correspond to the output interface 506, and are coupled via interconnects to an output filter capacitor 538, which may be external to the voltage regulator cells 406. Stated another way, the voltage regulator cells 406 of the voltage regulator set 410 share, and is routed separately via the interconnects to, a common output filter capacitor 538. Further, in some implementations, the feedback voltage signal carried by the feedback path 510 is connected to the output filter capacitor via the interconnects extending external to the voltage regulator cells 406.

Additionally, in some implementations, a regulation control mechanism of a voltage regulator cell 406 employs dual control loops including the regulation control loop and a transient modulation loop 540. The regulation control loop is based on the first feedback path 510, and configured to modulate the PWM periodic signal 516 based on an error signal (e.g., amplified difference signal 522) generated by integrating a difference between the reference voltage V_REFand the feedback voltage signal. In some implementations, the regulation control loop integrates a difference between the reference voltage V_REFand the feedback voltage signal, and includes a signal modulator 532, which is shared with the transient modulation loop 540. The amplified difference signal 522 reflects integration of the difference between the reference voltage V_REFand the feedback voltage signal, and is applied to modulate the PWM periodic signal 516 and generate a rail voltage V_RAILto be outputted at the output interface 506 of the voltage regulator cell 406. The rail voltage V_RAILsettles at the associated reference voltage V_REF. Additionally, the transient modulation loop 540 is configured to modulate the PWM periodic signal 516 based on detection of transient characteristics of the feedback voltage signal (e.g., the rail voltage V_REF).

FIG. 6 is a conceptual diagram illustrating example two voltage regulator cells 406-1 and 406-2 (also shown in FIG. 4B) for providing a rail voltage V_RAIL, in accordance with some implementations. Each of the two voltage regulator cells 406-1 and 406-2 includes a respective inductor 508 electrically coupled to an output interface 506 of the respective voltage regulator cell 406. In some implementations, for each voltage regulator cell 406-1 or 406-2, the respective inductor 508 is integrated on chip, e.g., monolithically formed on a respective PMIC chip 204. In some implementations, a configurable power plane 416 is embedded in a module substrate of a PMIC module 112 or a substrate 202 of the SoC 120 to which a PMIC module 112 is mounted. The two voltage regulator cells 406-1 and 406-2 may be formed on a common chip substrate 602 or on two distinct chip substrates 602. The output interfaces 506 of the two voltage regulator cells 406-1 and 406-2 are electrically coupled to the power plane 416, which is further coupled to a power rail 116 (not shown on FIG. 6).

In some implementations, the inductor 508 is integrated on the cell substrate 602, e.g., above the signal generator 528, the power stage 518, and/or any other circuits 408, 412, 418, or 420 of the PMIC module 112. An input terminal of the inductor 508 is coupled to an output of the power stage 518, e.g., using a via, a metallic layer, a solder ball, a redistribution layer (RDL), or a combination thereof. In an example, an output terminal of the inductor 508 corresponds to an output of the inductor 508, and is connected to an interconnect that couples the inductor 508 to a bump or a solder ball of the PMIC module 112. The bump or solder ball is applied to electrically couple the PMIC module 112 to other electrical components (e.g., components 102-108) of an SoC 120. In some implementations, each of two terminals of the inductor 508 includes a respective interconnect made of a via, a metallic layer, an RDL, or a combination thereof, and is configured to provide a Kelvin sensing point.

FIG. 7A is a perspective view of an example PMIC chip 204 including a plurality of inductors 508 coupled in a plurality of voltage regulator cells 406, in accordance with some implementations, and FIGS. 7B and 7C are two cross sectional views 720 and 740 of a portion of the PMIC chip 204 shown in FIG. 7A including two inductors 508 of two voltage regulator cells 406, in accordance with some implementations. The PMIC chip 204 has a chip substrate 602 and includes twelve voltage regulator cells 406 formed monolithically on a top surface of the chip substrate 602. Each voltage regulator cell 406 includes a respective inductor 508 integrated on the top surface of the chip substrate 602. Stated another way, the voltage regulator cells 406 (e.g., transistors and metal interconnects) may be formed on the cell substrate 602 and partially underneath the inductor 508. The PMIC chip 204 includes two cross sections AA′ and BB′ that are perpendicular to one another and to the top surface of the chip substrate 602. The cross section AA′ is shown in FIG. 7B, and part of the cross section BB′ is shown in FIG. 7C.

Referring to FIG. 7B, in some implementations, an inductor 508 includes three vias 722, 724, and 726. A first via 722 is coupled between an output a power stage 518) of a respective voltage regulator cell 406 to an input terminal 508A of the inductor 508, driving current toward the inductor 508. In some implementations, a second via 724 is coupled between an output terminal 508B of the respective inductor 508. The output terminal 508B of the respective inductor 508 corresponds to an output port 506 of the voltage regulator cell 406. Alternatively, in some implementations, the second via 724 is coupled between the output terminal 508B of the respective inductor 508 and an input signal interface 504 (FIG. 5). A third via 726 is coupled between the output terminal 508B of the inductor 508 and a power rail 116 powering other components (e.g., components 102-108 in FIG. 1) of an SoC 120, providing current and power to enable operations of the other components of the SoC 120. In some implementations, the third via 726 couples the output terminal 508B of the inductor 508 to the power rail 116 via a configurable power plane 416 (FIG. 6). In some implementations, the third via 726 is vertically aligned with the second via 724. In some implementations not shown, the third via 726 is laterally shifted (i.e., not vertically aligned) with respect to the second via 724.

In some embodiments, the first via 722 and the second via 724 enable Kelvin connections for sensing a current passing a conduction trace of the inductor 508. A current sensing circuit 728 is coupled to the input terminals 508A and the output terminal 508B of the inductor 508, and configured to measure a voltage drop on the inductor 508. Given that a resistance of the inductor 508 is known, the voltage drop is applied to determine a current passing through the inductor 508.

In some implementations, each of two terminals 508A and 508B of the inductor 508 includes a respective interconnect made of a via, a metallic layer, an RDL, or a combination thereof. The respective interconnect forms a Kelvin connection, which may be coupled to a current sensing circuit associated with the voltage regulator cell 406 for sensing an inductor current running through the inductor 508. In some implementations, a distance between Kelvin connections of each voltage regulator cell 406 is substantially uniform in the array 404 of voltage regulator cells 406 (e.g., in FIG. 7A). For each voltage regulator set 410, current balancing among different voltage regulator cells 406 is enabled using a single shared reference circuit 408.

Referring to FIG. 7C, in some implementations, the inductor 508 is formed on top of the cell substrate 602 (e.g., a silicon substrate), and include at least two laminated magnetic thin film layers 742 and 744 wrapping around a conductor 746. The inductor 508 further includes an insulation film layer 748 and a dielectric filling structure 750. The two laminated magnetic thin film layers 742 and 744 are electrically isolated from the conductor 746 by the insulation film layer 748 and a dielectric filling structure 750. In some implementations, there is no gap in an enclosure formed by the two laminated magnetic thin film layers 742 and 744. Conversely, in some implementations, there is a gap in the enclosure formed by the two laminated magnetic thin film layers 742 and 744. Further, in some implementations, each of the two laminated magnetic thin film layers 742 and 744 includes a stack of alternating magnetic thin films and dielectric thin films.

FIG. 8A is a detailed block diagram of an example electronic device 800 that includes a PMIC module 112 implementing location-mapped parameter settings 810, in accordance with some implementations. The PMIC module 112 includes some or all of the components of the PMIC module 112 described with respect to FIGS. 4A and 4B. In some embodiments, the PMIC module 112 includes a plurality of PMIC chips 204 (e.g., chips 204-1, 204A, and 204B in FIGS. 2A and 2B). A plurality of voltage regulator cells 406 are distributed on the plurality of PMIC chips 204, and each of a subset of PMIC chips 204 includes a group of respective voltage regulator cells 406. For example, the substrate 802 corresponds to one of the plurality of PMIC chips 204 (e.g., a PMIC chiplet 204T) of the PMIC module 112, and The PMIC chiplet 204T includes at least a first group 808 of voltage regulator cells 406 and a setting interface 804, which are integrated on the substrate 802. A memory component 806 may be coupled to, or included in, the PMIC chiplet 204T. The first group 808 of voltage regulator cells 406 may include less than all voltage regulator cells 406 or all voltage regulator cells 406 of the PMIC chip 204T. In some embodiments, the first group 808 of voltage regulator cells 406 provide the voltage regulator set 410-1 (FIG. 4B) for driving a first power rail 116-1.

The first group 808 of voltage regulator cells 406 is configured to operate based on parameter settings 810 of individual voltage regulator cells 406 within the first group 808 of voltage regulator cells 406. Based on the parameter settings 810, the first group 808 of voltage regulator cells 406 is configured to output at least one respective rail voltage, and provide the at least one respective rail voltage to one or more power rails 116 (e.g., the power rail 116-1, the power rail 116-2, etc.). In some embodiments, the substrate 802 corresponds to a PMIC chip 204T, and is part of an SoC (e.g., a PMIC of the SoC).

In some embodiments, the memory component 806 stores an encoding table 812 that includes a plurality of register files 814 (e.g., a register file 814-1, a register file 814-2, etc.), where a first register file 814A (e.g., the register file 814-1) of the plurality of register files 814 defines parameter settings 810 for the individual voltage regulator cells of the first group 808 of voltage regulator cells 406. In some embodiments, the memory component 806 includes a memory chip 208 distinct from the substrate 802 of the PMIC chip 204T and the PMIC chip 204T obtains the encoding table 812 from the memory chip 208, which may provide the encoding table 812 to two or more PMIC chips 204. Alternatively, in some embodiments, each of a subset of PMIC chips 204 has a group of respective voltage regulator cells 406, and includes a distinct memory component 806 locally on a respective substrate 802.

In some embodiments, the setting interface 804 is coupled to the memory component 806 (e.g., physically coupled, communicatively coupled, etc.). The setting interface 804 is configured to receive a first parameter setting signal 816 applied to select the first register file 814A (e.g., a configuration register file 814-4) among the plurality of register files for defining the parameter settings 810 for the voltage regulator set 410-1. In some embodiments, the PMIC chiplet 204T is part of an SoC. The setting interface 804 is electrically coupled to (e.g., mate) a set of SOC pins (not shown) located on a substrate of the SoC, and configured to receive a first parameter setting signal 816 from the set of SOC pins. The set of SOC pins are electrically coupled based on a relative location in the SOC, thereby making the first parameter setting signal 816 depend on the relative location of the SoC pins (e.g., a location of the PMIC chiplet 204T) in the SoC.

In some implementations, the settings interface 804 includes a plurality of pins (e.g., a set of pins 822-1-822-3), and the first parameter setting provided by the parameter setting signal 816 includes a set of hardwired pin values, which are received via the plurality of pins and applied to select the first register file 814A for defining the parameter settings 810 for the first group 808 of voltage regulator cells 406 (e.g., one or more of the pins 822). In some implementations, the at least one respective rail voltage includes a first rail voltage (e.g., 5 V, 3.3 V or 1.8 V) provided by a first subset of voltage regulator cells in the first group 808 of voltage regulator cells 406, and output pins of the first subset of voltage regulator cells are electrically coupled to one another and to a first power rail 116-1.

The electronic device 800 includes a plurality of voltage references 408 configured to provide one or more reference voltages (e.g., a first reference voltage provided by the reference circuit 408-1) to the first group 808 of voltage regulator cells 406. The electronic device 800 also includes distribution circuitry including a plurality of switch components (e.g., first switch array 412 and second switch array 418 in FIG. 4B). In some implementations, the electronic device 800 includes a bus that is configured to communicatively couple the first group 808 of voltage regulator cells 406 (e.g., voltage regulator set 410-1) with a corresponding set of voltage references and a subset of distribution circuitry (e.g., first switch array 412 in FIG. 4B). In some embodiments, the plurality of voltage references 408 are provided by the same substrate 802 of the PMIC chiplet 204T including the first group 808 of voltage regulator cells 406. In some embodiments not shown, the plurality of voltage references 408 are provided by a substrate (e.g., substrate 818-1, 818-2) of a PMIC chiplet distinct from the PMIC chiplet 204T. In some embodiments not shown, the plurality of voltage references 408 are provided a substrate of a PMIC chiplet that is dedicated to voltage referencing. In some embodiments not shown, the plurality of voltage references 408 are distributed among a plurality of PMIC chiplets 204 that may or may not include the PMIC chiplet 204T.

In some implementation, the first group 808 of voltage regulator cells 406 is included in one of a plurality of individual chiplets, and each respective chiplet of the plurality of individual chiplets is electrically coupled to a same reference voltage. For example, cells 406-1 and 406-2 may be part of a first chiplet, and each of the respective cells may be coupled to the reference circuit 408-1 providing a same reference voltage.

In some implementations, the substrate 802 includes a first substrate of a plurality of substrates, and the plurality of substrates includes one or more second substrates (e.g., substrates 818-1 and 818-2). In some implementations, each respective second substrate of the plurality of substrates is associated with a respective set of pin values (e.g., pin values associated with the set of pins 822) that are received via a respective parameter setting signal 816′ and applied to select a respective second register file in the encoding table 812 for defining respective parameter settings 810 for respective voltage regulator cells formed on the respective second substrate.

In some implementations, the parameter setting signal 816 corresponds to a location of the substrate 802 with respect to the electronic device 800 (e.g., a processor circuit) to which the substrate 802 is coupled or included, and is applied to select a particular register file based on the location of the substrate 802. In some implementations, the plurality of register files 814 and associated parameter settings correspond to a plurality of predefined locations for receiving the substrate 802 in the electronic device 800 (e.g., an SoC), and the parameter settings 810 defined for the individual voltage regulator cells of the first group 808 of voltage regulator cells 406 match on one of the plurality of predefined locations where the substrate 802 is disposed. In some embodiments, three distinct substrates 802, 818-1, and 818-2 have different chip locations in the electronic device 800, e.g., with reference to a processor module 102 powered by the PMIC module 112 (FIG. 1). Based on the chip locations, the register files 814-1, 814-2, and 814-3 are selected and applied to provide the parameter settings to the voltage regulator cells 406 formed on the substrates 802, 818-1, and 818-2, respectively.

FIG. 8B is a block diagram of an example encoding table 812 of a PMIC module (e.g., PMIC module 112), in accordance with some implementations. In some embodiments, the memory component 806 stores a plurality of table options 826 including the encoding table 812. The table options 826 may be applied to different types of electronic devices, and the encoding table 812 is selected from the table options 826 based on identification information of the electronic device 800. In some embodiments, the memory component 806 is a nonvolatile programmable memory (e.g., a flash memory). For example, in some embodiments, the memory component 806 includes a one-time programmable (OTP) memory 806P. Further, in some embodiments, the OTP memory 806P is programmed with the table options 826 or only the encoding table 812. Alternatively, in some embodiments, the OTP memory 806P is programmed to store an encoding indicator, which is applied to select the encoding table 812 among the table options 826, and the table options 826 are stored in a non-volatile portion of the memory component 806. The memory component 806 may be included in the memory chip 208 or in the PMIC chip 204T.

In some implementations, at least one of the parameter settings 810 of the individual voltage regulator cells of the first group 808 of voltage regulator cells 406 includes an indicator referencing data from another portion of the encoding table 812, distinct from and shared by the plurality of voltage regulator cells 406. For example, the encoding table 812 includes a set of predefined settings options 828, which may be provided in conjunction with settings from the plurality of register files 814.

In some implementations, for the first group 808 of voltage regulator cells 406, at least one of the parameter settings 810 of the individual voltage regulator cells includes an indicator referencing data from another portion of the encoding table 812 distinct from and shared by the plurality of register files 814. For example, in some embodiments, a fast transient detection sensitivity 830 has four predefined sensitivity levels stored in the predefined settings options 828, and the first register file 814A uses an indicator (e.g., “0,” “1,” “2,” and “3) to identify a respective sensitivity level used by the first register file 814 to set the first group 808 of voltage regulator cells 406.

In some implementations, each respective voltage regulator cell of the voltage regulation set 410-1 includes regulation control loop circuitry, one or more power stages (e.g., the power stage 518), one or more integrated on-chip inductors (e.g., on-chip inductor 508), and one or more voltage feedback signals (e.g., the voltage signal received on the feedback path 510). Each respective integrated on-chip inductor 508 of the one or more integrated on-chip inductors can be realized by two laminated magnetic thin film pieces surrounding (e.g., wrapping around) a single conductor. In some implementations, each on-chip inductor 508 has one terminal connecting with an output of power stage circuitry of the one or more power stages. In some embodiments, a connection is realized by vias, chip metal layers, and/or a redistribution layer (an RDL).

In some implementations, each respective integrated on-chip inductor 508 also has one output terminal, which has an outward interconnect to bumps or solder balls of the electronic device 800. In some embodiments, the bumps or solder balls are to form the joint connection between PMIC module 112 and an SoC of the electronic device 800. In some embodiments, the bumps or solder balls associated with the inductor 508 output terminals are to be connected to the terminal of the output filter capacitor.

In some implementations, each respective integrated on-chip inductor 508 also includes an inward interconnect (e.g., realized by vias, chip metal layers, an RDL), and the inward interconnect forms a Kelvin connection for sensing a respective current of the respective integrated on-chip inductor 508. In some implementations, the inward interconnect is connected to the current sensing circuitry associated with the corresponding voltage regulator cell associated with each respective on-chip inductor 508. In some implementation, a sensing distance between two Kelvin sensing contact points on each inductor 508 winding is maintained at a same (e.g., uniform) sensing distance (e.g., for all the integrated inductors 508 of the PMIC).

In some implementations, for a subset of voltage regulator cells of the first group 808 of voltage regulator cells 406, respective output terminals of the integrated on-chip inductors are connected to an output filter capacitor via interconnects outside of the electronic circuit. In some implementations, for the subset of voltage regulator cells, each respective voltage feedback signal is coupled to the output filter capacitor via an interconnect that is not integrated onto the electronic circuit (e.g., outside of the PMIC module 112). In some implementations, the one or more integrated on-chip inductors are fabricated over a footprint of their corresponding voltage regulator cell. More details on each cell 406 of the first group 808 of voltage regulator cells 406 and associated integrated on-chip inductors 508 are discussed above with reference to FIGS. 4A-7C.

In some implementations, the parameter settings 810 stored in the respective register files 814 include parameter settings for controlling the associated operations of electronic components of voltage regulator cells 406. For example, the parameter settings 810 include one or more of: (i) a voltage rail identifier (e.g., rail identifier 830-1); (ii) a DAC signal level (e.g., DAC reference 830-2); (iii) a loop gain parameter (main loop gain control 830-3); (iv) a compensation signal parameter (e.g., main loop compensation control 830-4); (v) a sensitivity parameter (e.g., fast transient detection sensitivity 830-5); and (vi) an amplification parameter (e.g., fast transient signal feedback amplification control 830-6).

In some implementations, each regulator cell 406 includes a regulation control loop circuitry configured to track a difference between a voltage feedback signal and a common voltage reference V_REFselected for the respective voltage regulator cell, and generate, based on the tracked difference between the voltage feedback signal and the common voltage reference, pulse width modulated (PWM) signals driving power stages (e.g., one or more power stages 518). The reference voltage V_REFand a gain of the regulation control loop circuit are set based on the parameter settings 810. In some implementations, a voltage regulator cell 406 includes a transient modulation loop 540 including an amplification and modulation circuit 536 configured for provide a fast transient signal feedback amplification control. The circuit 536 is set based on the amplification control 830-6 of the parameter settings 810 set based on the parameter setting signal 816.

In some embodiments, the parameter settings 810 of the first register file 814A are applied to set all voltage regulator cells of the first group 808 of voltage regulator cells 406. Alternatively, in some embodiments, the first register file 814A (e.g., selected form the register files 814-1 to 814-8) includes a plurality of cell register files 832 corresponding to individual voltage regulator cells 406 within the first group 808. For example, the first group 808 of voltage regulator cells 406 includes sixteen or more voltage regulator cells, and the first register file 814A includes sixteen cell register files 832. Each register file 832 may provide parameter settings 810 to one or more individual voltage regulator cells 406.

FIGS. 9A and 9B illustrate example electronic systems 900 and 950 and associated parameter settings 810 of voltage regulator cells 406, in accordance with some implementations. Each of the electronic systems 900 and 950 includes a different arrangement of chiplets of voltage regulator cells, as well as different associated parameter settings 810, which may be configured to correspond to a particular use case of the respective electronic circuits. As a prophetic example, the electronic system 900 includes a server using one or more artificial intelligence (AI) acceleration graphics processing units (GPUs) 902, and the electronic system 950 is an SoC for a personal computer. Though a skilled artisan will understand that many other use cases and configurations for the provided use cases are possible.

Referring to FIG. 9A, in some embodiments, the electronic system 900 includes a processor 902 (e.g., including the AI GPU(s)) and a plurality of PMIC chips 204 (e.g., eight PMIC chips) distributed at different locations with respect to the processor 902. An encoding table 812 is stored in a memory component 806 and includes a plurality of register files (e.g., files 814-1 to 814-8 in FIG. 8A) corresponding to the different locations of the PMIC chips 204. For example, the PMIC chips 204 include a chiplet 000, and a first register file 814A corresponding to the chiplet 000 is extracted from the encoding table 812 and applied to provide parameter settings 810 of individual voltage regulator cells 406 of the chiplet 000. In this example (FIG. 9A), the first group 808 of voltage regulator cells 406 of the chiplet 000 includes two voltage regulator cells 406 configured to provide a rail voltage jointly. These two voltage regulator cells 406 have the same parameter settings 810 (e.g., Rail ID=1, DAC=2, Loop gain=5, Compensation=8, Sensitivity=5, and Amplification=3). It is noted that, in some situations, each of the parameter settings 810 is defined by a respective indicator (e.g., “1,” “2,” “5”) for selecting one of a set of predefined settings options 828 (FIG. 8B).

In some embodiments, the electronic system 900 includes one or more high bandwidth memories (HBMs) 904, which are coupled to the processor module 102 and/or the PMIC chips 204 by a serial communication bus. Further, in some embodiments, the memory component 806 stores the encoding table 812 is included in the HBMs 904. Alternatively, in some embodiments, the memory component 806 is integrated on the PMIC chips 204.

Referring to FIG. 9B, in some embodiments, the electronic system 950 includes a processor 902 having a plurality of distinct processor units (e.g., CPU 902C, GPU 902G, NPU 902N) and a plurality of PMIC chips 204 (e.g., three PMIC chips labelled as “Chiplet 000,” “Chiplet 001,” and “Chiplet 010”) distributed at respective locations with respect to the processor 902. An encoding table 812 is stored in a memory component 806 and includes a plurality of register files (e.g., files 814-1 to 814-8 in FIG. 8A) corresponding to the different locations of the PMIC chips 204. For example, the PMIC chips 204 include a chiplet 000 and a chiplet 010, and two register files 906A and 906B corresponding to the chiplets 000 and 010 are extracted from the encoding table 812 and applied to provide parameter settings 810 of individual voltage regulator cells 406 of the chiplets 000 and 010. In this example (FIG. 9B), for the chiplet 000, the first group 808 of voltage regulator cells 406 includes two voltage regulator cells 406 configured to provide two distinct rail voltages (e.g., having two distinct rail identifications of “2” and “1”). These two voltage regulator cells 406 have the same parameter settings 810 for Loop Gain, but not for the other parameter settings (e.g., Compensation, Sensitivity, and Amplification).

In some embodiments, the parameter settings 810 of a voltage regulator cell 406 (e.g., “uVR cell 1” for the chiplet 010) are predefined. Conversely, in some embodiments, the parameter settings 810 of a voltage regulator cell 406 (e.g., “uVR cell 0” for the chiplet 010) are undefined or represented by a variable (e.g., “x”), and dynamically defined when the voltage regulator cell 406 is applied to drive a power rail 116.

FIG. 10 is a flow diagram of an example method 1000 for providing an PMIC module 112 including an array 404 of voltage regulator cells 406, which are configured to operate with location-based parameter settings 810, in accordance with some implementations. The method 1000 includes providing (operation 1002) a first group 808 of voltage regulator cells 406 formed on a substrate 802 and configured to operate based on parameter settings 810 of individual voltage regulator cells, output at least one respective rail voltage, and provide the at least one respective rail voltage to one or more power rails 116. The method 1000 includes providing (operation 1004) a memory component 806 coupled to the first group 808 of voltage regulator cells 406. The memory component 806 stores (operation 1006) an encoding table 812 including a plurality of register files 814, and a first register file 814A defines the parameter settings 810 for the individual voltage regulator cells of the first group 808 of voltage regulator cells 406. The method 1000 includes providing (operation 1008) a setting interface 804 coupled to the memory component 806. The settings interface 804 is configured to receive a first parameter setting signal 816 applied to select the first register file 814A among the plurality of register files 814 for defining the parameter settings 810 for the first group 808 of regulator cells 406, e.g., based on a location of the substrate 802. The first group 808 of voltage regulator cells 406 and the settings interface 804 are integrated (operation 1010) on the substrate 802. In some embodiments, the memory component 806 is integrated on the substrate 802 as well.

FIG. 11 is a flow diagram of an example method 1100 for managing power of an electronic device, In some embodiments. The electronic device (specifically, a PMIC module 112) has a substrate 802, a memory component 806, a setting interface 804, and a plurality of voltage regulator cells 406. The substrate 802 corresponds to a PMIC chip 204, and a first group 808 of voltage regulator cells 406 and the settings interface 804 are integrated on the substrate 802. The memory component 806 stores an encoding table 812 including a plurality of register files 814. In an example, the memory component 806 may be part of a memory chip 208. In another example, the memory component 806 may be part of the substrate 406. A first parameter setting signal 816 is received (operation 1102) by the PMIC chip 204 via the setting interface 804. Based on the first parameter setting signal 816, a first register file 814A is selected (operation 1104) from the plurality of register files 814 of the encoding table 812 stored on the memory component 806. The first register file 814A defines parameter settings 810 for the individual voltage regulator cells of the first group 808 of voltage regulator cells 406. The first group 808 of voltage regulator cells 406 are identified and set (operation 1104) based on the parameter settings 810 defined by the first register file 814A. After the first group 808 of voltage regulator cells 406 are set with the parameter settings 810 of the first register file 814A, the first group 808 of voltage regulator cells 406 generates (operation 1108) at least one respective rail voltage V_RAILto drive one or more power rails 116.

Each of the above identified elements may be stored in one or more memory devices, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software or firmware programs, procedures, modules or data structures, and thus various subsets of these modules may be combined or otherwise re-arranged in various implementations. In some implementations, the memory, optionally, stores a subset of the modules and data structures identified above. Furthermore, the memory, optionally, stores additional modules and data structures not described above.

Numerous examples of aspects of the disclosure are described as numbered clauses (1, 2, 3, etc.) for convenience. These are provided as examples, and do not limit the subject technology. Identifications of the figures and reference numbers are provided below merely as examples and for illustrative purposes, and the clauses are not limited by those identifications.

- Clause 1. An electronic device, comprising: a first group of voltage regulator cells configured to operate based on parameter settings of individual voltage regulator cells, output at least one respective rail voltage, and provide the at least one respective rail voltage to one or more power rails; a memory component coupled to the first group of voltage regulator cells, wherein the memory component stores an encoding table including a plurality of register files, and a first register file defines parameter settings for the individual voltage regulator cells of the first group of voltage regulator cells; a setting interface coupled to the memory component, the setting interface configured to receive a first parameter setting signal applied to select the first register file among the plurality of register files for defining the parameter settings for the first group of voltage regulator cells; and a substrate on which the first group of voltage regulator cells and the setting interface are integrated.
- Clause 2. The electronic device of clause 1, wherein for the first group of voltage regulator cells, at least one of the parameter settings of the individual voltage regulator cells includes an indicator referencing data from another portion of the encoding table distinct from and shared by the plurality of register files.
- Clause 3. The electronic device of clause 1 or clause 2, further comprising: a plurality of voltage references configured to provide one or more reference voltages to the first group of voltage regulator cells; a distribution circuitry including a plurality of switch components; and a bus configured to communicatively couple the first group of voltage regulator cells with a corresponding set of voltage references and a subset of distribution circuitry.
- Clause 4. The electronic device of any one of clause 1 to clause 3, wherein the substrate is part of a system-on-a-chip (SOC).
- Clause 5. The electronic device of any one of clause 1 to clause 4, wherein the memory component stores a plurality of table options including the encoding table, and is a nonvolatile programmable memory, e.g., one-time programmable (OTP) memory, and the encoding table is selected based on data written in the nonvolatile programmable memory for setting at least the first group of voltage regulator cells based on power requirements of the one or more power rails.
- Clause 6. The electronic device of any one of clause 1 to clause 5, wherein the setting interface includes a plurality of pins, and the first parameter setting signal includes a set of hardwired pin values, which are received via the plurality of pins and applied to select the first register file for defining the parameter settings for the first group of voltage regulator cells.
- Clause 7. The electronic device of any one of clause 1 to clause 6, wherein the first parameter setting signal corresponds to a location of the substrate with respect to a processor circuit to which the substrate is coupled, and is applied to select the first register file of the plurality of register files based on the location of the substrate.
- Clause 8. The electronic device of any one of clause 1 to clause 7, wherein the plurality of register files and associated parameter settings correspond to a plurality of predefined locations for receiving the substrate in an SoC, and the parameter settings defined for the individual voltage regulator cells of the first group of voltage regulator cells match on one of the plurality of predefined locations where the substrate is disposed.
- Clause 9. The electronic device of any one of clause 1 to clause 8, wherein: the substrate includes a first substrate of a plurality of substrates; the plurality of substrates includes one or more second substrates; and each respective second substrate of the plurality of substrates is associated with a respective set of pin values that are received via a first parameter setting signal and applied to select a respective second register file in the encoding table for defining respective parameter settings for respective voltage regulator cells formed on the respective second substrate.