FIG. 4 is a diagram describing a partial refresh operation according to some example embodiments of the present disclosure. Referring to FIG. 4, the storage controller 110 may perform the partial refresh operation. The storage controller 110 may include the first sub-block sBLK1, the second sub-block sBLK2, the third sub-block sBLK3, the fourth sub-block sBLK4, the power supply circuit 111p, and the refresh manager 112.

To perform the partial refresh operation, the refresh manager 112 may perform a collection operation on valid data distributed into the first and fourth sub-blocks sBLK1 to sBLK4.

For example, before perform the collection operation, the first sub-block sBLK1 may include the first memory region MR1 storing the first data DT1 being valid, and the second, third, and fourth memory regions MR2, MR3, and MR4 storing the second, third, and fourth data DT2, DT3, and DT4 being invalid. The second sub-block sBLK2 may include the sixth memory region MR6 storing the sixth data DT6 being valid, and the fifth, seventh, and eighth memory regions MR5, MR7, and MR8 storing the fifth, seventh, and eighth data DT5, DT7, and DT8 being invalid. The third sub-block sBLK3 may include the ninth memory region MR9 storing the ninth data DT9 being valid, and the tenth, eleventh, and twelfth memory regions MR10, MR11, and MR12 storing the tenth, eleventh, and twelfth data DT10, DT11, and DT12 being invalid. The fourth sub-block sBLK4 may include the fifteenth memory region MR15 storing the fifteenth data DT15 being valid, and the thirteenth, fourteenth, and sixteenth memory regions MR13, MR14, and MR16 storing the thirteenth, fourteenth, and sixteenth data DT13, DT14, and DT16 being invalid.

The refresh manager 112 may perform the collection operation on valid data distributed into the first and fourth sub-blocks sBLK1 to sBLK4, based on validity bitmap information stored in the validity bitmap register 113 of FIG. 1. The collection operation may refer to an operation of overwriting valid data of an inactive sub-block to an invalid memory region of an active sub-block. The inactive sub-block may refer to a sub-block which is not provided with the refresh voltage during the partial refresh operation. The activate sub-block may refer to a sub-block which is provided with the refresh voltage during the partial refresh operation.

For example, during the partial refresh operation, the refresh manager 112 may determine the second to fourth sub-blocks sBLK2 to sBLK4 as inactive sub-blocks and may determine the first sub-block sBLK1 as an active sub-block. The collection operation may include an operation of overwriting the sixth data DT6 being valid to the second memory region MR2, an operation of overwriting the ninth data DT9 being valid to the third memory region MR3, and an operation of overwriting the fifteenth data DT15 being valid to the fourth memory region MR4. The overwritten data DT6, DT9, and DT15 may be referred to as “migrated data”.

After the collection operation is performed, all the valid data of the first and fourth sub-blocks sBLK1 to sBLK4 may be collected (i.e., stored) in the first sub-block sBLK1 being an active sub-block. For example, the first and fourth memory regions MR1 to MR4 of the first sub-block sBLK1 may respectively store the first data DT1 being valid, the sixth data DT6 being valid, the ninth data DT9 being valid, and the fifteenth data DT15 being valid.

After the collection operation is performed, because the valid data DT6, DT9, and DT15 of the second to fourth sub-blocks sBLK2 to sBLK4 being inactive sub-blocks are copied (i.e., migrated) to the first sub-block sBLK1 being an active sub-block, the refresh operation on the second to fourth sub-blocks sBLK2 to sBLK4 may be unnecessary. Because the first sub-block sBLK1 includes all the valid data DT1, DT6, DT9, and DT15, even though the refresh operation on the first sub-block sBLK1 is only performed, the reliability of all the valid data DT1, DT6, DT9, and DT15 may be maintained.

Under control of the refresh manager 112, the power supply circuit 111p may provide the first refresh voltage VRF1 to the first sub-block sBLK1 such that the partial refresh operation corresponding to the first sub-block sBLK1 is performed. Because there is performed the refresh operation associated with only the first sub-block sBLK1 among the first and fourth sub-blocks sBLK1 to sBLK4, the first sub-block sBLK1 is marked by “ON” in association with the refresh operation, and the second to fourth sub-blocks sBLK2 to sBLK4 are marked by “OFF” in association with the refresh operation.

Because the first refresh voltage VRF1 is provided only to the first sub-block sBLK1 among the first and fourth sub-blocks sBLK1 to sBLK4 during the partial refresh operation, power consumption may be reduced. For example, because refresh voltages are not provided to the second to fourth sub-blocks sBLK2 to sBLK4 being inactive sub-blocks, the power consumption of the partial refresh operation may be smaller than the power consumption of the full refresh operation.

As described above, according to example embodiments of the present disclosure, the storage controller 110 may reduce power consumption in the refresh operation, by collecting the valid data DT1, DT6, DT9, and DT15 distributed among the plural sub-blocks sBLK1 to sBLK4 in the first sub-block sBLK1 being an active sub-block and performing the partial refresh operation on only the first sub-block sBLK1 where the valid data DT1, DT6, DT9, and DT15 are collected.

For better understanding of the present disclosure, the description is given as each of the four sub-blocks sBLK1 to sBLK4 includes four memory regions. However, the number of sub-blocks associated with the partial refresh operation may be more than or less than “4”, and the number of memory regions included in one sub-block may be more than or less than “4”. Also, the description is given as the number of active sub-blocks where valid data are to be collected is “1”, but valid data may be distributed and collected in two or more active sub-blocks.

FIG. 5 is a diagram describing a collection operation of a storage controller according to some example embodiments of the present disclosure. Referring to FIG. 5, the storage controller 110 may include the volatile memory device 111, the refresh manager 112, the validity bitmap register 113, and the metadata table 114.

The volatile memory device 111 may include the power supply circuit 111p, the first sub-block sBLK1, and the second sub-block sBLK2. Under control of the refresh manager 112, the power supply circuit 111p may supply the refresh voltage to the first sub-block sBLK1. The size of each of the first and second sub-blocks sBLK1 and sBLK2 may be the minimum size capable of supporting the refresh operation of the volatile memory device 111.

The first sub-block sBLK1 may include the first to fourth memory regions MR1 to MR4 respectively storing the first and fourth data DT1 to DT4. The first and second data DT1 and DT2 may be valid data. The third and fourth data DT3 and DT4 may be invalid data.

The second sub-block sBLK2 may include the fifth to eighth memory regions MR5 to MR8 respectively storing the fifth to eighth data DT5 to DT8. The sixth data DT6 may be valid data. The fifth, seventh, and eighth data DT5, DT7, and DT8 may be invalid data.

The refresh manager 112 may communicate with the volatile memory device 111, the validity bitmap register 113, and the metadata table 114. The refresh manager 112 may collect distributed valid data in an active sub-block where the partial refresh operation is to be performed and may perform the partial refresh operation corresponding to the active sub-block where the valid data are collected.

The validity bitmap register 113 may store validity bitmap information VBI. The refresh manager 112 may update the validity bitmap information VBI, based on the memory operation (e.g., a write operation, an overwrite operation, or a delete operation) performed in the volatile memory device 111. The validity bitmap information VBI may indicate whether the first to eighth data DT1 to DT8 respectively stored in the first to eighth memory regions MR1 to MR8 of the volatile memory device 111 are valid or invalid, in a type of a bit string.

When a memory region corresponding to each of bits constituting the bit string stores valid data, the bit corresponding to the memory region may store a first logical value (e.g., “1”); when a memory region corresponding to each of bits constituting the bit string stores invalid data, the bit corresponding to the memory region may store a second logical value (e.g., “0”). For example, the validity bitmap information VBI may include a bit string of “11000100”.

The metadata table 114 may store mapping information MI including a fixed index value and a migration index value. The fixed index value may be uniquely assigned to a memory region. The migration index value may be used to identify data migrated by the collection operation. Before the collection operation is performed, the fixed index value and the migration index value mapped by the mapping information MI may be identical to each other. After the collection operation is performed, the mapping information MI may map the fixed index value corresponding to the memory region and the migration index value corresponding to data migrated (or overwritten) by the collection operation.

Below, the collection operation of the storage controller 110 of the present disclosure will be described in detail.

In a first operation {circle around (1)}, the refresh manager 112 may determine whether a low-power mode is available, based on the validity bitmap information VBI stored in the validity bitmap register 113. The low-power mode may support the partial refresh operation.

For example, the validity bitmap information VBI may indicate that the first and second sub-blocks sBLK1 and sBLK2 store three valid data DT1, DT2, and DT6. The refresh manager 112 may select the first sub-block sBLK1 among the first and second sub-blocks sBLK1 and sBLK2 as an active sub-block. Because the size of the selected active sub-block is equal to or larger than the size of the three valid data DT1, DT2, and DT6, the refresh manager 112 may determine that the low-power mode is available.

In a second operation {circle around (2)}, the refresh manager 112 may overwrite the sixth data DT6 stored in the sixth memory region MR6 of the second sub-block sBLK2 to the third memory region MR3 of the first sub-block sBLK1 based on the validity bitmap information VBI. In other words, the refresh manager 112 may collect valid data in an active sub-block by overwriting valid data of an inactive sub-block to an invalid memory region of the active sub-block.

In some example embodiments, the refresh manager 112 may swap the sixth data DT6 of the sixth memory region MR6 of the second sub-block sBLK2 with the third data DT3 of the third memory region MR3 of the first sub-block sBLK1 based on the validity bitmap information VBI. For example, when the volatile memory device 111 supports a swap function of swapping two data stored at different physical locations, the refresh manager 112 may swap valid data of an inactive sub-block and invalid data of an active sub-block for the collection operation.

In a third operation {circle around (3)}, the refresh manager 112 may store the mapping information MI of the fixed index value of “3” corresponding to the third memory region MR3 and the migration index value of “6” corresponding to the overwritten sixth data DT6 in the metadata table 114. Also, to uniquely identify the location of the overwritten sixth data DT6, the refresh manager 112 may further store the mapping information MI of the fixed index value of “6” corresponding to the sixth memory region MR6 and the migration index value of “3” corresponding to the third data DT3 deleted by the overwriting in the metadata table 114.

Because the third data DT3 are invalid data, the reliability of the third data DT3 may not be important. Regardless of whether the third data DT3 are actually stored in the sixth memory region MR6, the refresh manager 112 may store the mapping information MI of the fixed index value of “6” corresponding to the sixth memory region MR6 and the migration index value of “3” corresponding to the third data DT3 in the metadata table 114.

In a fourth operation {circle around (4)}, the refresh manager 112 may perform the partial refresh operation corresponding to the first sub-block sBLK1. For example, the refresh manager 112 may control the power supply circuit 111p. Under control of the refresh manager 112, the power supply circuit 111p may supply the refresh voltage to the first sub-block sBLK1. In this case, the power supply circuit 111p may not provide the refresh voltage to the second sub-block sBLK2. The power consumption of the storage controller 110 may be reduced by performing the partial refresh operation on only an active sub-block, in which valid data are collected, instead of performing the full refresh operation on plural sub-blocks where valid data are distributed.

FIG. 6 is a diagram describing a restore operation of a storage system according to some example embodiments of the present disclosure. Referring to FIG. 6, the storage controller 110 may include the volatile memory device 111, the refresh manager 112, the validity bitmap register 113, and the metadata table 114.

The volatile memory device 111 may include the power supply circuit 111p, the first sub-block sBLK1, and the second sub-block sBLK2. Under control of the refresh manager 112, the power supply circuit 111p may supply the refresh voltage to the first and second sub-blocks sBLK1 and sBLK2.

The first sub-block sBLK1 may include the first and fourth memory regions MR1 to MR4 respectively storing the first, second, sixth, and fourth data DT1, DT2, DT6, and DT4. The first, second, and sixth, data DT1, DT2, and DT6 may be valid data. The sixth data DT6 may be migrated from the second sub-block sBLK2 to the first sub-block sBLK1 by a previous collection operation. The fourth data DT4 may be invalid data.

The second sub-block sBLK2 may include the fifth to eighth memory regions MR5 to MR8. During a previous partial refresh operation, the second sub-block sBLK2 may not be provided with the refresh voltage. Each of the fifth to eighth memory regions MR5 to MR8 may store data (i.e., invalid data) whose reliability is damaged as the capacitor is discharged.

The refresh manager 112 may communicate with the volatile memory device 111, the validity bitmap register 113, and the metadata table 114. After the partial refresh operation is performed, the refresh manager 112 may perform the full refresh operation and the restore operation in response to receiving a low-power mode exit command. The restore operation may refer to an operation of restoring valid data collected for the partial refresh operation so as to be distributed into original sub-blocks.

The validity bitmap register 113 may store the validity bitmap information VBI. The validity bitmap information VBI may be independent for the collection operation and the restore operation. For example, the validity bitmap information VBI may not change even if a collection operation or recovery operation is performed. Before the collection operation is performed and after the restore operation is performed, the validity bitmap information VBI may indicate whether the data DT1 to DT8 respectively stored in the memory regions MR1 to MR8 are valid or invalid, in a type of a bit string. For example, the validity bitmap information VBI may include a bit string of “11000100”.

The metadata table 114 may store the mapping information MI of the fixed index value and the migration index value. The mapping information MI may indicate whether valid data are migrated by the collection operation and whether valid data are migrated from any location. After the restore operation is completed, the metadata table 114 may be initialized by the refresh manager 112. In the initialized metadata table 114, the mapping information MI may map the fixed index value and the migration index value which are identical to each other.

Below, the restore operation of the storage controller 110 of the present disclosure will be described in detail.

In a first operation {circle around (1)}, the refresh manager 112 may perform the full refresh operation corresponding to the first and second sub-blocks sBLK1 and sBLK2. For example, the storage controller 110 may perform the partial refresh operation in the low-power mode. The refresh manager 112 may receive a low-power mode exit command during the low-power mode. The refresh manager 112 may control the power supply circuit 111p in response to the low-power mode exit command. Under control of the refresh manager 112, the power supply circuit 111p may supply the refresh voltages to the first and second sub-blocks sBLK1 and sBLK2.

In a second operation {circle around (2)}, the refresh manager 112 may read the mapping information MI stored in the metadata table 114. The mapping information MI may map the fixed index value of “3” corresponding to the third memory region MR3 and the migration index value of “6” corresponding to the overwritten sixth data DT6.

In a third operation {circle around (3)}, the refresh manager 112 may restore the sixth data DT6 based on the mapping information MI. For example, by referring to the mapping information MI, the refresh manager 112 may identify the fixed index value of “3” different from the migration index value of “6” from among the fixed index values of “1”, “2”, “3”, and “4” corresponding to the first to fourth memory regions MR1 to MR4 of the first sub-block sBLK1 being an active sub-block. By referring to the migration index value of “6” mapped to the identified fixed index value of “3”, the refresh manager 112 may copy the sixth data DT6 being valid to the sixth memory region MR6 corresponding to the fixed index value of “6” being identified to the migration index value of “6”. The copy may be performed in an overwrite manner.

After the sixth data DT6 of the third memory region MR3 are copied to the sixth memory region MR6, the third memory region MR3 may maintain the sixth data DT6 as invalid data. The refresh manager 112 may restore all the migrated valid data of the active sub-block and may then initialize the metadata table 114.

FIG. 7 is a flowchart describing a method of operating a storage controller according to some example embodiments of present the plurality disclosure. Referring to FIG. 7, the storage controller 110 may include the refresh manager 112 and the volatile memory device 111.

In operation S105, the storage controller 110 may operate in a normal power node. The normal power node may support the full refresh operation on sub-blocks of the volatile memory device 111. The storage controller 110 may update the validity bitmap information VBI based on the memory operation in the normal power node. The validity bitmap information VBI may indicate validity or invalidity of data stored in each of memory regions corresponding to the sub-blocks of the volatile memory device 111.

In operation S110, the refresh manager 112 may receive a low-power mode command. The low-power mode may support the partial refresh operation. For example, the refresh manager 112 may receive the low-power mode command from the external host device or the internal firmware module.

In operation S120, the refresh manager 112 may determine whether the low-power mode is available, based on the validity bitmap information VBI. For example, the refresh manager 112 may identify the number of valid data based on the validity bitmap information VBI; when the size of at least one selected active sub-block is equal to or larger than the product of the number of valid data and the size of the memory region, the refresh manager 112 may determine that the low-power mode is available.

In operation S130, the refresh manager 112 may perform the collection operation. The collection operation may refer to an operation of overwriting valid data of an inactive sub-block to an invalid memory region of an active sub-block.

In operation S140, the refresh manager 112 may receive the partial refresh operation. The partial refresh operation may refer to an operation of providing the refresh voltage only to an active sub-block among the sub-blocks of the volatile memory device 111. This may be described as the storage controller 110 operates in the low-power mode.

In operation S150, the refresh manager 112 may return a state response indicating whether the low-power mode is applied. The state response may be returned to a component which provides the low-power mode command in operation S110. For example, the refresh manager 112 may return, to the external host device or the internal firmware module, a success response indicating that the low-power mode is applied or a failure response indicating that the low-power mode is not applied.

In operation S160, the refresh manager 112 may receive the low-power mode exit command. When the low-power mode ends, the storage controller 110 may operate in the normal power node. For example, the refresh manager 112 may receive the low-power mode exit command from the external host device or the internal firmware module.

In operation S170, the refresh manager 112 may perform the full refresh operation. The full refresh operation may refer to an operation of providing the refresh voltages to the sub-blocks of the volatile memory device 111.

In operation S180, the refresh manager 112 may perform the restore operation. The restore operation may refer to an operation of copying valid data migrated from an inactive sub-block to an active sub-block by the collection operation to a memory region of the original inactive sub-block. The description may be given as after the restore operation is completed, the storage controller 110 operates in the normal power node.

In operation S190, the refresh manager 112 may return a done response. The done response may be returned to a component which provides the low-power mode exit command in operation S160. For example, the refresh manager 112 may return, to the external host device or the internal firmware module, the done response indicating that the low-power mode ends and the normal power node is applied.

FIG. 8 is a flowchart describing some operations of the flowchart of FIG. 7, according to some example embodiments of the present disclosure. Referring to FIGS. 7 and 8, the storage controller 110 may include the refresh manager 112 and the volatile memory device 111. Operation S210 and operation S211 may correspond to operation S110. Operation S221, Operation S222, and operation S223 may correspond to operation S120. Operation S231, operation S232, operation S233, operation S234, and operation S235 may correspond to operation S130. Operation S240 may correspond to operation S140. Operation S251 and operation S252 may correspond to operation S150.

In operation S210, the refresh manager 112 may receive power limit information from the external host device or the internal firmware module. The power limit information may be used to determine the availability of the low-power mode. For example, the power limit information may include a level of a power supplied from the external host device, the number of sub-blocks in which the collection operation will be performed, the size of a sub-block, the number of memory regions mapped to a sub-block, the size of a memory region, the number of active sub-blocks, the number of inactive sub-blocks, a limit time of the entering of the low-power mode, a limit time of the exit of the low-power mode, a limit time of a success response, a limit time of a failure response, etc.

In operation S211, the refresh manager 112 may receive the low-power mode command from the external host device or the internal firmware module. The low-power mode may support the partial refresh operation.

In some example embodiments, the order of operation S210 and operation S211 may be modified. For example, operation S210 may be performed prior to operation S211, operation S211 may be performed prior to operation S210, or operation S210 and operation S211 may be performed in parallel.

In operation S221, the refresh manager 112 may count the valid memory regions MR of the volatile memory device 111 based on the validity bitmap information VBI. For example, the refresh manager 112 may count at least one valid memory region MR among a plurality memory regions MR corresponding to the validity bitmap information VBI.

In operation S222, the refresh manager 112 may select at least one sub-block sBLK to be refreshed in the volatile memory device 111. In detail, the refresh manager 112 may select at least one sub-block sBLK, to which the partial refresh operation is to be applied, from among the plurality of sub-blocks sBLK corresponding to the validity bitmap information VBI. The at least one sub-block sBLK thus selected may be referred to as an “active sub-block”. Unselected sub-blocks sBLK, that is, the remaining sub-blocks sBLK may be referred to as “inactive sub-blocks”.

In operation S223, the refresh manager 112 may determine whether a condition of the low-power mode is satisfied, based on the counted number of valid memory regions MR and the at least one selected sub-block sBLK. The condition may be determined based on the power limit information in operation S210.

For example, when the size of the at least one selected sub-block sBLK is larger than or equal to the product of the counted number of valid memory regions MR and the size of the memory region MR, the refresh manager 112 may determine that the condition of the low-power mode is satisfied.

When it is determined that the condition of the low-power mode is satisfied, the refresh manager 112 may perform operation S231.

In operation S231, the refresh manager 112 may find the valid memory region MR of the inactive sub-block sBLK of the volatile memory device 111.

In operation S232, the refresh manager 112 may find the invalid memory region MR of the active sub-block sBLK of the volatile memory device 111.

In operation S233, the refresh manager 112 may overwrite the valid data DT of the valid memory region MR of the inactive sub-block sBLK to the invalid memory region MR of the active sub-block sBLK.

In operation S234, the refresh manager 112 may update the migration index value of the overwritten data DT.

Operation S231 to operation S234 may be collectively referred to as a “sub-collection operation”. The sub-collection operation may refer to an operation of migrating one valid data DT of the inactive sub-block sBLK.

In operation S235, the refresh manager 112 may determine whether the valid data DT of all the valid memory regions MR corresponding to the validity bitmap information VBI are collected in the active sub-block sBLK.

When the valid data DT which are not collected (or migrated) are present in the valid memory region MR of the inactive sub-block sBLK, the refresh manager 112 may again perform operation S231 to operation S234 in association with any other valid memory region MR not collected (or whose valid data are not collected). When all the valid memory regions MR (or valid data of all the valid memory regions MR) are collected to the active sub-block sBLK, the refresh manager 112 may perform operation S240.

Operation S231 to operation S235 may be collectively referred to as a “collection operation”. The collection operation may refer to an operation of migrating all the valid data DT of the inactive sub-block sBLK to the active sub-block sBLK.

In operation S240, the refresh manager 112 may perform the partial refresh operation corresponding to the active sub-block sBLK of the volatile memory device 111.

In operation S251, the refresh manager 112 may return the success response, which indicates that the low-power mode is applied, to the external host device or the internal firmware module.

Returning to operation S223, when it is determined that the condition of the low-power mode is not satisfied, the refresh manager 112 may perform operation S252.

In operation S252, the refresh manager 112 may receive the failure response, which indicates that the low-power mode is not applied, to the external host device or the internal firmware module.

FIG. 9 is a flowchart describing some operations of FIG. 7, according to some example embodiments of the present disclosure. Referring to FIGS. 7 and 9, the storage controller 110 may include the refresh manager 112 and the volatile memory device 111. Operation S360 may correspond to operation S160. Operation S370 may correspond to operation S170. Operation S381, Operation S382, and operation S383 may correspond to operation S180. Operation S390 may correspond to operation S190.

In operation S360, the refresh manager 112 may receive the low-power mode exit command from the external host device or the internal firmware module. When the low-power mode ends, the storage controller 110 may operate in the normal power node. The normal power mode may support the full refresh operation.

In operation S370, the refresh manager 112 may perform the full refresh operation. The full refresh operation may refer to an operation of providing the refresh voltages to both the active sub-block sBLK and the inactive sub-block sBLK.

In operation S381, the refresh manager 112 may find the overwritten data DT by referring to the mapping information MI. For example, the refresh manager 112 may identify the mapping information MI in which the fixed index value and the migration index value do not coincide.

In operation S382, the refresh manager 112 may copy the overwritten data DT to the original memory region MR by referring to the migration index value. For example, the refresh manager 112 may copy the data DT to the memory region MR corresponding to the fixed index value identical to the migration index value.

Operation S381 and operation S382 may be collectively referred to as a “sub-restore operation”. The sub-restore operation may refer to an operation of copying one data DT migrated to the active sub-block sBLK by the sub-collection operation to an original memory region before the collection operation.

In operation S383, the refresh manager 112 may determine whether all the valid memory regions MR (i.e., the memory regions MR storing the overwritten data DT) are restored, based on the mapping information MI corresponding to the memory regions MR belonging to the active sub-block sBLK.

When there is a memory region MR which is not restored, the refresh manager 112 may again perform operation S381 and operation S382 in association with any other overwritten data DT of the memory region MR not restored. When all the valid memory regions MR are restored, the refresh manager 112 may perform operation S390.

Operation S381, operation S382, and operation S383 may be collectively referred to as a “restore operation”. The restore operation may refer to an operation of copying all the valid data DT migrated by the collection operation to the original memory region MR.

In operation S390, the refresh manager 112 may return the done response, which indicates that the low-power mode ends and the normal power mode is applied, to the external host device or the internal firmware module. Also, the refresh manager 112 may initialize the mapping information MI such that the migration index value coincides with the fixed index value.

FIG. 10 is a block diagram describing a volatile memory device according to some example embodiments of the present disclosure. Referring to FIG. 10, the volatile memory device 111 may communicate with the refresh manager 112.

The volatile memory device 111 may include a volatile memory controller and a plurality of memory chips. The volatile memory controller may communicate with the refresh manager 112. The volatile memory controller may store data in memory chips or may read data stored therein. Also, the volatile memory controller may apply the refresh voltages to memory chips under control of the refresh manager 112.

The volatile memory controller may include the power supply circuit 111p, a first memory channel CH1, and a second memory channel CH2. Under control of the refresh manager 112, the power supply circuit 111p may supply the write voltage, the read voltage, or the refresh voltage to the first and second memory channels CH1 and CH2.

The first memory channel CH1 may be connected to the corresponding memory chips through memory ways WY11, WY12, WY13, and WY14. Each of the memory chips may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of sub-blocks sBLK. The size of the sub-block sBLK may be the smallest size capable of providing the refresh voltage through the power supply circuit 111p. Each of the plurality of sub-blocks sBLK may include a plurality of memory regions MR.

As in the above description, the second memory channel CH2 may be connected to the corresponding memory chips through memory ways WY21, WY22, WY23, and WY24. Each of the memory chips may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of sub-blocks sBLK. Each of the plurality of sub-blocks sBLK may include a plurality of memory regions MR.

For better understanding of the present disclosure, the description is given as the volatile memory device 111 includes two memory channels CH1 and CH2 and one memory channel is connected to four memory ways, but the present disclosure is not limited thereto. The volatile memory device 111 may be implemented to include a single memory channel or to include two or more memory channels. Also, the number of memory ways connected to one memory channel may be less than or more than “4”.