1a further comprises, in addition to the components of the semiconductor device 1, a feedback resistor Rf, a buffer 11, and an inverter 12.

In the semiconductor device 1a, the gates of the transistors MP1, MN1 are each connected to the external terminal XI, and the drains of the transistors MP1, MN1 are each connected to the external terminal XO. The crystal oscillator 13 is provided between the external terminal XI and the external terminal XO of the semiconductor device 1a, outside the semiconductor device 1a. That is, the crystal oscillator 13 is provided between the gates of the transistors MP1, MN1 and the drains of the transistors MP1, MN1, via the external terminals XI, XO of the semiconductor device 1a.

The capacitive element Cxi is provided between the external terminal XI of the semiconductor device 1a and the reference voltage terminal GND, outside the semiconductor device 1a. The capacitive element Cxo is provided between the external terminal XO of the semiconductor device 1a and the reference voltage terminal GND, outside the semiconductor device 1a.

In the semiconductor device 1a, the feedback resistor Rf is provided between the gates of the transistors MP1, MN1 and the drains of the transistors MP1, MN1. The buffer 11 is a so-called Schmitt buffer, which drives and outputs the output signals of the drains of the transistors MP1, MN1. The inverter 12 outputs the inverted signal of the output signal of the buffer 11. The output signal of the inverter 12 is supplied to the logic circuit 10 as a clock signal.

FIG. 5 is a diagram showing the simulation results of the EYE opening (EYE pattern) in the semiconductor system of the comparative example. In the semiconductor system of the comparative example, compared to the semiconductor system 3, the resistance values of the resistive elements R1, R2 are set to 002. Therefore, the power supply voltage VDD2 of the second power supply voltage line VDD2 indicates the same 3.3V as the power supply voltage VDD. Furthermore, the power supply voltage GND2 of the second reference voltage line GND2 indicates the same 0V as the reference voltage GND.

In FIG. 5, the oscillation frequency of the crystal oscillator 13 is 16 MHz, the scale of the logic circuit 10 is 40K gates when converted to NAND gates, the frequency of the main clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is assumed to be 50%. Furthermore, in FIG. 5, the amplitude of the external noise is assumed to be 3.3V±100 mV, and the frequency of the external noise is assumed to be 40 MHz.

In this case, the semiconductor system of the comparative example showed a jitter of 6.52 nsec/100 mV.

FIG. 6 is a diagram showing the simulation results of the EYE opening in the semiconductor system 3. In FIG. 6, while the power supply voltage VDD of the first power supply voltage line VDD indicates 3.3V, the power supply voltage VDD2 of the second power supply voltage line VDD2 indicates 2.7V due to the voltage drop by I_dark×R1. Moreover, in FIG. 6, while the reference voltage GND of the first reference voltage line GND indicates 0V, the reference voltage GND2 of the second reference voltage line GND2 indicates 0.5V due to the voltage rise by I_dark×R2.

In the semiconductor system 3, when simulations were conducted under the same conditions as the comparative example semiconductor system except for the resistance values of the resistive elements R1, R2, jitter showed 2.74 nsec/100 mV. That is, in the semiconductor system 3, compared to the case of the comparative example semiconductor system, jitter was suppressed to about 42%.

In recent years, in the automotive industry, IEC62132-4 (DPI method) has been attracting attention as an EMC test for ICs (Integrated Circuits) standardized by the IEC (International Electrotechnical Commission) standard. In this DPI method, even when noise of approximately ±600 mV is superimposed on the 3.3V power supply voltage VDD supplied to the local pin, based on a 50Ω conversion, it is required that the IC does not malfunction. A local pin refers to a pin that is not connected to the outside of the ECU but is connected to components including other ICs within the ECU.

Here, there is a proportional relationship between the noise superimposition amount of the power supply voltage VDD and jitter. Therefore, to examine whether the comparative example semiconductor system meets the requirements of the DPI method, when the amplitude of the external noise, that is, the noise superimposition amount of the power supply voltage VDD, was set to 3.3V±600 mV in the simulation conditions of FIG. 5, jitter showed 39.12 nsec/100 mV (=6.52×6 nsec/100 mV), and the EYE opening became narrow.

In contrast, to examine whether the semiconductor system 3 meets the requirements of the DPI method, when the amplitude of the external noise, that is, the noise superimposition amount of the power supply voltage VDD, was set to 3.3V±600 mV in the simulation conditions of FIG. 6, jitter showed 16.44 nsec/100 mV (=2.74×6 nsec/100 mV), and the EYE opening was maintained in a wide state. That is, the semiconductor system 3 can maintain the EYE opening in a wide state without using external components such as an external low-pass filter. In other words, the semiconductor system 3 can achieve low jitter.

The low jitter achieved by the semiconductor system 3 is explained more specifically. For example, when +100 mV of noise is superimposed on the power supply voltage VDD, the power supply voltage VDD2 also increases instantaneously by ΔVDD. At this time, the gate-source voltage of each of the transistors MP1, MN1 increases instantaneously, and current flows through the transistors MP1, MN1 and the resistive element R2, causing the reference voltage GND2 to also increase instantaneously by ΔGND. Thus, the potential difference between the power supply voltage VDD2 and the reference voltage GND2 is maintained almost constant even when noise occurs. That is, the semiconductor system 3 can achieve low jitter because it is less affected by noise.

Thus, the semiconductor system 3, having an oscillation circuit to which the configuration of the semiconductor device 1 is applied, can not only achieve low power consumption similar to the semiconductor device 1 but also maintain a wide EYE opening without using external components such as external low-pass filters, thereby realizing low jitter.

Fourth Embodiment

FIG. 7 is a diagram showing an example of the configuration of a semiconductor system 4 according to a fourth embodiment. The semiconductor system 4 includes a semiconductor device 1b instead of the semiconductor device 1a