>1-DL_m, two amplifiers 135_1 and 135_2, and a portion of a source multiplexing circuit 136.

According to the multiplexing driving method, the source driver 130 may supply the plurality of data signals to a plurality of first data lines (e.g., DL_1 and DL_2) among the plurality of data lines DL_1, DL_2, DL_3, and DL_4 during a first time period of one horizontal period and may supply a plurality of second data signals to a plurality of second data signals (e.g., DL_3 and DL_4) among the plurality of data lines DL_1, DL_2, DL_3, and DL_4 during a second time period of one horizontal period.

A plurality of red pixels R2 and R4 and a plurality of blue pixels B1 and B3 are alternately connected to the first data line DL_1 among the plurality of first data lines DL_1 and DL_2, and a plurality of blue pixels B2 and B4 and a plurality of red pixels R1 and R3 are alternately connected to the second data line DL_3 among the plurality of second data lines DL_3 and DL_4. A plurality of green pixels G11, G21, G31, and G41 are connected to the first data line DL_2 among the plurality of first data lines DL_1 and DL_2, and a plurality of green pixels G12, G22, G32, and G42 are connected to the second data line DL_4 among the plurality of second data lines DL_3 and DL_4. As described above, the red (R) pixel, the green (G) pixel, and the blue (B) pixel may be arranged in a pattern in which pixel columns with four data line units are repeated. A pattern of the pixels shown in FIG. 4 is merely an example, and example embodiments are not limited thereto.

A voltage charged in each of a plurality of parasitic capacitors CP_1 and CP_2 connected to each of the plurality of first data lines DL_1 and DL_2 may be written in the pixel. A parasitic capacitor is also formed in each of the plurality of second data lines DL_3 and DL_4, but, for the sake of discussion, the parasitic capacitor of each of the plurality of second data lines DL_3 and DL_4 is not considered to be involved in writing of the data signal in the pixel so that the parasitic capacitor of each of the plurality of second data lines is omitted in FIG. 4.

As shown in FIG. 4, the source driver 130 may include a driving control circuit 131, a shift register 132, a level shifter 133, a decoder 134, an output amplification circuit 135, and the source multiplexing circuit 136.

The driving control circuit 131 may generate a clock signal or control signals for controlling an operation of each component of the source driver 130 according to the source control signal CONS to provide the control signal corresponding to each component. For example, the driving control circuit 131 may be configured to generate and provide two multiplexing signals CLA and CLB that control a multiplexing operation of the source multiplexing circuit 136.

The shift register 132 may store the image data signal IMD by shifting the image data signal IMD in a unit of one pixel, and may provide a plurality of pixel-unit image data of one pixel row to the level shifter 34 according to a latch signal provided from the driving control circuit 131. The pixel-unit image data are referred to as pixel data.

The level shifter 133 may shift a digital signal level constituting each of a plurality of pixel data corresponding to one pixel row to provide the shifted level to the decoder 134. For example, an operating voltage range of the decoder 134 may be higher than an operating voltage range of the shift register 132. Therefore, the level shifter 133 may increase a digital signal level constituting each of a plurality of grayscale data to a digital signal level that may be processed by the decoder 134.

The decoder 134 may receive the plurality of pixel data from the level shifter 133, and may convert each of the plurality of pixel data that is a digital signal into each of the plurality of data signals that is an analog signal. The decoder 134 may generate a plurality of grayscale voltages corresponding to each of a plurality of grayscales using a plurality of gamma voltages and a plurality of resistor strings. The decoder 134 may generate each of the plurality of data signals by selecting one of the plurality of grayscale voltages according to each of the plurality of pixel data. The decoder 134 may be implemented as a digital-analog converter that converts the pixel data that is a digital signal into the data signal that is an analog signal.

The output amplification circuit 135 may include a plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may receive each of the plurality of data signals from the decoder 134 to output each of the plurality of data signals. Each of the plurality of amplifiers 135_1 and 135_2 may be implemented as an operational amplifier. An output of the operational amplifier may be connected (e.g., feedback) to a negative input terminal (−) thereof, a positive input terminal (+) of the operational amplifier may be connected to the decoder 134, and the data signal may be input to the positive input terminal (+).

The source multiplexing circuit 136 may include a plurality of switching elements 136_1, 136_2, 136_3, and 136_4 connected between the plurality of amplifiers 135_1 and 135_2 and the plurality of data lines DL_1-DL_4. The plurality of switching elements 136_1, 136_2, 136_3, and 136_4 may perform a switching operation according to one of the multiplexing signals CLA and CLB provided from the driving control circuit 131. For example, the plurality of switching elements 136_1 and 136_2 may perform a switching operation according to the multiplexing signal CLA, and the plurality of switching elements 136_3 and 136_4 may perform a switching operation according to the multiplexing signal CLB. The plurality of switching elements 136_1 and 136_2 may be turned on during a first time period in which the multiplexing signal CLA is at an ON level, and the plurality of switching elements 136_3 and 136_4 may be turned on during a second time period in which the multiplexing signal CLB is at an ON level.

One end of the switching element 136_1 may be connected to the data line DL_1, and the other end of the switching element 136_1 may be connected to an output end of the amplifier 135_1. One end of the switching element 136_2 may be connected to the data line DL_2, and the other end of the switching element 136_2 may be connected to an output end of the amplifier 135_2. One end of the switching element 136_3 may be connected to the data line DL_3, and the other end of the switching element 136_3 may be connected to an output end of the amplifier 135_1. One end of the switching element 136_4 may be connected to the data line DL_4, and the other end of the switching element 136_4 may be connected to an output end of the amplifier 135_2.

FIG. 5 is a timing diagram showing waveforms of the multiplexing signal and the gate signal, according to some example embodiments.

FIG. 5 shows a waveform of a gate clock signal GCK included in the gate control signal CONG. The gate driver (or a gate driving circuit) 140 may sequentially generate a plurality of gate signals VG1, VG2, VG3, and VG4 in a unit of one period of the gate clock signal GCK to provide the generated gate signals to the plurality of gate lines GL_1, GL_2, GL_3, and GL_4. As shown in FIG. 5, the plurality of gate signals VG1, VG2, VG3, and VG4 may sequentially have ON levels in a time period T1-T2, a time period T3-T4, a time period T5-T6, and a time period T7-T8. Although FIG. 5 shows that an ON level of each of the gate signals is a low level, the ON level of each of the gate signals may be changed according to a channel type of the switching transistor of the circuit of the pixel PX.

In a time period TP1, the multiplexing signal CLA may be at an ON level on so that the plurality of switching elements 136_1 and 136_2 are turned ON. Then, the plurality of amplifiers 135_1 and 135_2 may be connected to the plurality of data lines DL_1 and DL_2, respectively. In the time period TP1, the decoder 134 may supply each of a plurality of data signals VD_1 and VD_2 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of data lines DL_1 and DL_2. In example embodiments, the data signal VD_1 may be grayscale data to be written in a blue pixel B1 connected to the gate line GL_1 and the data line DL_1, and the data signal VD_2 may be grayscale data to be written in a green pixel G11 connected to the gate line GL_1 and the data line DL_2. Because the gate signal VG1 is at the OFF level in the time period TP1, the plurality of data signals VD_1 and VD_2 may be charged in the parasitic capacitors CP_1 and CP_2 of the plurality of data lines DL_1 and DL_2, respectively. If the gate signal VG1 is at the ON level in the time period T1-T2, the voltage charged in each of the parasitic capacitors CP_1 and CP_2 may be supplied to each of the blue pixel B1 and the green pixel G11. As shown in FIG. 5, the time period TP1 and the time period T1-T2 do not overlap.

In a time period TP2, the multiplexing signal CLB may be turned ON so that the plurality of switching elements 136_3 and 136_4 are turned ON. Then, the plurality of amplifiers 135_1 and 135_2 may be connected to the plurality of data lines DL_3 and DL_4, respectively. In the time period TP2, the decoder 134 may supply each of a plurality of data signals VD_3 and VD_4 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of data lines DL_3 and DL_4. In example embodiments, the data signal VD_3 may be grayscale data to be written in a red pixel R1 connected to the gate line GL_1 and the data line DL_3, and the data signal VD_4 may be grayscale data to be written in a green pixel G12 connected to the gate line GL_1 and the data line DL_4. Because the gate signal VG1 is at the ON level in the time period T1-T2 and the time period TP2 and the time period T1-T2 overlap, each of the plurality of data signals VD_3 and VD_4 may be supplied to each of the red pixel R1 and the green pixel G12 through each of the plurality of data lines DL_3 and DL_4.

The plurality of switching elements 136_1 and 136_2 may be turned ON by the multiplexing signal CLA with an ON level in a time period TP3, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_1 and DL_2. In the time period TP3, the decoder 134 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of data lines DL_1 and DL_2. In this case, the data signal VD_1 may be grayscale data to be written in a red pixel R2 connected to the gate line GL_2 and the data line DL_1, and the data signal VD_2 may be grayscale data to be written in a green pixel G21 connected to the gate line GL_2 and the data line DL_2. Because the gate signal VG2 is at an OFF level in the time period TP3, the plurality of data signals VD_1 and VD_2 may be charged in the parasitic capacitors CP_1 and CP_2 of the plurality of data lines DL_1 and DL_2, respectively. If the gate signal VG2 is at the ON level in the time period T3-T4, the voltage charged in each of the parasitic capacitors CP_1 and CP_2 may be supplied to each of the red pixel R2 and the green pixel G21.

The plurality of switching elements 136_3 and 136_4 may be turned ON by the multiplexing signal CLB with an ON level in a time period TP4, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_3 and DL_4. In the time period TP4, the decoder 134 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of data lines DL_3 and DL_4. In this case, the data signal VD_3 may be grayscale data to be written in a blue pixel B2 connected to the gate line GL_2 and the data line DL_3, and the data signal VD_4 may be grayscale data to be written in a green pixel G22 connected to the gate line GL_2 and the data line DL_4. Because the gate signal VG2 is at the ON level in the time period T3-T4 and the time period TP4 and the time period T3-T4 overlap, each of the plurality of data signals VD_3 and VD_4 may be supplied to each of the blue pixel B2 and the green pixel G22 through each of the plurality of data lines DL_3 and DL_4.

The plurality of switching elements 136_1 and 136_2 may be turned ON by the multiplexing signal CLA with an ON level in a time period TP5, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_1 and DL_2. In the time period TP5, the decoder 134 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of data lines DL_1 and DL_2. In this case, the data signal VD_1 may be grayscale data to be written in a blue pixel B3 connected to the gate line GL_3 and the data line DL_1, and the data signal VD_2 may be grayscale data to be written in a green pixel G31 connected to the gate line GL_3 and the data line DL_2. Because the gate signal VG3 is at an OFF level in the time period TP5, the plurality of data signals VD_1 and VD_2 may be charged in the parasitic capacitors CP_1 and CP_2 of the plurality of data lines DL_1 and DL_2, respectively. If the gate signal VG3 is at the ON level in the time period T5-T6, the voltage charged in each of the parasitic capacitors CP_1 and CP_2 may be supplied to each of the blue pixel B3 and the green pixel G31.

The plurality of switching elements 136_3 and 136_4 may be turned ON by the multiplexing signal CLB with an ON level in a time period TP6, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_3 and DL_4. In the time period TP6, the decoder 134 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of data lines DL_3 and DL_4. In this case, the data signal VD_3 may be grayscale data to be written in a red pixel R3 connected to the gate line GL_3 and the data line DL_3, and the data signal VD_4 may be grayscale data to be written in a green pixel G32 connected to the gate line GL_3 and the data line DL_4. Because the gate signal VG3 is at the ON level in the time period T5-T6 and the time period TP6 and the time period T5-T6 overlap, each of the plurality of data signals VD_3 and VD_4 may be supplied to each of the red pixel R3 and the green pixel G32 through each of the plurality of data lines DL_3 and DL_4.

The plurality of switching elements 136_1 and 136_2 may be turned ON by the multiplexing signal CLA with an ON level in a time period TP7, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_1 and DL_2. In the time period TP7, the decoder 134 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_1 and VD_2 to each of the plurality of data lines DL_1 and DL_2. In this case, the data signal VD_1 may be grayscale data to be written in a red pixel R4 connected to the gate line GL_4 and the data line DL_1, and the data signal VD_2 may be grayscale data to be written in a green pixel G41 connected to the gate line GL_4 and the data line DL_2. Because the gate signal VG4 is at an OFF level in the time period TP7, the plurality of data signals VD_1 and VD_2 may be charged in the parasitic capacitors CP_1 and CP_2 of the plurality of data lines DL_1 and DL_2, respectively. If the gate signal VG4 is at the ON level in a time period T7-T8, the voltage charged in each of the parasitic capacitors CP_1 and CP_2 may be supplied to each of the red pixel R4 and the green pixel G41.

The plurality of switching elements 136_3 and 136_4 may be turned ON by the multiplexing signal CLB with an ON level in a time period TP8, and each of the plurality of amplifiers 135_1 and 135_2 may be connected to each of the plurality of data lines DL_3 and DL_4. In the time period TP8, the decoder 134 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of amplifiers 135_1 and 135_2, and each of the plurality of amplifiers 135_1 and 135_2 may supply each of the plurality of data signals VD_3 and VD_4 to each of the plurality of data lines DL_3 and DL_4. In this case, the data signal VD_3 may be grayscale data to be written in a blue pixel B4 connected to the gate line GL_4 and the data line DL_3, and the data signal VD_4 may be grayscale data to be written in a green pixel G42 connected to the gate line GL_4 and the data line DL_4. Because the gate signal VG4 is at the ON level in the time period T7-T8 and the time period TP8 and the time period T7-T8 overlap, each of the plurality of data signals VD_3 and VD_4 may be supplied to each of the blue pixel B4 and the green pixel G42 through each of the plurality of data lines DL_3 and DL_4.

FIG. 6 is a block diagram of a configuration of the timing controller, according to some example embodiments. In FIG. 6, the timing controller 120 is configured to process the image signal IS to generate the image data signal IMD. The timing controller 120 may include a memory 121, a grayscale converter 122, a compensation circuit 123, and a source driver interface (SD INF) 124. The memory 121 may store information that may be utilized when operating the timing controller 120. For example, the memory 121 may store each of a plurality of compensation datasets in a form of a look-up table corresponding to each of a plurality of driving environments of the display device 12. The memory 121 may be implemented as a read only memory (ROM), a flash memory, or the like. The grayscale converter 122 may convert the image signal IS into grayscale data GSD in a unit of the pixel, and may generate a pixel address PAD corresponding to each grayscale data GSD to provide the pixel address PAD to the compensation circuit 123. The source driver interface (SD INF) 124 may latch final grayscale data FGD that is an output of the compensation circuit 123 to convert the latched data into image data IMD.

The compensation circuit 123 may include a compensation dataset generator 231, a compensator 232, a multiplexer (MUX) controller 233, and a multiplexer 234. The compensation circuit 123 may generate the compensation dataset according to the driving environment of the display device 12, may compensate the grayscale data GSD using the compensation dataset according to a position of the pixel so that it may generate compensation grayscale data CGD and outputs the final grayscale data FGD or may output the grayscale data GSD as the final grayscale data FGD without compensating the grayscale data GSD.

FIG. 7 is a flowchart of a method 700 of operation of the compensation circuit 123 of FIG. 6, according to some example embodiments. It is understood that additional operations can be provided before, during, and after the operations in FIG. 7, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable, or two or more operations can be performed simultaneously.

The compensation dataset generator 231 may detect a similar compensation dataset corresponding to the driving environment (hereinafter referred to as a display driving environment) of the display device 12 among the plurality of compensation datasets in the memory 121 (S1). Each of the plurality of compensation datasets may include grayscale compensation values for each color and grayscale for compensating for an artifact that occurs when the display device displays a screen according to the multiplexing driving method in the driving environment. For example, when a gray scale to be displayed by the plurality of pixels connected to the data line DL_1 is the same as a gray scale to be displayed by the plurality of pixels connected to the data line DL_3, a voltage charged in the parasitic capacitor CP_1 may be written in each pixel of the data line DL_1, and a voltage supplied by the amplifier 135_1 may be written in each pixel of the data line DL_3. A deviation in a charge rate of the pixel may occur between writing of a voltage through the parasitic capacitor and writing of a voltage by the amplifier. The pixel charge rate may be determined according to a voltage stored in the capacitor C1 or the capacitor Cs that is a storage element in FIG. 3. For example, because a luminance provided by the pixels of the data line DL_3 is higher (or lower) than a luminance provided by the pixels of the data line DL_1, a vertical line due to a luminance difference between the two data lines DL_1 and DL_3 may be recognized. In general, if colors (e.g., red or blue) constituting a color pattern of the plurality of pixels connected to each of the two data lines DL_1 and DL_3 are the same, the vertical line may become more visible. Similarly, because a luminance provided by the pixels of the data line DL_4 is higher (or lower) than a luminance provided by the pixels of the data line DL_2, a vertical line due to a luminance difference between the two data lines DL_2 and DL_4 may be recognized. Similarly, if colors (e.g., green) constituting a color pattern of the plurality of pixels connected to each of the two data lines DL_2 and DL_4 are the same, the vertical line may become more visible.

To solve this, the display device 12, according to example embodiments, may compensate for grayscale data of the pixels of the data line DL_1 to compensate for the luminance difference when it generates the data signal supplying to the pixels of the data line DL_1. In the display device 12, a grayscale compensation value for the input grayscale for each color and grayscale of the pixel may be obtained by an experimental method. Each of the plurality of compensation datasets may be implemented as a look-up table in which the grayscale compensation values obtained in the driving environment are disposed for each color and each grayscale.

Table 1 is an example look-up table showing a compensation dataset including grayscale compensation values corresponding to a certain driving environment. In Table 1, each of input grayscales (g_1, g_2, g_3, g_4, g_5, . . . , g_k−1, and g_k) may be a grayscale indicated by the grayscale data, and may indicate a predetermined number of grayscales within an entire grayscale range that the grayscale data may have. In Table 1, each of (rg1, rg2, rg3, rg4, rg5, . . . , rgk−1, rgk), (gg1, gg2, gg3, gg4, gg5, . . . , ggk−1, ggk), and (bg1, bg2, bg3, bg4, bg5, . . . , bgk−1, bgk) may be grayscale compensation values for each color, and each grayscale compensation value may indicate the grayscale compensation value corresponding to the color in the input grayscale. K may be a natural number of 2 or more.

TABLE 1

Input grayscale
g_1
g_2
g_3
g_4
g_5
. . .
g_k − 1
g_k

Grayscale
Red
rg1
rg2
rg3
rg4
rg5
. . .
rgk − 1
rgk

compensation
(R)

value
Green
gg1
gg2
gg3
gg4
gg5
. . .
ggk − 1
ggk

(G)

Blue
bg1
bg2
bg3
bg4
bg5
. . .
bgk − 1
bgk

(B)

The display processor 110 may collect information on driving environment factors from related configurations. For example, the display processor 110 may receive temperature information from a temperature sensor provided in the display device 12 or the electronic device 1, may read a setting value indicating an operating frequency of the display device 12, and may receive brightness information from a brightness control interface of the electronic device 1. The display processor 110 may transmit the driving environment factors to the compensation dataset generator 231.

The compensation dataset generator 231 may detect two compensation datasets (hereinafter, similar compensation datasets) corresponding to two driving environments similar to the display driving environment among the plurality of compensation datasets. It may be challenging to find a compensation dataset corresponding to substantially the same driving environment as the display driving environment among the plurality of compensation datasets. To solve this, the compensation dataset generator 231 may select two driving environments similar to the display driving environment among the plurality of driving environments, and may read two similar compensation datasets corresponding to the selected two driving environments from the memory 121.

The compensation dataset generator 231 may generate the compensation dataset by interpolating two similar compensation datasets (S2). Hereinafter, the compensation dataset generated by the compensation dataset generator 231 may be referred to as an interpolation compensation dataset. The compensation dataset generator 231 may provide the interpolation compensation dataset to the compensator 232. The compensation dataset generator 231 may generate the compensation dataset by applying interpolation methods such as linear interpolation, Lagrange polynomial interpolation, or the like, to compensation values for each color and each grayscale data in each of the two similar compensation datasets.

If the compensation dataset generator 231 performs the operations S1 and S2 to generate the compensation dataset, it may be understood that a setting operation required for the compensator 232 to compensate for the grayscale data has been completed. The compensator 232 may generate the final grayscale data FGD by compensating for the grayscale data GSD representing the input grayscale using the input grayscale, the pixel address, and the compensation dataset. Hereinafter, for convenience of description, the grayscale data GSD are referred to as “original grayscale data”, and the compensated grayscale data are referred to as “compensation grayscale data.”

The original grayscale data GSD corresponds to the input grayscale input to the compensator 232. The compensator 232 may detect grayscale compensation values corresponding to two input grayscale values adjacent to the original grayscale data GSD in the compensation dataset, and may generate a grayscale compensation value by interpolating the detected two grayscale compensation values (S3). For example, the compensator 232 may detect the grayscale compensation value (rgi) of the input grayscale (g_i) that is less than the original grayscale data GSD and is adjacent to the original grayscale data GSD among a plurality of input grayscales for the same color (e.g., red) as a color corresponding to the original grayscale data GSD and the grayscale compensation value (rgi+1) of the input grayscale (g_i+1) that is greater than the original grayscale data GSD and is adjacent to the original grayscale data GSD in the compensation dataset. The compensator 232 may generate a grayscale compensation value (GCV) corresponding to the original grayscale data GSD by interpolating the grayscale compensation value (rg_i) and the grayscale compensation value (rgi+1).

The compensator 232 may generate the compensation grayscale data CGD by adding the grayscale compensation value (GCV) to the original grayscale data GSD (S4).

The MUX controller 233 may determine a data line (hereinafter referred to as a pixel data line) to which the pixel is connected according to the pixel address PAD, and may determine whether the pixel data line is a compensation data line (S5). If the pixel data line is the compensation data line, the MUX controller 233 may generate a control output MCS that is “1” to provide the control output to the multiplexer 234. If the pixel data line is not the compensation data line, the MUX controller 233 may generate the control output MCS that is “0” to provide the control output MCS to the multiplexer 234.

If the pixel data line is the compensation data line, the multiplexer 234 may output the compensation grayscale data CGD as the final grayscale data FGD according to the control output MCS that is “1” of the MUX controller 233 (S6).

If the pixel data line is not the compensation data line, the multiplexer 234 may output the original grayscale data GSD as the final grayscale data FGD according to the control output MCS that is “0” of the MUX controller 233 (S7).

The final grayscale data FGD output by the multiplexer 234 may be provided to the source driver interface (SD INF). The source driver interface (SD INF) may latch a plurality of final grayscale data FGD in a unit of the pixel row to convert the latched data into the image data IMD, and may transmit the converted data to the source driver 130. However, example embodiments are not limited thereto. According to some example embodiments, if an operation in which the compensation circuit 123 generates the final grayscale data FGD and an operation in which the source driver 130 processes the pixel-unit image data are synchronized with each other, the final grayscale data FGD may be directly transmitted to the source driver 130 as the image data IMD.

FIG. 8 is a flowchart of a method 800 of operation of the compensation circuit 123, according to some example embodiments. It is understood that additional operations can be provided before, during, and after the operations in FIG. 8, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable, or two or more operations can be performed simultaneously. The method 800 may be similar in some respects to the method 700 of FIG. 7, and therefore may be best understood with reference thereto where like numerals indicate like elements not described again in detail.

The operations S1 and S2 of the method 800 in FIG. 8 are similar to the operations S1 and S2 of the method 700 in FIG. 7.

The MUX controller 233 may determine the pixel data line according to the pixel address PAD, and may determine whether the pixel data line is the compensation data line (S10).

If the pixel data line is not the compensation data line as a result of the determination in the operation S10, the MUX controller 233 may provide the control output MCS that is “0” to the multiplexer 234, and the multiplexer 234 may control the original grayscale data GSD to be output as the final grayscale data FGD (S11). In this case, the original grayscale data GSD may bypass the compensator 232 and is output from the multiplexer 234 without a compensation operation being performed on it by the compensator 232. The control output MCS that is “0” of the MUX controller 233 may be provided to the compensator 232, and the compensator 232 may not operate based on the control output MCS that is “0”.

If the pixel data line is the compensation data line as a result of the determination in the operation S10, the compensator 232 may detect grayscale compensation values corresponding to two grayscale data adjacent to the original grayscale data GSD in the compensation data set and may generate the grayscale compensation value (GCV) by interpolating the detected two grayscale compensation values (S12). In this case, the MUX controller 233 may generate the control output MCS that is “1” to provide the control output MCS to the compensator 232, and, in response to the control output that is “1”, the compensator 232 may generate the compensation grayscale data CGD by adding the grayscale compensation value (GCV) to the original grayscale data GSD (S13).

In operation S14, the multiplexer 234 may output the compensation grayscale data CGD as the final grayscale data FGD according to the control output MCS that is “1” of the MUX controller 233.

The compensator 232 may consider a position of the pixel in determining the grayscale compensation value (GCV).

FIG. 9 is a flowchart of a method 900 of operation of the compensation circuit, according to some example embodiments. It is understood that additional operations can be provided before, during, and after the operations in FIG. 9, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable, or two or more operations can be performed simultaneously. The method 900 may be similar in some respects to the method 700 of FIG. 7, and therefore may be best understood with reference thereto where like numerals indicate like elements not described again in detail.

In the flowchart shown in FIG. 9, operations S1-S7 are similar to the operations S1-S7 shown in FIG. 7. However, a new operation S8 may be performed between the operations S3 and S4.

In operation S8, the compensator 232 may determine a gain for the grayscale compensation value (GCV) according to the pixel address PAD, and may multiply the grayscale compensation value (GCV) by the determined gain to determine a grayscale compensation value (GCF). The gain for the grayscale compensation value (GCV) may be a ratio that applies the grayscale compensation value (GCV), and the gain that determines a degree of compensation may vary depending on a position of the pixel. For example, as the position of the pixel in the display panel 150 is closer to a center thereof, the gain may increase.

FIG. 10 is a flowchart of a method 1000 of operation of the compensation circuit, according to example embodiments. It is understood that additional operations can be provided before, during, and after the operations in FIG. 10, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable, or two or more operations can be performed simultaneously. The method 1000 may be similar in some respects to the method 800 of FIG. 8, and therefore may be best understood with reference thereto where like numerals indicate like elements not described again in detail.

In the flowchart shown in FIG. 10, operationsS10-S14 are similar to the operationsS10-S14 shown in FIG. 8. However, a new operation S15 may be performed between the operationsS12 and S13.

In operation S15, the compensator 232 may determine a gain for the grayscale compensation value (GCV) according to the pixel address PAD, and may multiply the grayscale compensation value (GCV) by the determined gain to determine a grayscale compensation value (GCF).

FIGS. 11(a), 11(b), and 11(c) illustrate methods for generating the final grayscale data according to some example embodiments of FIG. 7 and/or FIG. 9. The discussion below of FIGS. 11(a), 11(b), and 11(c) may be understood with reference to FIGS. 4 and 5.

FIG. 11(a) illustrates original grayscale data corresponding to four data lines DL_1-DL_4 and four gate lines GL1-GL4. Referring to FIG. 11(a), the original grayscale data are shown to indicate a “128” grayscale for convenience of description.

FIG. 11(b) illustrates grayscale compensation values (GCV) according to a color and a grayscale in the driving environment of the display device 12. In FIG. 11(b), the grayscale compensation value (GCV) for the red pixel indicates a “2” grayscale, the grayscale compensation value (GCV) for the blue pixel indicates a “1” grayscale, and the grayscale compensation value (GCV) for the green pixel indicates a “5” grayscale.

Because two data lines DL_1 and DL_2 are compensation data lines and two data lines DL_3 and DL_4 are not compensation data lines, as shown in FIG. 11(c), the final grayscale data are generated by adding the grayscale compensation values (GCV) to the original grayscale data for the two data lines DL_1 and DL_2, and the original grayscale data for the two data lines DL_3 and DL_4 are generated as the final grayscale data.

FIGS. 12(a), 12(b), and 12(c) illustrate methods for generating the final grayscale data according to some example embodiments of FIG. 8 and/or FIG. 10. The discussion below of FIGS. 12(a), 12(b), and 12(c) may be understood with reference to FIGS. 4 and 5.

FIG. 12(a) illustrates original grayscale data corresponding to four data lines DL_1-DL_4 and four gate lines GL1-GL4. In FIG. 12(a), the original grayscale data are shown to indicate a “128” grayscale for convenience of description.

FIG. 12(b) illustrates grayscale compensation values (GCV) according to a color and a grayscale in the driving environment of the display device 12. Because two data lines DL_1 and DL_2 are compensation data lines and two data lines DL_3 and DL_4 are not compensation data lines, in FIG. 12(b), the grayscale compensation value (GCV) for the red pixel of each of the two data lines DL_1 and DL_2 indicates a “2” grayscale, the grayscale compensation value (GCV) for the blue pixel thereof indicates a “1” grayscale, and the grayscale compensation value (GCV) for the green pixel thereof indicates a “5” grayscale. The grayscale compensation value (GCV) is not generated for the two data lines DL_3 and DL_4.

As shown in FIG. 12(c), the final grayscale data are generated by adding the grayscale compensation values (GCV) to the original grayscale data for the two data lines DL_1 and DL_2, and the original grayscale data for the two data lines DL_3 and DL_4 are generated as the final grayscale data.

A connection relationship between the source multiplexing circuit 136 of the source driver 130 and the plurality of data lines DL_1-DL_m according to some example embodiments may be different from the structure shown in FIG. 4. An artifact pattern such as a vertical line that occurs may vary depending on a method in which the plurality of amplifiers (135_1, 135_2, . . . ) are connected to the plurality of data lines DL_1-DL_m through the source multiplexing circuit 136.

FIG. 13 illustrates another configuration of the source driver and the display panel, according to some example embodiments. The configuration in FIG. 13 may be similar in some respects to the configuration in FIG. 4, and therefore may be best understood with reference thereto where like numerals indicate like elements not described again in detail. For the sake of clarity of illustration, the driving control circuit 131, the shift register 132, the level shifter 133, and the decoder 134 shown in FIG. 4 are omitted in FIG. 13.

FIG. 13 illustrates eight data lines DL_1, DL_2, DL_3, DL_4, DL_5, DL_6, DL_7, and DL_8, four amplifiers 135_1, 135_2, 135_3, and 135_4, and a portion of the source multiplexing circuit 136.

According to the multiplexing driving method, the source driver 130 may supply the plurality of data signals to a plurality of first data lines (e.g., DL_1, DL_2, DL_3, and DL_4) among the plurality of data lines DL_1, DL_2, DL_3, DL_4, DL_5, DL_6, DL_7, and DL_8 during a first time period of one horizontal period and may supply a plurality of second data signals to a plurality of second data signals (e.g., DL_5, DL_6, DL_7, and DL_8) among the plurality of data lines DL_1, DL_2, DL_3, DL_4, DL_5, DL_6, DL_7, and DL_8 during a second time period of one horizontal period. As shown in FIG. 13, a voltage charged in each of a plurality of parasitic capacitors CP_1, CP_2, CP_3, and CP_4 connected to each of the plurality of first data lines DL_1, DL_2, DL_3, and DL_4 may be written in the pixel corresponding to the voltage charged in each of the plurality of parasitic capacitors. A parasitic capacitor is also formed in each of the plurality of second data lines DL_5, DL_6, DL_7, and DL_8, but, for the sake of discussion, the parasitic capacitor of each of the plurality of second data lines DL_5, DL_6, DL_7, and DL_8 is not considered to be involved in writing of the data signal in the pixel and so the parasitic capacitor of each of the plurality of second data lines is omitted in FIG. 13.

A plurality of red pixels R21 and R41 and a plurality of blue pixels B11 and B31 are alternately connected to the first data line DL_1 among the plurality of first data lines DL_1, DL_2, DL_3, and DL_4, and a plurality of blue pixels B12 and B32 and a plurality of red pixels R22 and R42 are alternately connected to the second data line DL_5 among the plurality of second data lines DL_5, DL_6, DL_7, and DL_8. A plurality of green pixels G11, G21, G31, and G41 are connected to the first data line DL_2 among the plurality of first data lines DL_1, DL_2, DL_3, and DL_4, and a plurality of green pixels G13, G23, G33, and G43 are connected to the second data line DL_6 among the plurality of second data lines DL_5, DL_6, DL_7, and DL_8. A plurality of red pixels R11 and R31 and a plurality of blue pixels B21 and B41 are alternately connected to the first data line DL_3 among the plurality of first data lines DL_1, DL_2, DL_3, and DL_4, and a plurality of blue pixels B22 and B42 and a plurality of red pixels R12 and R32 are alternately connected to the second data line DL_7 among the plurality of second data lines DL_5, DL_6, DL_7, and DL_8. The plurality of green pixels G12, G22, G32, and G42 are connected to the first data line DL_4 among the plurality of first data lines DL_1, DL_2, DL_3, and DL_4, and a plurality of green pixels G14, G24, G34, and G44 are connected to the second data line DL_8 among the plurality of second data lines DL_5, DL_6, DL_7, and DL_8. As described above, the red (R) pixel, the green (G) pixel, and the blue (B) pixel may be arranged in a pattern in which pixel columns with eight data line units are repeated. As is understood, the pattern of the pixels shown in FIG. 13 is merely example, and example embodiments are not limited thereto.

Each of the plurality of amplifiers 135_1, 135_2, 135_3, and 135_4 may receive each of the plurality of data signals from the decoder 134 (FIG. 3), and may output each of the plurality of data signals. In some example embodiments, each of the plurality of amplifiers 135_1, 135_2, 135_3, and 135_4 may be implemented as an operational amplifier. An output end of the operational amplifier may be connected to a negative input terminal (−) thereof, a positive input terminal (+) of the operational amplifier may be connected to the decoder 134, and the data signal may be input to the positive input terminal (+).

The source multiplexing circuit 136 may include a plurality of switching elements 136_1, 136_2, 136_3, 136_4, 136_5, 136_6, 136_7, and 136_8 connected between the plurality of amplifiers 135_1-135_4 and the plurality of data lines DL_1-DL_8. The plurality of switching elements 136_1, 136_2, 136_3, 136_4, 136_5, 136_6, 136_7, and 136_8 may perform a switching operation according to one of the multiplexing signals CLA and CLB received from the driving control circuit