130 and the emission driver 160 may be disposed on sides of the display panel 110. For example, the gate driver 130 and the emission driver 160 may be integral with each other.

FIG. 2 is a schematic block diagram illustrating an emission driver 160 included in a display device 10 of FIG. 1.

Referring to FIGS. 1 and 2, in an embodiment, the emission driver 160 may include emission stages EM_STAGE1, EM_STAGE2, EM_STAGE3, EM_STAGE4, . . . which receive an emission start signal EM_FLM, a first clock signal EM_CLK1, and a second clock signal EM_CLK2, and output emission signals EM[1], EM[2], EM[3], EM[4], . . . and emission carry signals EM_CR[1], EM_CR[2], EM_CR[3], EM_CR[4], . . . . A first emission stage EM_STAGE1 may receive the emission start signal EM_FLM as an input signal. Subsequent emission stages EM_STAGE2, EM_STAGE3, EM_STAGE4, . . . may receive the emission carry signals EM_CR[1], EM_CR[2], EM_CR[3], EM_CR[4], . . . of each of the previous emission stages as the input signal.

The emission stages EM_STAGE1, EM_STAGE2, EM_STAGE3, EM_STAGE4, . . . may include odd-numbered emission stages EM_STAGE1, EM_STAGE3, . . . , and even-numbered emission stages EM_STAGE2, EM_STAGE4, . . . . The odd-numbered emission stages EM_STAGE1, EM_STAGE3, . . . may receive the input signals based on the first clock signal EM_CLK1, and may output emission signals EM[1], EM[3], . . . and emission carry signals EM_CR[1], EM_CR[3], . . . based on the second clock signal EM_CLK2. The even-numbered emission stages EM_STAGE2, EM_STAGE4, . . . may receive the input signals based on the second clock signal EM_CLK2, and may output emission signals EM[2], EM[4], . . . and emission carry signals EM_CR[2], EM_CR[4], . . . based on the first clock signal EM_CLK1.

For example, as shown in FIG. 2, the emission stages EM_STAGE1, EM_STAGE2, EM_STAGE3, EM_STAGE4, . . . may sequentially output the emission carry signals EM_CR[1], EM_CR[2], EM_CR[3], EM_CR[4], . . . and the emission signals EM[1], EM[2], EM[3], EM[4], . . . in a frame period. The first emission stage EM_STAGE1 may output a first emission carry signal CR[1] and a first emission signal EM[1] based on the emission start signal EM_FLM. The second emission stage EM_STAGE2 may output a second emission carry signal EM_CR[2] and a second emission signal EM[2] based on the first emission carry signal EM_CR[1]. The third emission stage EM_STAGE3 may output a third emission carry signal EM_CR[3] and a third emission signal EM[3] based on the second emission carry signal EM_CR[2]. The fourth emission stage EM_STAGE4 may output a fourth emission carry signal EM_CR[4] and a fourth emission signal EM[4] based on the third emission carry signal EM_CR[3].

FIG. 3 is a schematic diagram of an equivalent circuit illustrating an emission stage 200 included in an emission driver 160.

Referring to FIGS. 1 to 3, the emission driver 160 may include emission stages 200. The emission stage 200 may include an input circuit 210, an inversion control circuit 220, a control circuit 230, an emission output circuit 240, a carry output circuit 250, and/or a boosting circuit 260.

The input circuit 210 may provide an input signal EM_FLM/EM_PCR to control nodes NQ1 and NQ2. The input signal EM_FLM/EM_PCR may be an emission start signal EM_FLM or a previous emission carry signal EM_PCR. A gate start signal GS_FLM may be a signal for starting an operation of a first emission stage of the emission stages 200. The previous emission carry signal EM_PCR may be an emission carry signal output from any one of previous emission stages. In an embodiment, the input circuit 210 may include first transistors T1_1 and T1_2.

The first transistors T1_1 and T1_2 may include a gate electrode configured to receive a first clock signal EM_CLK1, a first electrode configured to receive the input signal EM_FLM/EM_PCR, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The first transistors T1_1 and T1_2 may provide the input signal EM_FLM/EM_PCR to the control nodes NQ1 and NQ2 based on the first clock signal EM_CLK1. In an embodiment, the first transistors T1_1 and T1_2 may include a first-1 transistor T1_1 and a first-2 transistor T1_2 which are connected in series and have gate electrodes connected to each other.

The inversion control circuit 220 may control a voltage of an inversion control node NQB based on a voltage of the control nodes NQ1 and NQ2. In an embodiment, the inversion control circuit 220 may include a fourth transistor T4.

The fourth transistor T4 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive a second low gate voltage VGL2_EM, and a second electrode connected to the inversion control node NQB. The fourth transistor T4 may provide the second low gate voltage VGL2_EM to the inversion control node NQB based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the fourth transistor T4 may further include a back gate electrode configured to receive the second low gate voltage VGL2_EM.

In an embodiment, the inversion control circuit 220 may further include a seventh transistor T7, eighth transistors T8_1 and T8_2, a ninth transistor T9, a tenth transistor T10, an 11th transistor T11, and a third capacitor C3. The seventh transistor T7, the eighth transistors T8_1 and T8_2, the ninth transistor T9, the tenth transistor T10, the 11th transistor T11, and the third capacitor C3 may provide a high gate voltage VGH_EM to the inversion control node NQB based on the voltage of the control nodes NQ1 and NQ2.

The seventh transistor T7 may include a gate electrode configured to receive the first clock signal EM_CLK1, a first electrode configured to receive the high gate voltage VGH_EM, and a second electrode. The seventh transistor T7 may provide the high gate voltage VGH_EM based on the first clock signal EM_CLK1. In an embodiment, the seventh transistor T7 may further include a back gate electrode configured to receive the first clock signal EM_CLK1.

The eighth transistors T8_1 and T8_2 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive the first clock signal EM_CLK1, and a second electrode connected to the second electrode of the seventh transistor T7. The eighth transistors T8_1 and T8_2 may provide the first clock signal EM_CLK1 based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the eighth transistors T8_1 and T8_2 may include an eighth-1 transistor T8_1 and an eighth-2 transistor T8_2 which are connected in series and have gate electrodes connected to each other.

The ninth transistor T9 may include a gate electrode configured to receive the high gate voltage VGH_EM, a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode. The ninth transistor T9 may prevent or reduce the boosted voltage of the first electrode of the third capacitor C3 from being provided to the seventh transistor T7 and the eighth transistors T8_1 and T8_2. Accordingly, the stresses of the seventh transistor T7 and the eighth transistors T8_1 and T8_2 may be alleviated.

The tenth transistor T10 may include a gate electrode connected to the second electrode of the ninth transistor T9, a first electrode configured to receive the second clock signal EM_CLK2, and a second electrode. The tenth transistor T10 may provide the second clock signal EM_CLK2 based on a voltage of the first electrode of the third capacitor C3.

The 11th transistor T11 may include a gate electrode connected to the second electrode of the tenth transistor T10, a first electrode configured to receive the high gate voltage VGH_EM, and a second electrode connected to the inversion control node NQB. The 11th transistor T11 may provide the high gate voltage VGH_EM to the inversion control node NQB based on a voltage of the second electrode of the third capacitor C3. In an embodiment, the 11th transistor T11 may further include a back gate electrode connected to the second electrode of the tenth transistor T10.

The third capacitor C3 may boost a voltage of the gate electrode of the tenth transistor T10 and a voltage of the gate electrode of the 11th transistor T11. As the voltage of the gate electrode of the tenth transistor T10 is boosted by the third capacitor C3, the tenth transistor T10 may smoothly provide a second clock signal EM_CLK2 having a high-level voltage. As the voltage of the gate electrode of the 11th transistor T11 is boosted by the third capacitor C3, the 11th transistor T11 may smoothly provide the high gate voltage EM_VGH to the inversion control node NQB.

The control circuit 230 may control a voltage of control nodes NQ1 and NQ2 based on the voltage of the inversion control node NQB. In an embodiment, the control circuit 230 may include second transistors T2_1 and T2_2.

The second transistors T2_1 and T2_2 may include a gate electrode connected to the inversion control node NQB, a first electrode configured to receive a second low gate voltage VGL2_EM, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The second transistors T2_1 and T2_2 may provide the second low gate voltage VGL2_EM to the control nodes NQ1 and NQ2 based on the voltage of the inversion control node NQB. In an embodiment, the second transistors T2_1 and T2_2 may include a second-1 transistor T2_1 and a second-2 transistor T2_2 which are connected in series and have gate electrodes connected to each other. In an embodiment, the second transistors T2_1 and T2_2 may further include a back gate electrode connected to the inversion control node NQB.

The emission output circuit 240 may output the high gate voltage VGH_EM as an emission signal EM based on the voltage of the control nodes NQ1 and NQ2, and may output a first low gate voltage VGL_EM as the emission signal EM based on the voltage of the inversion control node NQB. In an embodiment, the emission output circuit 240 may include a 12th transistor T12, a 14th transistor T14, a fourth capacitor C4, and a fifth capacitor C5.

The 12th transistor T12 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive the high gate voltage VGH_EM, and a second electrode connected to an emission output node NEM at which the emission signal EM is output. The 12th transistor T12 may provide the high gate voltage VGH_EM to the emission output node NEM based on a voltage of the control nodes NQ1 and NQ2. In an embodiment, the 12th transistor T12 may further include a back gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2).

The 14th transistor T14 may include a gate electrode connected to the inversion control node NQB, a first electrode configured to receive the first low gate voltage VGL_EM, and a second electrode connected to the emission output node NEM. The 14th transistor T14 may provide the first low gate voltage VGL_EM to the emission output node NEM based on the voltage of the inversion control node NQB. In an embodiment, the 14th transistor T14 may further include a back gate electrode connected to the inversion control node NQB.

The fourth capacitor C4 may include a first electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2) and a second electrode connected to the emission output node NEM. The fourth capacitor C4 may reduce a distorted waveform of the emission signal EM.

The fifth capacitor C5 may include a first electrode connected to the inversion control node NQB and a second electrode configured to receive the first low gate voltage VGL_EM. The fifth capacitor C5 may stabilize the voltage of the inversion control node NQB.

The carry output circuit 250 may output the high gate voltage VGH_EM as an emission carry signal EM_CR based on the voltage of the control nodes NQ1 and NQ2, and may output the second low gate voltage VGL2_EM as the emission carry signal EM_CR based on the voltage of the inversion control node NQB. In an embodiment, the carry output circuit 250 may include a sixth transistor T6 and a 13th transistor T13.

The sixth transistor T6 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive the high gate voltage VGH_EM, and a second electrode connected to a carry output node NCR at which the emission carry signal EM_CR is output. The sixth transistor T6 may provide the high gate voltage VGH_EM to the carry output node NCR based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the sixth transistor T6 may further include a back gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2).

The 13th transistor T13 may include a gate electrode connected to the inversion control node NQB, a first electrode configured to receive the second low gate voltage VGL2_EM, and a second electrode connected to the carry output node NCR. The 13th transistor T13 may provide the second low gate voltage VGL2_EM to the carry output node NCR based on the voltage of the inversion control node NQB. In an embodiment, the 13th transistor T13 may further include a back gate electrode connected to the inversion control node NQB.

The boosting circuit 260 may boost the voltage of control nodes NQ1 and NQ2. The boosting circuit 260 may include a fifth transistor T5 and a first capacitor C1.

The fifth transistor T5 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive a next emission carry signal EM_NCR, and a second electrode connected to a boosting node NB. The next emission carry signal EM_NCR may be an emission carry signal output from any one of next emission stages.

The first capacitor C1 may include a first electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2) and a second electrode connected to the boosting node NB. The first capacitor C1 may boost the voltage of control nodes NQ1 and NQ2. As the voltage of the control nodes NQ1 and NQ2 (for example, the voltage of the gate electrode of the 12th transistor T12) is boosted by the first capacitor C1, the 12th transistor T12 may smoothly provide the high gate voltage VGH_EM to the emission output node NEM. As the voltage of the control nodes NQ1 and NQ2 (for example, the voltage of the gate electrode of the sixth transistor T6) is boosted by the first capacitor C1, the sixth transistor T6 may smoothly provide the high gate voltage VGH_EM to the carry output node NCR.

In an embodiment, the emission stage 200 may further include 16th transistors T16_1 and T16_2. The 16th transistors T16_1 and T16_2 may include a gate electrode configured to receive a reset signal ESR, a first electrode configured to receive the first low gate voltage VGL_EM, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The 16th transistors T16_1 and T16_2 may provide the first low gate voltage VGL_EM to the control nodes NQ1 and NQ2 based on the reset signal ESR. In an embodiment, the 16th transistors T16_1 and T16_2 may include a 16th-1 transistor T16_1 and a 16th-2 transistor T16_2 which are connected in series and have gate electrodes connected to each other.

In an embodiment, the reset signal ESR may be substantially simultaneously applied to the emission stages 200 when the display device 10 including the emission driver 160 is powered on. The 16th transistors T16_1 and T16_2 may substantially simultaneously reset the control nodes NQ1 and NQ2 with the first low gate voltage VGL_EM based on the reset signal ESR.

In an embodiment, the emission stage 200 may further include 15th transistors T15_1 and T15 2. The 15th transistors T15_1 and T15_2 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive the high gate voltage VGH_EM, and a second electrode connected to an intermediate node of the first transistors T1_1 and T1_2, an intermediate node of the second transistors T2_1 and T2_2, and an intermediate node of the 16th transistors T16_1 and T16_2. The 15th transistors T15_1 and T15_2 may provide the high gate voltage VGH_EM to the intermediate node of the first transistors T1_1 and T1_2, the intermediate node of the second transistors T2_1 and T2_2, and the intermediate node of the 16th transistor T16_1 and T16_2 based on the voltage of the control nodes NQ1 and NQ2. Although the voltage of the control nodes NQ1 and NQ2 is boosted as above, the 15th transistors T15_1 and T15_2 may apply the high gate voltage VGH_EM to the intermediate node of the first transistors T1_1 and T1_2, the intermediate node of the second transistors T2_1 and T2_2, and the intermediate node of the 16th transistors T16_1 and T16_2, and thus the first transistors T1_1 and T1_2, the second transistors T2_1 and T2_2, and the 16th transistors T16_1 and T16_2 may be prevented from being degraded. In an embodiment, the 15th transistors T15_1 and T15_2 may include a 15th-1 transistor T15_1 and a 15th-2 transistor T15_2 which are connected in series and have gate electrodes connected to each other.

In an embodiment, the control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2, and the emission stage 200 may further include a third transistor T3.

The third transistor T3 may include a gate electrode configured to receive the high gate voltage VGH_EM, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. The third transistor T3 may prevent or reduce the boosted voltage of the second control node NQ2 from being provided to the first control node NQ1. Accordingly, the stresses of the first transistors T1_1 and T1_2, the second transistors T2_1 and T2_2, the fourth transistor T4, the 15th transistors T15_1 and T15_2, and the 16th transistors T16_1 and T16_2, which are connected to the first control node NQ1, may be alleviated.

In an embodiment, all of the transistors T1_1, T1_2, T2_1, T2_2, T3, T4, T5, T6, T7, T8_1, T8_2, T9, T10, T11, T12, T13, T14, T15_1, T15_2, T16_1, and T16_2 included in the emission stage 200 may be N-type transistors (e.g., NMOS transistors) or oxide transistors.

FIG. 4 is a schematic timing diagram illustrating an operation of an emission stage 200 of FIG. 3.

Referring to FIGS. 1 to 4, the emission stage 200 may receive the input signal EM_FLM/EM_PCR, the high gate voltage VGH_EM, the first low gate voltage VGL_EM, the second low gate voltage VGL2_EM, the first clock signal EM_CLK1, and the second clock signal EM_CLK2. The high gate voltage VGH_EM may be larger than the first low gate voltage VGL_EM, and the second low gate voltage VGL2_EM may be smaller than the first low gate voltage VGL_EM. In an embodiment, the high gate voltage VGH_EM may be about 16 V, the first low gate voltage VGL_EM may be about-3 V, and the second low gate voltage VGL2_EM may be about-6 V.

The first clock signal EM_CLK1 and the second clock signal EM_CLK2 may have different phases (e.g., opposite phases). Each of the first clock signal EM_CLK1 and the second clock signal EM_CLK2 may have an alternating high-level voltage H and low-level voltage L. In an embodiment, the high-level voltage H may be equal to the high gate voltage VGH_EM, and the low-level voltage L may be equal to the second low gate voltage VGL2 EM.

At a first time point TP1, the input signal EM_FLM/EM_PCR may be changed to the low-level voltage L, the first clock signal EM_CLK1 may be changed to the high-level voltage H, and the second clock signal EM_CLK2 may be changed to the low-level voltage L. The first transistors T1_1 and T1_2 and the seventh transistor T7 may be turned on based on the first clock signal EM_CLK1. The first transistors T1_1 and T1_2 may provide the input signal EM_FLM/EM_PCR having the low-level voltage L to the first control node NQ1, and the first control node NQ1 may have the low-level voltage L. The third transistor T3 and the ninth transistor T9 may be turned on based on the high gate voltage VGH_EM. The third transistor T3 may provide the low-level voltage L to the second control node NQ2. The seventh transistor T7 may provide the high gate voltage VGH_EM to the first electrode of the ninth transistor T9, and the first electrode of the ninth transistor T9 may have the high-level voltage H. The ninth transistor T9 may provide the high-level voltage H to the gate electrode of the tenth transistor T10. The tenth transistor T10 may be turned on based on the high-level voltage H. The tenth transistor T10 may provide the second clock signal EM_CLK2 having the low-level voltage L to the gate electrode of the 11th transistor T11, and the gate electrode of the 11th transistor T11 may have the low-level voltage L.

At a second time point TP2, the input signal EM_FLM/EM_PCR may have the low-level voltage L, the first clock signal EM_CLK1 may be changed to the low-level voltage L, and the second clock signal EM_CLK2 may be changed to the high-level voltage H. The tenth transistor T10 may provide the second clock signal EM_CLK2 having the high-level voltage H to the gate electrode of the 11th transistor T11, and the gate electrode of the 11th transistor T11 may have the high-level voltage H. The 11th transistor T11 may be turned on based on the high-level voltage H. The 11th transistor T11 may provide the high gate voltage VGH_EM to the inversion control node NQB, and the inversion control node NQB may have the high-level voltage H. The 13th transistor T13 and the 14th transistor T14 may be turned on based on the high-level voltage H. The 13th transistor T13 may provide the second low gate voltage VGL2_EM to the carry output node NCR, and the 14th transistor T14 may provide the first low gate voltage VGL_EM to the emission output node NEM.

At a third time point TP3, the input signal EM_FLM/EM_PCR may have the high-level voltage H, the first clock signal EM_CLK1 may be changed to the high-level voltage H, and the second clock signal EM_CLK2 may be changed to the low-level voltage L. The first transistors T1_1 and T1_2 may be turned on based on the first clock signal EM_CLK1. The first transistors T1_1 and T1_2 may provide the input signal EM_FLM/EM_PCR having the high-level voltage H to the first control node NQ1, and the first control node NQ1 may have the high-level voltage H. The fourth transistor T4 may be turned on based on the high-level voltage H. The fourth transistor T4 may provide the second low gate voltage VGL2_EM to the inversion control node NQB, and the inversion control node NQB may have the low-level voltage L. The third transistor T3 may be turned on based on the high gate voltage VGH_EM. The third transistor T3 may provide the high-level voltage H to the second control node NQ2, and the fifth transistor T5 may be turned on based on the high-level voltage H. The fifth transistor T5 may provide the next emission carry signal EM_NCR to the boosting node NB (for example, the second electrode of the first capacitor C1).

At a fourth time point TP4, the emission carry signal EM_CR may be changed from the low-level voltage L to the high-level voltage H, a voltage of the boosting node NB may be boosted by a difference between the high-level voltage H and the low-level voltage L, the boosting node NB may have the high-level voltage H, and the second control node NQ2 may have a boosted high-level voltage BH. The sixth transistor T6 and the 12th transistor T12 may be turned on based on the high-level voltage H. The sixth transistor T6 may provide the high gate voltage VGH_EM to the carry output node NCR, and the 12th transistor T12 may provide the high gate voltage VGH_EM to the emission output node NEM.

In an embodiment, a difference between the high-level voltage H and the low-level voltage L of each of the first clock signal EM_CLK1 and the second clock signal EM_CLK2 may be smaller than a difference between the high gate voltage VGH_EM and the second low gate voltage VGL2_EM. Accordingly, the power consumption of the emission stage 200 may be reduced.

In an embodiment, the high-level voltage H of each of the first clock signal EM_CLK1 and the second clock signal EM_CLK2 may be smaller than the high gate voltage VGH_EM. For example, the high-level voltage H of each of the first clock signal EM_CLK1 and the second clock signal EM_CLK2 may be about 13 V.

FIG. 5 is a schematic diagram of an equivalent circuit illustrating a boosting circuit of an emission stage according to a comparative example. FIG. 6 is a schematic timing diagram illustrating an operation of a boosting circuit according to the comparative example of FIG. 5.

Referring to FIGS. 1 to 6, a boosting circuit of an emission stage according to a comparative example may include a fifth transistor T5 and a first capacitor C1, and a first electrode of the fifth transistor T5 may receive a second clock signal EM_CLK2.

At a fourth time point TP4, the second clock signal EM_CLK2 may be changed from the low-level voltage L to the high-level voltage H, a voltage of a first electrode of the first capacitor C1 may be boosted by a difference between the high-level voltage H and the low-level voltage L, a boosting node NB may have the high-level voltage H, and the second control node NQ2 may have a boosted high-level voltage BH. During a boosting period BP, the second clock signal EM_CLK2 may have the alternating high-level voltage H and low-level voltage L. Thus, during the boosting period BP, a voltage of the boosting node NB may be alternately boosted by a difference between the high-level voltage H and the low-level voltage L, and a voltage of the second control node NQ2 may be alternately boosted by a difference between the boosted high-level voltage BH and the high-level voltage H. As a change of voltage is larger, power consumption may be larger. Thus, the power consumption of the emission stage according to the comparative example of FIG. 5 may be large.

FIG. 7 is a schematic diagram of an equivalent circuit illustrating a boosting circuit 260 of an emission stage 200 of FIG. 3. FIG. 8 is a schematic timing diagram illustrating an operation of the boosting circuit 260 of FIG. 7.

Referring to FIGS. 1 to 8, the boosting circuit 260 of the emission stage 200 of FIG. 3 may include a fifth transistor T5 and a first capacitor C1, and a first electrode of the fifth transistor T5 may receive a next emission carry signal EM_NCR.

At a fourth time point TP4, the emission carry signal EM_CR may be changed from a low-level voltage L to a high-level voltage H, a voltage of the boosting node NB may be boosted by a difference between the high-level voltage H and the low-level voltage L, the boosting node NB may have the high-level voltage H, and the second control node NQ2 may have a boosted high-level voltage BH. During the boosting period BP, the emission carry signal EM_CR may be constant. Thus, during the boosting period BP, the voltage of the boosting node NB may be constant, and the voltage of the second control node NQ2 may be constant. As a change of voltage is smaller, power consumption may be smaller. Accordingly, the power consumption of the emission stage 200 of FIG. 3 may be small.

FIG. 9 is a schematic block diagram illustrating a gate driver 130 included in a display device 10 of FIG. 1.

Referring to FIGS. 1 and 9, the gate driver 130 may include gate stages GS_STAGE1, GS_STAGE2, GS_STAGE3, GS_STAGE4, . . . which receive a gate start signal GS_FLM, a first clock signal GS_CLK1, and a second clock signal GS_CLK2, and output gate signals GS [1], GS [2], GS [3], GS [4] . . . and gate carry signals GS_CR[1], GS_CR[2], GS_CR[3], GS_CR[4], . . . . A first gate stage GS_STAGE1 may receive the gate start signal GS_FLM as an input signal. Subsequent gate stages GS_STAGE2, GS_STAGE3, GS_STAGE4, . . . may receive the gate carry signals GS_CR[1], GS_CR[2], GS_CR[3], GS_CR[4], . . . of each of the previous gate stages as the input signal.

The gate stages GS_STAGE1, GS_STAGE2, GS_STAGE3, GS_STAGE4, . . . may include odd-numbered gate stages GS_STAGE1, GS_STAGE3, . . . , and even-numbered gate stages GS_STAGE2, GS_STAGE4, . . . . The odd-numbered gate stages GS_STAGE1, GS_STAGE3, . . . may receive the input signals based on the first clock signal GS_CLK1, and may output gate signals GS [1], GS [3], . . . and gate carry signals GS_CR[1], GS_CR[3], . . . based on the second clock signal GS_CLK2. The even-numbered gate stages GS_STAGE2, GS_STAGE4, . . . may receive the input signals based on the second clock signal GS_CLK2, and may output gate signals GS [2], GS [4], . . . and gate carry signals GS_CR[2], GS_CR[4], . . . based on the first clock signal GS_CLK1.

For example, as shown in FIG. 9, the gate stages GS_STAGE1, GS_STAGE2, GS_STAGE3, GS_STAGE4, . . . may sequentially output the gate carry signals GS_CR[1], GS_CR[2], GS_CR[3], GS_CR[4], . . . and the gate signals GS [1], GS [2], GS [3], GS [4], . . . in a frame period. The first gate stage GS_STAGE1 may output a first gate carry signal GS_CR[1] and a first gate signal GS [1] based on the gate start signal GS_FLM. The second gate stage GS_STAGE2 may output a second gate carry signal GS_CR[2] and a second gate signal GS [2] based on the first gate carry signal GS_CR[1]. The third gate stage GS_STAGE3 may output a third gate carry signal GS_CR[3] and a third gate signal GS_[3] based on the second gate carry signal GS_CR[2]. The fourth gate stage GS_STAGE4 may output a fourth gate carry signal GS_CR[4] and a fourth gate signal GS [4] based on the third gate carry signal GS_CR[3].

FIG. 10 is a schematic diagram of an equivalent circuit illustrating a gate stage 300 included in a gate driver 130.

Referring to FIGS. 1, 9 and 10, the gate driver 130 may include gate stages 300. The gate stage 300 may include an input circuit 310, a first inversion control circuit 320-1, a second inversion control circuit 320-2, a control circuit 330, a gate output circuit 340, a carry output circuit 350, a boosting circuit 360, a first selection circuit 370-1, and/or a second selection circuit 370-2.

The input circuit 310 may provide an input signal G_FLM/G_PCR to control nodes NQ1 and NQ2. The input signal G_FLM/G_PCR may be a gate start signal G_FLM or a previous gate carry signal G_PCR. The gate start signal G_FLM may be a signal for starting an operation of a first gate stage GS_STAGE1 of the gate stages 300. The previous gate carry signal G_PCR may be a gate carry signal output from any one of previous gate stages. In an embodiment, the input circuit 310 may include first transistors T1_1 and T1_2.

The first transistors T1_1 and T1_2 may include a gate electrode configured to receive a first clock signal G_CLK1, a first electrode configured to receive the input signal G_FLM/G_PCR, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The first transistors T1_1 and T1_2 may provide the input signal G_FLM/G_PCR to the control nodes NQ1 and NQ2 based on the first clock signal G_CLK1. In an embodiment, the first transistors T1_1 and T1_2 may include a first-1 transistor T1_1 and a first-2 transistor T1_2 which are connected in series and have gate electrodes connected to each other.

The first inversion control circuit 320-1 may control a voltage of a first inversion control node NQB1 based on a voltage of the control nodes NQ1 and NQ2. In an embodiment, the first inversion control circuit 320-1 may include a 16th transistor T16.

The 16th transistor T16 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive a second low gate voltage VGL2_G, and a second electrode connected to the first inversion control node NQB1. The 16th transistor T16 may provide the second low gate voltage VGL2_G to the first inversion control node NQB1 based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the 16th transistor T16 may further include a back gate electrode connected to the control nodes NQ1 and NQ2.

The second inversion control circuit 320-2 may control a voltage of a second inversion control node NQB2 based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the second inversion control circuit 320-2 may include a 21st transistor T21.

The 21st transistor T21 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive the second low gate voltage VGL2_G, and a second electrode connected to the second inversion control node NQB2. The 21st transistor T21 may provide the second low gate voltage VGL2_G to the second inversion control node NQB2 based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the 21st transistor T21 may further include a back gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1).

The control circuit 330 may control the voltage of the control nodes NQ1 and NQ2 based on the voltage of the first inversion control node NQB1 or the voltage of the second inversion control node NQB2. In an embodiment, the control circuit 330 may include second transistors T2_1 and T2_2 and third transistors T3_1 and T3_2.

The second transistors T2_1 and T2_2 may include a gate electrode connected to the second inversion control node NQB2, a first electrode configured to receive the second low gate voltage VGL2_G, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The second transistors T2_1 and T2_2 may provide the second low gate voltage VGL2_G to the control nodes NQ1 and NQ2 based on the voltage of the second inversion control node NQB2. In an embodiment, the second transistors T2_1 and T2_2 may include a second-1 transistor T2_1 and a second-2 transistor T2_2 which are connected in series and have gate electrodes connected to each other. In an embodiment, the second-2 transistor T2_2 may further include a back gate electrode configured to receive the second low gate voltage VGL2_G.

The third transistors T3_1 and T3_2 may include a gate electrode connected to the first inversion control node NQB1, a first electrode configured to receive the second low gate voltage VGL2_G, and a second electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1). The third transistors T3_1 and T3_2 may provide the second low gate voltage VGL2_G to the control nodes NQ1 and NQ2 based on the voltage of the first inversion control node NQB1. In an embodiment, the third transistors T3_1 and T3_2 may include a third-1 transistor T3_1 and a third-2 transistor T3_2 which are connected in series and have gate electrodes connected to each other. In an embodiment, the third-2 transistor T3_2 may further include a back gate electrode configured to receive the second low gate voltage VGL2_G.

The gate output circuit 340 may output a high gate voltage VGH_G as a gate signal GS based on the voltage of the control nodes NQ1 and NQ2, and may output a first low gate voltage VGL_G as the gate signal GS based on the voltage of the first inversion control node NQB1 or the voltage of the second inversion control node NQB2. In an embodiment, the gate output circuit 340 may include a ninth transistor T9, a tenth transistor T10, an 11th capacitor T11, and a second capacitor C2.

The ninth transistor T9 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive the high gate voltage VGH_G, and a second electrode connected to a gate output node NG at which the gate signal GS is output. The ninth transistor T9 may provide the high gate voltage VGH_G to the gate output node NG based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the ninth transistor T9 may further include a back gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2).

The tenth transistor T10 may include a gate electrode connected to the first inversion control node NQB1, a first electrode configured to receive the first low gate voltage VGL_G, and a second electrode connected to the gate output node NG. The tenth transistor T10 may provide the first low gate voltage VGL_G to the gate output node NG based on the voltage of the first inversion control node NQB1. In an embodiment, the tenth transistor T10 may further include a back gate electrode connected to the first inversion control node NQB1.

The 11th transistor T11 may include a gate electrode connected to the second inversion control node NQB2, a first electrode configured to receive the first low gate voltage VGL_G, and a second electrode connected to the gate output node NG. The 11th transistor T11 may provide the first low gate voltage VGL_G to the gate output node NG based on the voltage of the second inversion control node NQB2. In an embodiment, the 11th transistor T11 may further include a back gate electrode connected to the second inversion control node NQB2.

The second capacitor C2 may include a first electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2) and a second electrode connected to the gate output node NG. The second capacitor C2 may reduce a distorted waveform of the gate signal GS.

The carry output circuit 350 may output the high gate voltage VGH_G as a gate carry signal G_CR based on the voltage of the control nodes NQ1 and NQ2, and may output the second low gate voltage VGL2_G as the gate carry signal G_CR based on the voltage of the first inversion control node NQB1 or the voltage of the second inversion control node NQB2. In an embodiment, the carry output circuit 350 may include a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

The sixth transistor T6 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive the high gate voltage VGH_G, and a second electrode connected to the carry output node NCR at which the gate carry signal G_CR is output. The sixth transistor T6 may provide the high gate voltage VGH_G to the carry output node NCR based on the voltage of the control nodes NQ1 and NQ2. In an embodiment, the sixth transistor T6 may further include a back gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2).

The seventh transistor T7 may include a gate electrode connected to the first inversion control node NQB1, a first electrode configured to receive the second low gate voltage VGL2 G, and a second electrode connected to the carry output node NCR. The seventh transistor T7 may provide the second low gate voltage VGL2_G to the carry output node NCR based on the voltage of the first inversion control node NQB1. In an embodiment, the seventh transistor T7 may further include a back gate electrode connected to the first inversion control node NQB1.

The eighth transistor T8 may include a gate electrode connected to the second inversion control node NQB2, a first electrode configured to receive the second low gate voltage VGL2_G, and a second electrode connected to the carry output node NCR. The eighth transistor T8 may provide the second low gate voltage VGL2_G to the carry output node NCR based on the voltage of the second inversion control node NQB2. In an embodiment, the eighth transistor T8 may further include a back gate electrode connected to the second inversion control node NQB2.

The boosting circuit 360 may boost the voltage of control nodes NQ1 and NQ2. The boosting circuit 360 may include a fifth transistor T5 and a first capacitor C1.

The fifth transistor T5 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2), a first electrode configured to receive a next gate carry signal G_NCR, and a second electrode connected to the second control node NQ2. The next gate carry signal G_NCR may be a gate carry signal output from any one of next gate stages.

The first capacitor C1 may include a first electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2) and a second electrode connected to the boosting node NB. The first capacitor C1 may boost the voltage of control nodes NQ1 and NQ2. As the voltage of the control nodes NQ1 and NQ2 (for example, the voltage of the gate electrode of the 12th transistor T12) is boosted by the first capacitor C1, the 12th transistor T12 may smoothly provide the high gate voltage VGH_G to the gate output node NG. As the voltage of the control nodes NQ1 and NQ2 (for example, the voltage of the gate electrode of the sixth transistor T6) is boosted by the first capacitor C1, the sixth transistor T6 may smoothly provide the high gate voltage VGH_G to the carry output node NCR.

The first selection circuit 370-1 may activate the seventh transistor T7 and the tenth transistor T10 and may inactivate the eighth transistor T8 and the 11th transistor T11 based on a first selection signal G_GBL1. In an embodiment, the first selection circuit 370-1 may include 12th transistors T12_1 and T12_2, a 13th transistor T13, a 14th transistor T14, a 15th transistor T15, and a third capacitor C3.

The 12th transistors T12_1 and T12_2 may include a gate electrode configured to receive the first selection signal G_GBL1, a first electrode configured to receive the first selection signal G_GBL1, and a second electrode. In an embodiment, the 12th transistors T12_1 and T12_2 may include a 12th-1 transistor T12_1 and a 12th-2 transistor T12_2 which are connected in series and have gate electrodes connected to each other. The 13th transistor T13 may include a gate electrode connected to the second electrode of the 12th transistors T12_1 and T12_2, a first electrode configured to receive the first selection signal G_GBL1, and a second electrode. The 14th transistor T14 may include a gate electrode configured to receive a second clock signal G_CLK2, a first electrode connected to the second electrode of the 13th transistor T13, and a second electrode connected to the first inversion control node NQB1. The 15th transistor T15 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive the first low gate voltage VGL_G, and a second electrode connected to the gate electrode of the 13th transistor T13. The third capacitor C3 may include a first electrode connected to the gate electrode of the 13th transistor T13 and a second electrode connected to the first inversion control node NQB1. The third capacitor C3 may quickly turn on and turn off the 13th transistor T13.

The second selection circuit 370-2 may activate the eighth transistor T8 and the 11th transistor T11 and may inactivate the seventh transistor T7 and the tenth transistor T10 based on a second selection signal G_GBL2. In an embodiment, the second selection circuit 370-2 may include 17th transistors T17_1 and T17_2, an 18th transistor T18, a 19th transistor T19, a 20th transistor T20, and a fourth capacitor C4.

The 17th transistors T17_1 and T17_2 may include a gate electrode configured to receive the second selection signal G_GBL2, a first electrode configured to receive the second selection signal G_GBL2, and a second electrode. In an embodiment, the 17th transistors T17_1 and T17_2 may include a 17th-1 transistor T17_1 and a 17th-2 transistor T17_2 which are connected in series and have gate electrodes connected to each other. The 18th transistor T18 may include a gate electrode connected to the second electrode of the 17th transistors T17_1 and T17_2, a first electrode configured to receive the second selection signal G_GBL2, and a second electrode. The 19th transistor T19 may include a gate electrode configured to receive the second clock signal G_CLK2, a first electrode connected to the second electrode of the 18th transistor T18, and a second electrode connected to the second inversion control node NQB2. The 20th transistor T20 may include a gate electrode connected to the control nodes NQ1 and NQ2 (or the first control node NQ1), a first electrode configured to receive the first low gate voltage VGL_G, and a second electrode connected to the gate electrode of the 18th transistor T18. The fourth capacitor C4 may include a first electrode connected to the gate electrode of the 18th transistor T18 and a second electrode connected to the second inversion control node NQB2. The fourth capacitor C4 may quickly turn on and turn off the 18th transistor T18.

The first selection signal G_GBL1 and the second selection signal G_GBL2 may have different phases (e.g., opposite phases). Each of the first selection signal G_GBL1 and the second selection signal G_GBL2 may have an alternating high-level voltage and low-level voltage. In an embodiment, in a first frame period, the first selection signal G_GBL1 and the second selection signal G_GBL2 may have a high-level voltage and a low-level voltage, respectively, and thus the seventh transistor T7 and the tenth transistor T10 may operate. In addition, in a second frame period after the first frame period, the first selection signal G_GBL1 and the second selection signal G_GBL2 may have a low-level voltage and a high-level voltage, respectively, and thus the eighth transistor T8 and the 11th transistor T11 may operate.

In an embodiment, the gate stage 300 may further include 23rd transistors T23_1 and T23_2. The 23rd transistors T23_1 and T23_2 may include a gate electrode configured to receive a reset signal ESR, a first electrode configured to receive the first low gate voltage VGL_G, and a second electrode connected to the control nodes NQ1 and NQ2 (or the second control node NQ2). The 23rd transistors T23_1 and T23_2 may provide the first low gate voltage VGL_G to the control nodes NQ1 and NQ2 based on the reset signal ESR. In an embodiment, the 23rd transistors T23_1 and T23_2 may include a 23rd-1 transistor T23_1 and a 23rd-2 transistor T23_2 which are connected in series and have gate electrodes connected to each other.