526. Thus, the non-zero-magnitude signal 524 may be shaped to maintain stability of the two-wire lighting control device 502.

The first signal 520 and the non-zero-magnitude signal 524 may be added together to form the combined signal 528 for the filter circuit 526. In this example, the non-zero-magnitude signal 524 may have a magnitude of effectively zero volts when the first signal 520 has a non-zero magnitude, and the non-zero-magnitude signal 524 may have a non-zero magnitude when the magnitude of the first signal 520 is effectively zero volts.

The first signal 520 and the non-zero-magnitude signal 524 may be combined together by a combiner circuit 525 to form the combined signal 528 for the filter circuit 526. In this example, the two-wire lighting control device 502 may include a switch (not shown), such as a multiplexer for example. The multiplexer may receive the first signal 520 on a first input and may receive the non-zero-magnitude signal 524 on a second input. The multiplexer may select the first input or the second input to output in dependence upon a select signal. The select signal may be based on the inputs. For example, when the first signal 520 has a non-zero magnitude, the multiplexer may select the first input (i.e., the first signal 520) to output, and when the magnitude of the first signal 520 is effectively zero volts, the multiplexer may select the second input (i.e., the non-zero-magnitude signal) to output. The select signal may be based on the trigger signal generated at the control input of the controllably conductive device 508 by the control circuit 510. For example, the multiplexer may operate in concert with the trigger signal between the control circuit 510 and the controllably conductive device 508. The multiplexer may select the second input (i.e., the non-zero-magnitude signal 524) when the control signal between the control circuit 510 and the controllably conductive device 508 directs the controllably conductive device 508 to become conductive (i.e., at the phase angle). And, the switch may select the first input (i.e., the first signal 520) when the controllably conductive device 508 becomes non-conductive at the end of the half-cycle.

To illustrate, the controllably conductive device 508 may be non-conductive for a first duration of time and conductive for a second duration of time. The multiplexer may select the first signal 520 during the first duration of time and the non-zero-magnitude signal 524 during the second duration of time. And, as illustrated in FIG. 5, the combined signal 528 may include a portion of the first signal 520 (shown in solid line) and a portion of the non-zero-magnitude signal 524 (shown in broken line). In the resultant combined signal 528, the non-zero-magnitude signal portion may serve to complement (e.g., to complete) the first signal portion. In other words, the non-zero-magnitude signal 524 may be a fill-signal that fills-in a missing portion of the first signal 520.

The filter circuit 526 may filter the combined signal 528 to attenuate high-frequency components, particularly high-frequency noise associated with the first signal 520 that may tend to cause errors in zero-crossing detection. The filter circuit 526 may be consistent with the filters disclosed in previously-referenced U.S. Pat. Nos. 6,091,205 and 6,380,692. For example, the filter circuit 526 may be a low-pass filter, such as, for example, a Bessel filter for example, which may be configured to provide a substantially linear phase delay of less than one-half of a period of the fundamental frequency. The low-pass filter may be configured to attenuate frequency components of the combined signal 528 that are substantially equal to third order harmonics and greater of the fundamental frequency.

The filtered output is received by a zero-cross detection circuit 530, which may detect when the magnitude of the filtered output crosses effectively zero volts (i.e., goes from positive to negative and/or from negative to positive). The zero-cross detection circuit 530 may provide information indicative of the timing of the zero-crossings to the control circuit 510. And, as described above, the control circuit 510 causes the controllably conductive device 508 to become conductive or non-conductive with timing in accordance with a desired dimming level in the load 506. For example, the timing between a zero-crossing and the subsequent trigger signal to render the controllable conductive device conductive may be commensurate with the desired dimming level.

FIGS. 6A-6E illustrate various combined signals, along with example non-zero-magnitude signal waveforms. The shape or waveform of the non-zero-magnitude signal 524 generated by the signal generator 522 may generally complement the first signal 520 to maintain stability of the overall system. For each example shown in FIGS. 6A-6E, the portion of the combined signal 528 associated with the first signal 520 is shown in solid line, and the portion of the combined signal associated with the non-zero-magnitude signal 524 is shown in broken line. Of course, one of ordinary skill will appreciate that the signals represented are examples and may be adapted for use in forward phase-control, reverse phase-control, and/or center phase-control systems.

As shown in FIG. 6A, the combined signal may represent a smooth sinusoid. Signal 602 is an example combined signal associated with a controllably conductive device 508 operating with a low-end firing angle. Signal 604 is an example combined signal associated with a controllably conductive device operating at a 50% firing angle. And, signal 606 is an example combined signal associated with a controllably conductive device 508 operating at a high-end firing angle. The sinusoidal combined signal shown in FIG. 6A maintains a fundamental frequency consistent with that of the AC line voltage of the AC power source 504. As a result, variation in the phase delay through the filter circuit 526 as a function of the firing time may be mitigated.

Different waveform shapes may be suitable for the portion of the combined signal associated with the non-zero-magnitude signal 524. FIG. 6B illustrates a non-zero-magnitude signal that comprises a square wave having constant amplitude. Signals 608, 610, and 612 represent low-end, 50%, and high-end, respectively. Here, the pulse width of the square wave varies with the firing angle; for example, as shown in FIG. 6B, the square wave is narrow at low-end and is much wider at high-end.

FIG. 6C shows that the width and the amplitude of the square wave may be adjusted according to the firing angle. Signals 614, 616, and 618 represent low-end, 50%, and high-end respectively. For example, the amplitude of the square wave may be selected to match that of the first signal at the firing time. Thus, at low-end, the square-wave fill signal is narrow and has a relatively of low amplitude. At 50%, the square-wave fill signal has a width of one-half of the half-cycle of the AC input signal and is at its highest amplitude (e.g., the peak amplitude of the AC input signal). At high-end, the square-wave fill signal may be at its widest, having a low amplitude, similar to that at low-end.

FIG. 6D shows a non-zero-magnitude signal that may comprise a triangular wave. Signals 620, 622, and 624 represent low-end, 50%, and high-end respectively. At low-end and at 50%, the fill signal may have an initial voltage similar to that of the first signal and then steadily decrease to zero. At high-end, the triangular waveform may be shaped to roughly approximate the sinusoid of the AC line voltage of the AC power source 504. For example, the non-zero-magnitude signal may extend, increasing the amplitude to a peak approximately at the center of the half-cycle of the AC line voltage and then extend, decreasing to zero volts at or around the zero-crossing of the AC power source 504.

FIG. 6E shows that a step-sine wave may be used as a non-zero-magnitude signal. Here, the step-sine wave may include a composite of multiple square waves of varying width and amplitude to approximate a sine wave. Signals 626, 628, and 630 represent low-end, 50%, and high-end respectively.

Each of the example combined signals maintains a fundamental frequency consistent with that of the original AC input signal such that variation in the phase delay through the filter as a function of the firing time may be mitigated. In effect, the non-zero-magnitude signals may provide a corrective influence when the resultant combined signal is filtered. For example, when the first signal is mostly a sinusoid and a smaller portion of the first signal is effectively zero volts, the added area from an example fill signal provides a correction to shift the center fundamental of the filter output and to compensate for any error in the firing angle. Similarly, when the first signal is represented by a small portion of sinusoid and a larger portion of zero, then the fill signal provides additional negative feedback to correct the shift in center of the fundamental of the filter output and to correct the corresponding error in the firing angle.

The example combined signals, shown in FIGS. 6A-E may be used for purposes alternative to or in addition to serving as input to a filter. For example, a combined signal may be used to make a power calculation, as disclosed in commonly-assigned U.S. patent application Ser. No. 13/793,308, entitled POWER MEASUREMENT IN A TWO-WIRE LOAD CONTROL DEVICE, filed Mar. 11, 2013, which is hereby incorporated by reference. For example, the combined signals shown in FIGS. 6A and 6B, may accurately depict an AC voltage waveform such that a useful power calculation may be made.

FIG. 7 is a block diagram of a portion of a two-wire lighting control device 700. The lighting control device 700 comprises a hot terminal H adapted to be coupled an AC power source (not shown) and a dimmed-hot terminal DH adapted to be coupled to a lighting load (not shown). The lighting control device 700 comprises a controllably conductive device that is implemented as two FETs 710, 712 coupled in anti-series connection. The gates of the FETs 710, 712 are coupled to a gate drive circuit 714 and the sources of the FETs are coupled together at circuit common. A control circuit 720 is coupled to the gate drive circuit 714 and generates a drive signal V_DRfor controlling the gate drive circuit to render the FETs 710, 712 conductive and non-conductive to thus control the amount of power delivered to the lighting load.

The lighting control device 700 comprises a power supply (not shown) that may be coupled across the controllably conductive device for generating a supply voltage V_CC(e.g., approximately 3.3 volts) for powering the control circuit 720. The lighting control device 700 also comprises a reference supply (not shown) for generating a reference voltage V_REF, which may have a magnitude equal to approximately one-half of the DC supply voltage V_CC(e.g., approximately 1.5 volts). The reference supply may comprise, for example, a simple power supply, such as a resistor-zener power supply.

The lighting control device 700 generates a combined signal 730 from a dimmer-voltage signal 732 and a non-zero-magnitude signal 734. The lighting control device 700 comprises a scaling circuit 730 coupled across the controllably conductive device (i.e., the anti-series-combination of the FETs 710, 712) for producing a scaled version of the dimmer-voltage waveform developed across the controllably conductive device to which the reference voltage V_REFis added to generate the dimmer-voltage signal 732. Accordingly, the dimmer-voltage signal 732 is representative of the dimmer-voltage waveform developed across the controllably conductive device.

The lighting control device 700 comprises a digital-to-analog converter (DAC) 742 coupled to the control circuit 720 for generating the non-zero-magnitude signal 734. In the example of FIG. 7, the control circuit 720 may generate the non-zero-magnitude signal 734 by sending digital signal values to the digital-to-analog converter 742. For example, the control circuit 720 may have a look-up table of values stored in memory that may represent samples of the non-zero-magnitude signal 734. For example, the values may represent samples of any of the non-zero-magnitude signals, as shown in FIGS. 6A-6E. The control circuit 720 may output these digital values at regular intervals to the digital-to-analog converter 742, such that the digital-to-analog converter may generate an analog representation of the non-zero-magnitude signal 734.

The lighting control device 700 comprises a controllable switch 744, which receives the non-zero-magnitude signal 734 and is controlled by the control circuit 720 to generate the combined signal 730.

The lighting control device 700 also comprise a filter circuit 746 for filtering the combined signal 730 to generate a filtered signal VF and a comparator circuit 748 for comparing the filtered signal to the reference voltage V_REFto generate a zero-crossing signal V_ZCrepresentative of the zero-crossings of the AC power source. The control circuit 720 may control the controllable switch 744 in concert with the generation of drive signal V_DRto control the intensity of the lighting load to the desired dimming level (e.g., firing the controllable switch 708 at the same time). In an example operation, the control circuit 720 may detect a zero-crossing in the signal received from the filter circuit 746 and the comparator circuit 748. The control circuit 720 may time the generation of a control signal for dimming operation based on a desired light level for a first duration of time. And, when generating the control signal to effect dimming operation, the control circuit 720 may close the controllable switch 744 for a second duration of time (e.g., the remaining time in the AC half-cycle) until another zero-crossing is detected. In an example, the combined signal 730 may include, in the first duration of time, a signal representing the dimmer-voltage waveform developed across a controllable conductive device (not shown) and, in the second duration of time, the non-zero-magnitude signal 734 from the digital-to-analog converter 742.

The combined signal 730 may be used for purposes alternative to or in addition to serving as input to the filter circuit 746. A lighting control device may provide the combine signal 730 to a processing circuit (not shown) for performing other operations. For example, the combined signal 730 may be provided to the processing circuit in addition to the filter circuit 746. Also for example, the combined signal 730 may be provided to the processing circuit, and the filter circuit 746 and comparator circuit 748 may be omitted.

The processing circuit may include the control circuit 720 and/or any other device, system, and/or subsystem suitable for processing a signal (e.g., measuring, analyzing, transmitting, conveying, multiplexing, combining, modulating, and/or otherwise performing operation(s) on and/or on the basis of the signal). For example, the processing circuit may use the combined signal 730 to perform measurements and/or calculations regarding the AC voltage and/or current waveforms. For example, the processing circuit may use the combined signal 730 to perform a power calculation. For example, the processing circuit may use the combined signal 730 in connection with circuits that benefit from a full AC voltage waveform to operate, such as circuits that benefit from a full AC voltage waveform for timing information, for example.

FIG. 8 is a simplified flowchart of a zero-crossing procedure 800 executed periodically by a control circuit (e.g., the control circuit 720 of the lighting control device 700) at step 810 (e.g., in response to the zero-crossing signal V_ZC). First, the control circuit 720 drives the drive signal V_DRto the gate drive circuit 714 low (e.g., to approximately circuit common) at step 812, such that the FETs 710, 712 are non-conductive at the beginning of the half-cycle. At step 814, the control circuit 720 controls the controllable switch 744 to be open (i.e., non-conductive), such that the combined signal 730 is equal to the dimmer-voltage signal 732. The control circuit 720 then recalls the firing time T_FIR(i.e., the firing angle) for the present half-cycle to control the intensity of the lighting load to the desired dimming level at step 816. At step 818, the control circuit 720 loads the firing time T_FIRinto timer A and starts timer A, decreasing in value with respect to time, before the zero-crossing procedure 800 exits. The control circuit 720 will execute a dimming timer procedure 900 when timer A expires.

FIG. 9 is a simplified flowchart of the dimming timer procedure 900, which is executed by the control circuit 720 when timer A expires at step 910 (i.e., after the firing time T_FIRfrom the beginning of the half-cycle). The control circuit 720 drives the drive signal V_DRhigh (e.g., to approximately the DC supply voltage V_CC) at step 912 to render the FETs 710, 712 conductive, and then closes the controllable switch 744 at step 914, such that the digital-to-analog converter 742 is coupled to the filter circuit 746. Since the magnitude of the dimmer-voltage signal 732 decreases to approximately zero volts when the FETs 710, 712 are rendered conductive, the combined signal 730 is equal to the non-zero-magnitude signal 734 generated by the digital-to-analog converter 742 after the firing time T_FIR. The dimming timer procedure 900 procedure then exits, and the zero-crossing procedure 800 will be executed at the next zero-crossing as determined by the zero-crossing signal V_ZC.

FIG. 10A is a simplified schematic diagram of a portion of a two-wire lighting control device 1000, which uses pulse-width modulation to generate a non-zero-magnitude signal. FIGS. 10B and 10C depict corresponding signal diagrams. As in the lighting control device 700 of FIG. 7, the lighting control device 1000 comprises two FETs 1010, 1012 in anti-series connection as the controllably conductive device adapted coupled in series between the AC power source and the lighting load. The FETs 1010, 1012 are rendered conductive and non-conductive in response to a drive signal V_DRprovided to a gate drive circuit 1014 by a control circuit 1020 to control the amount of power delivered to the lighting load.

The lighting control device 1000 comprises a multiplexer 1040 for generating a combined signal 1030, a filter 1046 for filtering the combined signal, and a comparator circuit 1048 for generating a zero-crossing signal representative of the zero-crossings of the AC power source. The multiplexer 1040 receives a first signal 1032, which is received from the controllably conductive device, for example, at a normally closed (NC) input of the multiplexer. The first signal 1032 is representative of the dimmer-voltage waveform developed across the controllably conductive device. The lighting control device 1000 comprises a first resistive divider including resistors R1050, R1052, which are coupled in series between the hot terminal H and circuit common, and have resistances of, for example, approximately 784 kΩ and 15 kΩ, respectively. The lighting control device 1000 also comprises a second resistive divider including resistors R1054, R1056, which are coupled in series between the dimmed-hot terminal DH and circuit common, and have resistances of, for example, approximately 784 kΩ and 15 kΩ, respectively.

During the positive half-cycles, current is conducted from the hot terminal H and through the first resistive divider and the body diode of the second FET 1012, such that a scaled voltage representative of the dimmer-voltage waveform across the controllably conductive device is generated by the first resistive divider. During the negative half-cycles, current is conducted from the dimmed-hot terminal DH and through the second resistive divider and the body diode of the first FET 1010, such that a scaled voltage representative of the dimmer-voltage waveform across the controllably conductive device is generated by the second resistive divider. The junction of the resistors R1050, R1052 of the first resistive divider is coupled to the reference voltage V_REFthrough a resistor R1058 (e.g., having a resistance of approximately 5.49 kΩ, and the junction of the resistors R1054, R1056 of the second resistive divider is coupled to the reference voltage V_REFthrough a resistor R1059 (e.g., having a resistance of approximately 5.49 kΩ. Accordingly, the scaled voltages generated by the first and second resistive dividers are referenced about the reference voltage V_REF(and not referenced to circuit common).

The first signal 1032 is generated by combining the scaled voltages generated by the first and second resistive dividers. However, since the scaled voltages generated by the first and second resistive dividers are rectified by the body diodes of the FETs 1010, 1012, the output of the first resistive divider is coupled to the output of the second resistive divider by an inverting circuit 1060, which comprises an operational amplifier (“op-amp”) 1062. The scaled voltage generated by the first resistive divider is coupled to the non-inverting input of the op-amp 1062 via a resistor R1064 (e.g., having a resistance of approximately 464 kΩ. The non-inverting input is coupled to the output of the op-amp 1062 via a resistor R1066 (e.g., having a resistance of approximately 464 kΩ, and the inverting input of the op-amp is coupled to the reference voltage V_REF. The output of the op-amp 1062 is coupled to the output of the second resistive divider via a resistor R1068 (e.g., having a resistance of approximately 5.49 kΩ. Accordingly, the first signal 1032 looks like an AC voltage waveform that is reference about the reference voltage V_REF, such that the magnitude of the first signal is always positive. In other words, the first signal 1032 is representative of the dimmer-voltage waveform generated across the controllably conductive device (which is an AC voltage waveform), but does not drop below zero volts, such that the first signal may be processed by standard digital circuitry.

The non-zero-magnitude signal comprises a step-sine wave 1034 generated by a pair of complementary pulse-width modulated channels on the control circuit 1020: a V_{PWM_LO_SINE}channel 1070 and a V_{PWM_HI_SINE}channel 1072. The functionality of the pulse-width modulated channels may be an available feature of a microprocessor-based control circuit. The pulse-width modulated channels may be pulse-width modulated channels available on a microprocessor, a dedicated integrated circuit, composed of fundamental circuit elements, and the like. The complementary pulse-width modulated channels output of the control circuit 1020 via respective resistors R1074, R1076 and respective capacitors R1078, R1080. The pulse-width modulated channels output across a storage RC circuit, including storage capacitor C1082 and corresponding resistor R1084 relative to the filter reference voltage V_REF. The step-sine wave 1034 generated by the complementary pulse-width modulated channels and accompanying circuitry is provided to a normally-open (NO) input of the multiplexer 1040.

The multiplexer 1040 may switch between the NC input (i.e., the first signal 1032) and the NO input (i.e., the step-sine wave 1034) in response to a select-input control signal V_MUXprovided at a Mux Control output of the control circuit 1020. The select-input control signal V_MUXis coupled to a select input (IN) of the multiplexer 1040 via a circuit comprising a transistor Q1086 and a resistor R1088. The control circuit 1020 may signal at the Mux Control output in concert with controlling the dimming operation of the FETs 1010, 1012 such that the first signal 1032 and the step-sine wave 1034 are combined to form the combined signal 1030 at the output COM pin of the multiplexer 1040. When the select-input control signal V_MUXis driven high (i.e., to approximately the DC supply voltage V_CC), the transistor Q1086 is rendered conductive and the select input IN of the multiplexer 1040 is pulled down to circuit common, such that the first signal 1032 at the NC input is provided at the output COM pin of the multiplexer. When the select-input control signal V_MUXis driven low (i.e., to approximately circuit common), the transistor Q1086 becomes non-conductive and the select input IN of the multiplexer 1040 is pulled up towards the DC supply voltage V_CCthrough the resistor 1088, such that the step-sine wave 1034 at the NO input is provided at the output COM pin of the multiplexer.

In operation, the complementary pulse-width modulated channels V_{PWM_LO_SINE}, V_{PWM_HI_SINE}add or subtract charge to and from the storage capacitor C1082 to adjust the magnitude of the step-sine wave 1034 with respect to the reference voltage V_REF. As illustrated in FIG. 10B, in each positive half-cycle of the step-sine wave 1034, the PWM_LO_SINE channel 1070 stays in a high default state, while the PWM_HI_SINE channel 1072 is controlled through a series of pulses to add charge to the storage capacitor C1082 when the PWM_HI_SINE channel 1072 is high and to subtract charge from the storage capacitor C1082 when the PWM_HI_SINE channel 1072 is low. By controlling the duty cycle of the pulses of the PWM_HI_SINE channel 1072 (i.e., the amount of time that the PWM_HI_SINE channel 1072 is high versus low), the control circuit 1020 is able to adjust the magnitude of the step-sine wave 1034 in each positive half-cycle. In each negative half-cycle of the step-sine wave 1034 as illustrated in FIG. 10C, the PWM_HI_SINE channel 1072 stays in a low default state, while the PWM_LO_SINE channel 1070 is controlled through a series of pulses to subtracts charge from the storage capacitor C1082 when the PWM_LO_SINE channel 1070 is low and to add charge to the storage capacitor C1082 when the PWM_LO_SINE channel 1070 is high.

As illustrated, the width of the pulse may affect the rate of change of the step-sine wave 1034. For example, changing the width of each pulse of the PWM_HI_SINE channel 1072 may change the overall rate of change in the step-sine wave 1034 in the positive direction. Similarly, changing the width of each pulse of the PWM_LO_SINE channel 1070 may change the overall rate of change in the step-sine wave 1034 in the negative direction.

To generate the appropriate duty cycles for the pulse-width modulated channels, the control circuit 1020 may have stored one or more tables. The control circuit 1020 may control the state of each of the pulse-width modulated channels, performing a “SET” when a timing counter is zero and a “RESET” when the counter reaches a value, such as a value stored in a register. In light of the SET/RESET structure, the frequency of the step-sine wave 1034 may be configurable, for example, to match the line frequency. An AC half-cycle may be divided into a number of bins, and the modulo of a timer channel may be used to control the period of the half-cycle. The modulo may be 1/N_BINSof the half-cycle period where N_BINSis the number of bins used. The timer channel may calculate the half-cycle period on a half-cycle-by-half-cycle basis. Also, for example, the number N_BINSof bins in the half-cycle may be selected to be an exponent of two. To illustrate, the number N_BINSof bins may be 32 per half-cycle to provide acceptable resolution and preserve processing capacity by limiting the number of interrupts required.

One or more lookup tables may be created to generate the step-sine wave 1034. Each value from the lookup table may be fed into the value register. At each timer overflow, the next value may be loaded. Each value, when loaded, may establish the voltage value for that bin. In effect, the voltage step in each bin may be proportional to the duty cycle in that bin, and the duty cycle is provided by the value from the register. The frequency of the step-sine wave 1034 may be set based on a look-up table, created from a sine table. Here, the duty cycle is “value/modulo,” and the “modulo” is based on the line frequency (e.g., modulo=f/2*32, for 32 bins).

The table values may be scaled. The scaled tables may have a three-element depth, which may allow read and write functions each to have ownership of one element, with one element in redundancy. The task execution may be asynchronous, and a page switching scheme may be used to make sure that reading and writing avoid overlapping. Also, the page switching scheme may be used to ensure that table updates are absorbed at the zero cross.