120 takes the form of a heterojunction bipolar transistor (HBT). In the case where BT structure 120 is an NPN-type transistor and subcollector 122 and collector 124 are doped n-type, intrinsic base 126 may be doped p-type to form a P-N junction, and hence a base-to-collector interface. It is also understood that intrinsic base 126 may be doped n-type in the case where the bipolar transistor is a PNP-type transistor. However embodied, intrinsic base 126 may extend to a predetermined height over collector 124 and, as discussed herein, intrinsic base 126 may have sidewalls substantially aligned with those of collector 124 thereunder.

Intrinsic base 126 may be structurally and compositionally distinct from other portions of a base terminal for BT structure 120. Intrinsic base 126 in particular may be lightly doped, or possibly undoped, whereas other bases (e.g., extrinsic base(s) 128 discussed herein) may be doped more highly than intrinsic base 126. Intrinsic base 126 may be formed, e.g., by forming a layer of semiconductor material, which may be monocrystalline silicon or SiGe as discussed herein, on collector 124. Additional semiconductor material may be formed through selective epitaxial growth and/or similar processes to form additional semiconductor material while preserving the crystallographic orientation and/or composition of the underlying material(s). Selective epitaxial growth of intrinsic base 126 and extrinsic base 128 may cause base(s) 126, 128 to be on, and cover, upper surfaces of collector 124 and isolation layer 131 thereunder.

BT structure 120 may include extrinsic base(s) 128 on isolation layer 131 and adjacent intrinsic base 126. Extrinsic base(s) 128 each may include a polycrystalline semiconductor (e.g., polycrystalline SiGe) with a relatively high amount of the same doping type as (e.g., more p-type doping than) intrinsic base 126. Extrinsic base(s) 128 may be formed, e.g., by depositing an initial (seed) layer of monocrystalline and/or other semiconductor materials on collector 124 and isolation layer 131. Through selective epitaxial growth, deposition, and/or other processing, extrinsic base(s) 128 can be formed from the initial layer to a desired height. Extrinsic base(s) 128 may have sidewalls that are substantially aligned with sidewalls of isolation layer 131 thereunder. Isolation layer 131, by being located underneath extrinsic base(s) 128, partially electrically isolates extrinsic base(s) 128 from each other, such that intrinsic base 126 is between extrinsic base(s) 128 over collector 124.

Emitter 130 may be on intrinsic base 126. As shown, emitter 130 may be formed on intrinsic base 126, for example, by epitaxial growth and doping of additional semiconductor material(s) on intrinsic base 126. Emitter 130 may have the same doping type as subcollector 122 and collector 124, and thus, has an opposite doping type relative to intrinsic base 126. In the case where BT structure 120 is an NPN device, collector 124 and emitter 130 may be doped n-type to provide the two n-type active semiconductor materials, and intrinsic base 126 and extrinsic base(s) 128 may be doped p-type. Emitter 130 may include monocrystalline silicon and/or other monocrystalline semiconductor materials, including one or more materials used elsewhere in structure 100 to form subcollector 122, collector 124, base(s) 126, 128, etc.

A spacer 115 may also be adjacent emitter 130 to structurally and electrically separate emitter 130 and extrinsic base(s) 128, and/or contacts formed thereto. Spacer 115 may have different compositions to control (e.g., increase) the electrical insulation between emitter 130 and nearby portions of extrinsic base(s) 128. For instance, spacer 115 may be an oxide based insulator formed alongside emitter 130. Optionally, additional layers of spacer 115 material may be formed to provide a particular arrangement of insulative materials between extrinsic base(s) 128 and emitter 130. Other compositions and/or arrangements of spacer 115 currently known or later developed also may be used. Spacer(s) 115 thus may include oxide materials, nitride materials, and/or any other insulative material discussed herein, e.g., compositions similar to insulator layer 105 or other insulating structures. Spacer(s) 115 be formed, e.g., by depositing layers of spacer material such that each covers any exposed surfaces of a targeted component (e.g., emitter 130, gate conductor 108 of FET structure 104, etc.). In various implementations, spacer(s) 115 may include a single layer or more than two layers. Spacer(s) 115 adjacent emitter 130 may be formed in different stages of processing from any spacer(s) 115 of FET structure 104, and in some cases may have a different material composition.

Referring to FIGS. 1 and 2 together, with FIG. 2 providing a plan view of structure 100 in plane X-Y, BT structure 120 also may include an emitter contact 132 and a base contact 134. Each contact 132, 134 electrically couple emitter 130 and extrinsic base 128, respectively, of BT structure 120 to overlying metal wires and/or vias. Notably, subcollector 122 may not have a contact thereto and may only be coupled between S/D terminal 106 of FET structure 104 and collector 124. Thus, subcollector 122 interlinks structures 104, 120 during operation but may not have dedicated conductive pathways to overlying metal wires and/or vias. Contact(s) 112, 114, 132, 134 optionally may be formed as part of a single operation, e.g., by removing portions of ILD layer 110 to form openings, optionally forming silicide layers (discussed elsewhere herein) on semiconductor materials exposed within the openings, and filling the openings with metal to define each contact 112, 114, 132, 134. One or more of contacts 112, 114, 132, 134 may include refractory metal liners (not separately shown) on their sidewalls to impede or prevent electromigration degradation, shorting to other components, etc. As shown, structure 100 may include four contacts 112, 114, 132, 134 and thus may include only one contact 114 to S/D terminal 106 and only one contact 134 to emitter 130, with no contacts being specifically provided for subcollector 122 and/or subcollector 122 (FIG. 1). Other arrangements of structure 100 are possible as discussed herein.

Referring to FIG. 3, portions of some active semiconductor materials (e.g., S/D terminal(s) 106, gate conductor 108, extrinsic base 128, emitter 130) may be converted into a silicide layer 150 to improve conductivity between each contact 112, 114, 132, 134 and the semiconductor materials thereunder, e.g., by providing a conductive metal alloy including silicon and, for example, cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar material on the upper surface(s) of a targeted material. The conductive material(s) may be annealed while in contact with the underlying semiconductor to produce silicide layer 150 for electrically coupling semiconductor materials to any contacts, 112, 114, 132, 134 formed thereon. Excess conductive material can then be removed using any now known or later developed solution, e.g., etching, chemical mechanical planarization (CMP), etc., where applicable. Silicide layer(s) 150 also may be formed in locations without contact(s) 112, 114, 132, 134 thereto. For instance, silicide layer(s) 150 may be formed as the interface between S/D terminal 106 and subcollector 122 simultaneously with, or otherwise similarly to, other silicide layers 150 before ILD 110 is formed. Silicide layer 150 may be partially within S/D terminal 106 and partially within subcollector 122. Silicide layer(s) 150 may traverse the boundary between S/D terminal 106 and subcollector 122, e.g., to provide a more highly conductive pathway from FET structure 104 to BT structure 120. Silicide layer(s) 150 from S/D terminal 106 to subcollector 122, moreover, may provide an electrical short to reduce electrical resistance along the pathway from S/D terminal 106 to collector 124 through subcollector 122.

Turning to FIG. 4, further implementations of structure 100 may provide FET structure 104 and BT structure 120 in a triple well configuration. A triple well configuration refers to substrate configurations featuring multiple doped wells within a substrate, instead of a deep well, with various shallow wells inside of a particular doped well. These wells may have p-type and n-type doping, e.g., to provide opposite polarity FETs (e.g., multiple FET structure 104 of varying polarity) in close proximity within a device layer. As shown in FIG. 4, structure 100 may include a doped well 152 (e.g., p-type or n-type doped semiconductor) in a particular concentration beneath S/D terminals 106 and channel region 107. Doped well 152 may have the same doping type as channel region 107 and/or subcollector 122 in various embodiments. A shallow well 154 may be on doped well 152 and may have the opposite doping type from doped well 152 thereunder as well as channel region 107 and/or subcollector 122 thereover. Thus, doped well 152, shallow well 154, and any components formed thereover form three regions of alternating polarity to define a triple well structure. Adjacent portions of a device (e.g., those separated from structure 100 by insulator layers 105 in the form of STIs) may have different polarities from structure 100, e.g., by optionally omitting shallow well 154 where desired. Silicide layers 150 (FIG. 3) are omitted from FIG. 4 solely for clarity of illustration but also may be included.

FIG. 5 illustrates further configurations of structure 100 in which FET structure 104 has a different doping polarity from other implementations discussed herein. In other embodiments of structure 100 discussed herein, FET structure 104 is illustrated as being in the form of a PFET, and thus S/D terminal 106 may be doped p-type to correspond to the n-type doping of subcollector 122. Structure 100 is operable for use with other transistor polarities, including implementations where the doping type of S/D terminal 106 does not match that of subcollector 122. In this case, subcollector 122 may include a transitional S/D terminal 156 adjacent one S/D terminal 106 and having an opposite doping type. To improve conductivity between S/D terminals 106, 156, one silicide layer 150 may be formed within the upper surface of each terminal 106, 156 to provide a conductive pathway between the two doped semiconductor materials despite their different doping polarities. Although additional S/D terminal 156 is within subcollector 122, it may be laterally adjacent and in physical contact with S/D terminal 106 of FET structure 104 along its sidewalls. The presence of additional S/D terminal 156 may allow BT structure(s) 120 having a different polarity from that of FET structure 104 (i.e., where BT structure 120 is an NPN bipolar transistor but FET structure 104 is an PFET) to be provided together in structure 100 with few changes, e.g., creating additional S/D terminal 156 but not necessarily additional contact(s) thereto. In all other respects, structure 100 with additional S/D terminal 156 may be similar or identical to other implementations discussed herein.

FIG. 6 depicts a plan view of a further implementation of structure 100, with an optional additional contact to the interconnected S/D terminal 106 and subcollector 122. Although subcollector 122 need not include a conductive contact thereto, various implementations of structure 100 may include such a contact and additional components for further control of FET structure 104 and/or BT structure 120. For example, to account for possible overcurrent during operation of structure 100, a collector contact 136 may be on subcollector 122 (e.g., out of plane with other contacts 112, 114, 132, 134) for coupling subcollector 122 with a shunt capacitor 138, inductor 140, and external coupling 142. Shunt capacitor 138 and inductor 140, may have a sufficient impedance to prevent any electrical current from passing therethrough during non-overcurrent situations within structure 100. To prevent excessive currents from negatively affecting structure(s) 104, 120, shunt capacitor 138 and inductor 140 together may allow excess currents to bypass either or both of structures 104, 120 during operation and pass to other components (e.g., ground and/or other circuitry) via external coupling 142. In such cases, structure 100 may operate substantially as though collector contact 136, shunt capacitor 138, and inductor 140 are not present when overcurrent events are not occurring. Structure 100 also may include a different arrangement of components coupled to subcollector 122, e.g., in any situation where it may be desirable to couple external components to S/D terminal 106 of FET structure 104 and collector 124 of BT structure 120 through subcollector 122.

Turning to FIG. 7, further implementations of structure 100 may allow S/D terminal 106 to be coextensive with subcollector 122 (i.e., they may co-occupy one region of doped semiconductor material). Substrate 102, insulator layer 105 (e.g., STIs), and channel region 107 may be provided substantially as described and shown elsewhere herein, with ILD 110 being over S/D terminal 106 and S/D contact 114 extending vertically therethrough. In the implementation of FIG. 6, subcollector 122 is within channel region 107 and coextensive with another S/D terminal 106. The term “coextensive,” as defined previously herein, refers to two components that occupy the same space and thus are formed of an identical material composition. Thus, S/D terminal 106 and subcollector 122 may be within a single region of doped semiconductor region having a uniform doping polarity and concentration (e.g., they may be coextensive within n-type semiconductor material). The coextensive S/D terminal 106 and subcollector 122 may have a similar or identical doping profile (i.e., doping polarity and concentration) as another S/D terminal 106 in structure 100 that is not coextensive with a different subcollector 122. Thus, S/D terminals 106 in structure 100 may be indistinguishable from each other regardless of whether they also function as subcollector 122 during operation of structure(s) 104, 120.

For the coextensive S/D terminal 106 and subcollector 122 to operate, gate conductor 108 may be over channel region 107 between S/D terminal 106 and may be surrounded by gate dielectric layer(s) 109, e.g., including gate dielectric layers and gate spacers. One or more conductive contacts to gate conductor 108 may be located outside the plane (i.e., in front of or behind the plane of the page) to enable application of voltages to gate conductor 108. Such an arrangement is shown in FIG. 9 and discussed elsewhere. Gate dielectric layer 109 may electrically insulate gate conductor 108 from various active semiconductor materials in BT structure 120, e.g., due to the larger doping concentrations of components within BT structure 120. Spacers 115 of varying thickness from gate dielectric 109 also may be on the upper surface and sidewalls of gate conductor 108 to further insulate gate conductor 108 from BT structure 120.

In this configuration, gate conductor 108 and gate dielectric layer 109 serve the same purposes of insulator layer 105 (FIGS. 1, 3-5) during operation. Collector 124 may be formed by epitaxial growth of semiconductor material on the coextensive S/D terminal 106 and subcollector 122, then planarized such that the upper surface of collector 124 is substantially coplanar with gate dielectric layer(s) 109. Intrinsic base 126 and extrinsic base(s) 128 can then be formed on collector 124 and gate dielectric layer(s) 109 in substantially the same shape and configuration as other embodiments. Emitter 130 and contacts 132, 134 then can be formed over base(s) 126, 128 to provide the remaining portions of BT structure 120.

Referring to FIGS. 8 and 9, where FIG. 8 provides a cross-sectional view in plane X-Z and FIG. 9 provides a plan view in plane X-Y, further implementations of structure 100 may enable two FET structures 104 to be provided in the case where one S/D terminal 106 is coextensive with subcollector 122 (FIG. 7 only). Here, two gate conductors 108 and gate dielectric layer(s) 109 may be formed over channel region 107, with the coextensive S/D terminal 106 and subcollector 122 located between gate conductors 108. Two additional S/D terminals 106 (which may not be coextensive with other subcollectors 122) may be over substrate 102 such that each gate conductor 108 is horizontally between two S/D terminals 106. In this arrangement, BT structure 120 may be horizontally between, and coupled to, two FET structures 104. As shown specifically in FIG. 9, gate conductor 108 and gate dielectric layer 109 may surround collector 124, and also may be located under bases 126, 128. Portions of gate conductor 108 located away from FET structure(s) 104 (e.g., along the Y axis as shown) may have gate contacts 112 thereon, such that structure 100 includes contacts 112, 114, 132, 134 discussed herein despite one S/D terminal 106 being coextensive with subcollector 122.

FIG. 10-16 depict various phases of an example method to form structure 100 according to different embodiments. The various examples of processing shown and described herein are provided relative to the example implementation shown in FIGS. 8 and 9, but it is understood that any implementation of structure 100 may be formed using methods of the disclosure by modifications within the skill of one having ordinary skill in the art, or by further modifications herein described.

FIG. 10 depicts the result of various initial phases of processing, where one or more S/D terminals 106 and/or channel region(s) 107 are formed by initial doping of substrate 102 in desired locations and/or to predetermined concentrations with desired polarities. Substrate 102 also may include, e.g., a subcollector site 144 having the same doping type and/or concentration as channel region(s) 107 adjacent thereto or having a different doping profile. In some cases, subcollector site 144 may be free of doping apart from any pre-doping of substrate 102. Gate conductor 108 and gate dielectric layers 109 also may be on channel regions 107, e.g., by way of deposition and etching to form gate structures substantially in accordance with conventional FET processing techniques. Insulator layers 105 (e.g., TIs as discussed herein) also may be on or within substrate 102. Optionally, gate conductor(s) 108 initially may be in the form of a single contiguous gate conductor covering subcollector site 144.

FIG. 11 depicts further processing by forming additional insulator layer 105 material (e.g., additional dielectric materials) to cover any previously formed insulator layer 105, as well as upper surfaces and sidewalls of gate conductor 108 and subcollector site 144 along its upper surface. Insulator layer 105 may be formed by non-conformal or conformal deposition and/or other processes suitable to form dielectric materials. Additionally, insulator layer 105 may include the same or similar materials to spacer(s) 115 discussed elsewhere herein.

FIG. 12 depicts removing a portion of insulator layer 105 and doping of subcollector site 144 (FIGS. 10 and 11) to form S/D terminal 106 and subcollector 122 within substrate 102 (e.g., as a single region of semiconductor material in which S/D terminal 106 and subcollector 122 are coextensive). The removing of insulator layer 105 over subcollector site 144 may include, e.g., covering other portions of the structure with a temporary mask (not shown), removing portions of insulator layer 105 not covered by the temporary mask (e.g., by etching and/or other removal techniques), and thereafter removing the temporary mask. The partial removing insulator layer 105 may create an opening S horizontally adjacent or between gate conductors 108. Directional etching and/or similar techniques to remove insulator layer 105 may prevent gate dielectric layer 109 from being removed from the sidewalls of gate conductors 108. The doping of subcollector site to form S/D terminal 106 and subcollector 122 therein may include, e.g., implantation and/or other techniques to dope a semiconductor material. The continued presence of gate dielectric layer 109 elsewhere on the structure may enable only subcollector site 144 to be doped.