For the purposes of this disclosure, expressions such as “at least one of,” or “any one of,” or “one or more of” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” “at least one selected from the group consisting of X, Y, and Z,” and “at least one selected from the group consisting of X, Y, or Z” may be construed as X only, Y only, Z only, any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expressions “at least one of A and B” and “at least one of A or B” may include A, B, or A and B. As used herein, “or” generally means “and/or,” and the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and/or B” may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are used only used to distinguish one element, member, component, region, area, layer, section, or portion from another element, member, component, region, area, layer, section, or portion. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc. may also be used herein to differentiate different categories or sets of elements. For conciseness, the terms “first,” “second,” etc. may represent “first-category (or first-set),” “second-category (or second-set),” etc., respectively.

In the examples, the x-axis, the y-axis, and/or the z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. The same applies for first, second, and/or third directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, while the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, “substantially” may include a range of +/−5% of a corresponding value. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

In some embodiments well-known structures and devices may be described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units, and/or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such block, unit, and/or module are/is physically implemented by a logic circuit, an individual component, a microprocessor, a hard wire circuit, a memory element, a line connection, and other electronic circuits. This may be formed using a semiconductor-based manufacturing technique or other manufacturing techniques. The block, unit, and/or module implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform various functions discussed herein, optionally may be driven by firmware and/or software. In addition, each block, unit, and/or module may be implemented by dedicated hardware, or a combination of dedicated hardware that performs some functions and a processor (for example, one or more programmed microprocessors and related circuits) that performs a function different from those of the dedicated hardware. In addition, in some embodiments, the block, unit, and/or module may be physically separated into two or more interact individual blocks, units, and/or modules without departing from the scope of the present disclosure. In addition, in some embodiments, the block, unit and/or module may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

FIG. 1 is a plan view illustrating a configuration of a display device according to one or more embodiments of the present disclosure. FIG. 2 is a side cross-sectional view illustrating the display device of FIG. 1 in detail.

Referring to FIGS. 1 and 2, a display device 10 according to one or more embodiments may be applied to portable electronic devices, such as tablet personal computer (PC), portable multimedia player (PMP), navigation, ultra mobile PC (UMPC), e-book, e-notebook, mobile phone, smart phone, mobile communication terminal, etc. For example, the display device 10 may be applied to a display of a television, a laptop computer, a monitor, a billboard, or the Internet of Things (IOT).

The display device 10 according to one or more embodiments may be variously classified according to a display method. For example, the display device 10 may be classified into an organic light-emitting diode display (OLED), an inorganic light-emitting display (EL), a quantum dot light-emitting display (QED), a micro-LED display, a nano-LED display, a plasma display panel (PDP), a field emission display (FED), a liquid crystal display (LCD), an electrophoretic display (EPD), etc. Hereinafter, an organic light-emitting diode display (OLED) will be described as an example of the display device 10 according to one or more embodiments, and unless a special distinction is required, the organic light-emitting diode display (OLED) may be abbreviated as the display device 10. The display device 10 is not limited to the organic light-emitting diode display (OLED), and other display devices listed above or known in the art may be applied within the scope of sharing technical spirits.

The display device 10 according to one or more embodiments may have a rectangular shape, a square shape, a circular shape, an elliptical shape, or a quadrate shape in plan view. For example, when the display device 10 is a mobile device, such as a tablet PC, the display device 10 may have a rectangular shape with a long side positioned in a horizontal direction. However, the present disclosure is not limited thereto, and the long side of the display device 10 may be positioned in a vertical direction, and the display device 10 may be rotatably installed, such that the long side of the display device 10 may also be variably positioned in the horizontal or vertical direction.

The display device 10 includes a display panel 100, a display-driving circuit 200, and a touch-sensing module including a touch sensor TSU and a touch-driving circuit 400.

For example, the display panel 100 of the display device 10 includes a display DU for displaying an image, and the touch sensor TSU for sensing a touch of a body portion, such as a finger and/or an electronic pen, is located on the display panel 100. A plurality of pixels SP are formed in a preset arrangement in the display DU of the display panel 100, and an image is displayed by the plurality of pixels SP.

The touch sensor TSU may be mounted on a front surface of the display panel 100 or may be formed integrally with the display panel 100. The touch sensor TSU may include a plurality of touch electrodes to sense a user's touch in a capacitive manner using the touch electrodes.

The display-driving circuit 200 may output data voltages and pixel-driving control signals for driving the plurality of pixels SP arranged in the display DU. The display-driving circuit 200 may supply data voltages to data lines to which the plurality of pixels SP are connected. The display-driving circuit 200 may supply a power voltage to a power line, supply gate control signals to a gate driver 210, and supply the pixel-driving control signals to the plurality of pixels SP.

The display-driving circuit 200 delays at least one frame period of the still image display period from one frame period of the video display period and adjusts the image display timing of the next frame based on changes in voltage magnitude or the amount of current supplied to the plurality of pixels. To this end, the display-driving circuit 200 detects still image or video characteristics of image data input from the outside. Then, the maximum grayscale value (or the maximum luminance value) of the image data for at least one frame is detected, and the grayscale values or luminance values of the image data of one or more frames (e.g., every at least one frame) are compared and analyzed to determine the load of all pixels SP of the one or more frames.

In addition, the display-driving circuit 200 analyzes the grayscale value or luminance value of image data RGB Data of the one or more frames to detect current amount data or voltage magnitude data flowing through the pixels SP, and detects the changes of current amount and voltage magnitude value of a first power line electrically connected to at least one pixel SP, in real time.

The display-driving circuit 200 supplies an image data voltage to each of the pixels SP, and controls the driving timing of the pixels SP, so that an image is displayed for every frame during the image display period of video characteristics. On the other hand, the display-driving circuit 200 delays the image display period of the current frame during the image display period of still image characteristics, and controls the next frame image display timing and image display period according to changes in the current amount or voltage magnitude of the pixels SP displaying the image.

The touch-driving circuit 400 may be electrically connected to the touch sensor TSU. The touch-driving circuit 400 may supply touch-driving signals to the plurality of touch electrodes arranged in the touch sensor TSU, and may sense an amount of change of capacitance between the plurality of touch electrodes. The touch-driving circuit 400 may calculate whether a user's touch input is made, and may calculate touch coordinates, based on the amount of change of capacitance between the plurality of touch electrodes.

Meanwhile, the display-driving circuit 200 may operate as a main processor, or may be formed integrally with the main processor. Accordingly, the display-driving circuit 200 may control the overall function of the display device 10. For example, the display-driving circuit 200 may receive touch data from the touch-driving circuit 400, may determine user's touch coordinates, and may generate digital video data according to the touch coordinates. In addition, the display-driving circuit 200 may execute an application indicated by an icon displayed on the user's touch coordinates. As still another example, the display-driving circuit 200 may receive coordinate data from an electronic pen or the like, may determine touch coordinates of the electronic pen, and may generate digital video data according to the touch coordinates, or also may execute an application indicated by an icon displayed on the touch coordinates of the electronic pen.

Referring to FIG. 2, the display panel 100 may be divided into a main area MA and a sub-area SBA. The main area MA may include a display area DA having pixels SP displaying an image, and a non-display area NDA located around the display area DA. In the display area DA, light may be emitted from light-emitting areas or from opening areas of each pixel SP to display an image. To this end, the pixels SP of the display area DA may include a pixel circuit including switching elements (e.g., thin film transistors), a pixel-defining layer defining the light-emitting area or the opening area, and a self-light-emitting element.

The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. In one or more embodiments, the non-display area NDA may include a gate driver for supplying gate signals to the gate lines, and fan-out lines connecting the display-driving circuit 200 and the display area DA.

The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that may be bent, folded, rolled, or the like. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include the display-driving circuit 200 and a pad portion connected to a circuit board 300. Optionally, the sub-area SBA may be omitted, and the display-driving circuit 200 and the pad portion may be located in the non-display area NDA.

At least one display-driving circuit 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic-bonding method. For example, the display-driving circuit 200 may be located in a sub-area SBA, and may overlap the main area MA in the thickness direction (Z-axis direction) by bending of the sub-area SBA. As another example, the display-driving circuit 200 may be mounted on the circuit board 300.

The circuit board 300 may be electrically connected to the pad portion of the display panel 100 by an anisotropic conductive film (ACF). To this end, lead lines of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible film, such as a flexible printed circuit board, a printed circuit board, or a chip on film.

The substrate SUB of the display panel 100 may be a base substrate or a base member. The substrate SUB may be a flexible substrate that may be bent, folded, rolled, or the like. For example, the substrate SUB may include a glass material or a metal material, but is not limited thereto. As another example, the substrate SUB may include a polymer resin, such as polyimide (PI).

A thin film transistor layer TFTL may be located on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting the pixel circuit of the pixels SP. The thin film transistor layer TFTL may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display-driving circuit 200 and the data lines, and lead lines connecting the display-driving circuit 200 and the pad portion. When the gate driver 210 is formed on one side of the non-display area NDA of the display panel 100, the gate driver 210 may also include the thin film transistors.

The thin film transistor layer TFTL may be located in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, the gate lines, the data lines, and the power lines of each of the pixels of the thin film transistor layer TFTL may be located in the display area DA. The gate control lines and the fan-out lines of the thin film transistor layer TFTL may be located in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be located in the sub-area SBA.

A light-emitting element layer EML may be located on the thin film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements, in which a first electrode, a light-emitting layer, and a second electrode are sequentially stacked to emit light, and also may include a pixel-defining film for defining pixels. The plurality of light-emitting elements of the light-emitting element layer EML may be located in the display area DA.

An encapsulation layer TFEL may cover an upper surface and side surfaces of the light-emitting element layer EML, and may protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EML.

A touch sensor TSU may be located on the encapsulation layer TFEL. The touch sensor TSU may include a plurality of touch electrodes for sensing a user's touch in a capacitance type, and touch lines connecting the plurality of touch electrodes and the touch-driving circuit 400. For example, the touch sensor TSU may sense a user's touch in a self-capacitance method or a mutual capacitance method.

As another example, the touch sensor TSU may be located on a separate substrate located on the display DU. In this case, the substrate supporting the touch sensor TSU may be a base member that encapsulates the display DU.

The plurality of touch electrodes included in the touch sensor TSU may be located in a touch-sensing area overlapping the display area DA. The touch lines of the touch sensor TSU may be located in a touch peripheral area overlapping the non-display area NDA.

The touch-driving circuit 400 may be located on a separate circuit board 300. The touch-driving circuit 400 may be formed as an integrated circuit (IC). As described above, the touch-driving circuit 400 applies the touch-driving signals to the touch electrodes of the touch sensor TSU. In addition, the touch-driving circuit 400 measures an amount of change of charge of a mutual capacitance of each of the touch nodes formed at intersection areas of the touch electrodes. For example, the touch-driving circuit 400 measures a change of capacitance of the touch nodes according to a change of the magnitude of a voltage or an amount of current of a touch-sensing signal received through the touch electrodes. In this way, the touch-driving circuit 400 may determine whether or not a user's touch is made, whether or not a user's approach is made, and the like, according to the amount of change of charge of the mutual capacitance of each of the touch nodes. Here, the touch-driving signal may be a pulse signal having a frequency (e.g., predetermined frequency). The touch-driving circuit 400 calculates whether a touch input of a user's body part, such as a finger, is made, and touch coordinates based on the amount of change of capacitance between the plurality of touch electrodes.

For example, the touch-driving circuit 400 may detect whether the user's touch is made by sequentially supplying the touch-driving signals to the plurality of touch electrodes arranged across each other in the touch sensor TSU, and sequentially measuring the amount of change of charge of the capacitance of each of the touch nodes formed by intersection of the touch electrodes.

FIG. 3 is a layout view schematically illustrating an example of a display panel according to one or more embodiments. For example, FIG. 3 is a layout view illustrating a display area DA and a non-display area NDA of the display DU before the touch sensor TSU is formed.

The display area DA, which is an area displaying an image, may be defined as a central area of the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. Each of the plurality of pixels SP may be defined as a minimum unit for outputting light.

The plurality of gate lines GL may supply the scan signals or the gate signals received from the gate driver 210 to the plurality of pixels SP. The plurality of gate lines GL may extend in an X-axis direction, and may be spaced apart from each other in a Y-axis direction intersecting the X-axis direction.

The plurality of data lines DL may supply the data voltage received from the display-driving circuit 200 to the plurality of pixels SP. The plurality of data lines DL may extend in the Y-axis direction, and may be spaced apart from each other in the X-axis direction.

In addition, a plurality of control lines, such as a plurality of light emission control lines and initialization lines, may be formed in the display area DA to supply pixel-driving control signals, such as emission control signals or initialization signals, received from the display-driving circuit 200 to the plurality of pixels SP. In the display area DA, the control lines may extend in the Y-axis direction, and may be spaced apart from each other in the X-axis direction.

Meanwhile, the plurality of power lines VL may supply high-potential and low-potential power voltages received from the display-driving circuit 200 to the plurality of pixels SP. Here, the power voltage may be at least one of a high-potential and low-potential driving voltage, an initialization voltage, and a reference voltage. The plurality of power lines VL may extend in the Y-axis direction, and may be spaced apart from each other in the X-axis direction.

The non-display area NDA may surround the display area DA (e.g., in plan view). The non-display area NDA may include a gate driver 210, fan-out lines FOL, and gate control lines GCL. The gate driver 210 may generate a plurality of gate signals based on the gate control signals, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

The fan-out lines FOL may extend from the display-driving circuit 200 to the display area DA. The fan-out lines FOL may supply the data voltage received from the display-driving circuit 200 to the plurality of data lines DL.

The gate control line GCL may extend from the display-driving circuit 200 to the gate driver 210. The gate control line GCL may supply the gate control signal received from the display-driving circuit 200 to the gate driver 210.

The display-driving circuit 200 may supply the data voltage to the data lines DL through the fan-out lines FOL. The data voltage may be supplied to the plurality of pixels SP, and may determine luminance of the plurality of pixels SP. The display-driving circuit 200 may supply the gate control signals to the gate driver 210 through the gate control line GCL. In addition, the display-driving circuit 200 may supply the pixel-driving control signals to each control line through separate fan-out lines connected to the control lines of the display area DA.

FIG. 4 is an equivalent circuit diagram of a first example of a pixel of the display panel illustrated in FIG. 3.

Referring to FIG. 4, each of the pixels SP may include three transistors DTR, STR1, STR2 and one storage capacitor CST for light emission of the light-emitting elements LE. The driving transistor DTR adjusts the amount of current flowing from a first power line ELVDL to which the first power voltage is supplied to the light-emitting element LE according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DTR may be connected to a first electrode of a first transistor ST1, a first electrode thereof may be connected to the first power line ELVDL to which the first power voltage is applied, and the second electrode thereof may be connected to a first electrode of the light-emitting element LE.

The first transistor STR1 is turned on by the scan signal of a gate line GL to supply a data voltage of the data line DL to the gate electrode of the driving transistor DTR. The gate electrode of the first transistor STR1 may be connected to the gate line GL, the first electrode thereof may be connected to the data line DL, and the second electrode thereof may be connected to the gate electrode of the driving transistor DTR.

The second transistor STR2 is turned on by the sensing signal of a sensing signal line SSL to connect an initialization voltage line VIL to the second electrode of the driving transistor DTR. The gate electrode of the second transistor ST2 may be connected to the sensing signal line SSL, the first electrode thereof may be connected to the initialization voltage line VIL, and the second electrode thereof may be connected to the second electrode of the driving transistor DTR.

In one or more embodiments, the first electrode of each of the first and second transistors STR1 and STR2 may be a source electrode, and the second electrode thereof may be a drain electrode, but the present disclosure is not limited thereto, and may be vice versa.

The storage capacitor CST is formed between the gate electrode and the second electrode of the driving transistor DTR. The storage capacitor CST stores a difference voltage between a gate voltage and a source voltage or a drain voltage of the driving transistor DTR.

The driving transistor DTR, the first transistor STR1, and the second transistor STR2 may be formed as thin film transistors. Further, in the description of FIG. 4, it is assumed that the driving transistor DTR, the first switching transistor STR1, and the second transistor STR2 are N-type metal oxide semiconductor field effect transistors (MOSFETs), but the present disclosure is not limited thereto. For example, the driving transistor DTR, the first transistor STR1, and the second transistor STR2 may be formed as P-type MOSFETs, or one or more of the driving transistor DTR, the first transistor STR1, or the second transistor STR2 may be formed as N-type MOSFETs, while one or more others may be formed as P-type MOSFETs.

FIG. 5 is an equivalent circuit diagram of a second example of a pixel of the display panel illustrated in FIG. 3.

Referring to FIG. 5, each pixel SP may include a storage capacitor CST, and one driving transistor DTR and a plurality of switching transistors for light emission of the light-emitting elements LE. In this case, the plurality of switching transistors may include first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6.

The driving transistor DTR includes a gate electrode, a first electrode, and a second electrode. The driving transistor DTR controls the amount of a drain-source current (hereinafter, referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

The storage capacitor CST is formed between the first electrode of the driving transistor DTR and the first power line ELVDL. For example, the first electrode of the storage capacitor CST may be connected to the first power line ELVDL, and the second electrode thereof may be connected to the first electrode of the driving transistor DTR.

When the first electrode of each of the driving transistor DTR and the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 is a source electrode, the second electrode thereof may be a drain electrode. Alternatively, when the first electrode of each of the driving transistor DTR and the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 is a drain electrode, the second electrode thereof may be a source electrode.

The driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 may be configured as P-type metal oxide semiconductor field effect transistors (MOSFETs), and the first transistor STR1 and the third transistor STR3 may be configured as N-type MOSFETs. Alternatively, the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6, and the driving transistor DTR may be formed of a P-type metal oxide semiconductor field effect transistor (MOSFET). However, one or more of of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR being formed as the P-type MOSFETs and the remaining one or more thereof being formed as the N-type MOSFETs are not limiting. For example, it should be noted that the equivalent circuit diagram of the pixel is not limited to that shown in FIGS. 4 and 5. The equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure may be formed with another known circuit structure that can be employed by a person skilled in the art in addition to the embodiments shown in FIGS. 4 and 5.

FIG. 6 is a detailed configuration block diagram of the display-driving circuit illustrated in FIGS. 1 to 3.

Referring to FIG. 6, the display-driving circuit 200 according to one or more embodiments includes a maximum grayscale detector (e.g., maximum grayscale detection unit) 201, a load detector (e.g., load detection unit) 202, an image analyzer (e.g., image analysis unit) 203, an image display current amount analyzer (e.g., image display current amount analysis unit) 221, an image display voltage detector (e.g., image display voltage detection unit) 231, an image display determiner (e.g., image display determination unit) 232, and a panel driver (e.g., panel-driving control unit) 233.

The maximum grayscale detector 201 sorts image data RGB Data input from the outside in units of at least one frame, and detects the maximum grayscale value (or the maximum luminance value) of image data of the one or more frames by comparing and analyzing the grayscale values (or the maximum luminance values) of image data of the one or more frames.

For example, the maximum grayscale detector 201 sequentially compares and analyzes grayscale values (or luminance values) of pixels SP included in the image data of the one or more frames, and detects a maximum grayscale value (or a maximum luminance value) of each frame. Then, the maximum grayscale detector 201 transmits maximum grayscale data M_Data (or maximum luminance data) including the detected maximum grayscale value to the image display current amount analyzer 221.

The load detector 202 compares and analyzes grayscale values or luminance values of the image data of the one or more frames to detect the load of the entire pixels SP of the one or more frames.

For example, the load detector 202 detects and analyzes a maximum grayscale value, a maximum luminance value, an average grayscale value, or an average luminance value from the grayscale values (or the luminance values) of the pixels PX included in the image data of the one or more frames. Then, the load detector 202 calculates or detects the load on at least one pixel SP or all pixels SP based on the maximum grayscale value, the maximum luminance value, the average grayscale value, or the average luminance value of the image data of the one or more frames. The load detector 202 may calculate the load using a preset load detection equation, or may detect the load from a database pre-stored in a memory, such as a lookup table using experimental values. The load detector 202 transmits load data L_Data including the load calculation result value to the image display current amount analyzer 221. The load detector 202 may supply the detected maximum grayscale value, maximum luminance value, average grayscale value, or average luminance value to the image analyzer 203, the image display current amount analyzer 221, the image display determiner 232.

The image analyzer 203 detect still image or moving image characteristics of the image data RGB Data input from the outside based on the comparative analysis result of the maximum grayscale value, the maximum luminance value, the average grayscale value, or the average luminance value of the image data of the one or more frames.

For example, the image analyzer 203 may respectively compare the maximum grayscale value, maximum luminance value, average grayscale value, or average luminance value for the image data RGB Data of previous frames to the maximum grayscale value, maximum luminance value, average grayscale value, or average luminance value for the image data RGB Data of the current frame, and may analyze the difference value to detect the still image or video characteristics of the current frame image data RGB Data. For example, the image analyzer 203 calculates the difference value between the maximum grayscale value, maximum luminance value, average grayscale value, or average luminance value of the current frame image compared to those of the previous frame, and compares them with a preset reference value. Then, if the calculated difference value is detected to be greater than the preset reference value, the image data RGB Data of the current frame may be determined to be video data. On the other hand, if the calculated difference value is detected to be less than the preset reference value, the image data RGB Data of the current frame may be determined to be still image data. In addition, the image analyzer 203 may determine frame image data as screen transition image data at a point when the calculated difference value detected to be less than a preset reference value becomes larger than a preset reference value. The image analyzer 203 sends a detection signal for still image or video characteristics, which is detected and determined for each frame period basis, that is, sends a still image or video detection signal MSS to the image display determiner 232 and the panel driver 233 and/or the like.

The image display current amount analyzer 221 detects a current amount data I_Data or voltage magnitude data corresponding to at least one pixel SP based on the maximum grayscale value, maximum luminance value, average grayscale value, or average luminance value of image data RGB Data of the one or more frames, the load on all pixels SP, the magnitude of the data voltage applied to at least one pixel SP, and at least one grayscale value, voltage value, or luminance value among the grayscale value for at least one pixel SP. For example, the image display current amount analyzer 221 may detect the amount of current or the voltage magnitude applied to the light-emitting element LE for at least one pixel SP according to the maximum grayscale value or the maximum luminance value of the image data RGB Data.

Information on the amount of current or the magnitude of voltage applied to the light-emitting element LE compared to the maximum grayscale value or the maximum luminance value detected by the maximum grayscale detector 201 and/or the like can be preset and stored in a memory and/or the like as experimental values for each characteristic of the display panel 100.

The image display current amount analyzer 221 may detect the amount of current or magnitude of voltage applied to the light-emitting element LE for at least one pixel SP according to the average grayscale value or average luminance value of the image data RGB Data. The image display current amount analyzer 221 transmits the current amount data I_Data or voltage magnitude data of the one or more frames detected in real time to the image display determiner 232.

The image display voltage detector 231 detects changes in the voltage magnitude value and in the amount of current of the first power line ELVDL electrically connected to all pixels SP or at least one pixel SP in the display area DA for the one or more frame periods in real time.

For example, the image display voltage detector 231 detects the change of the amount of current and the voltage magnitude of the first power line ELVDL of the one or more frame periods at one terminal of the first power line ELVDL commonly connected to all pixels SP in real time. In contrast, the image display voltage detector 231 may also detect the change of the amount of current and the voltage magnitude value of the first power line ELVDL at the middle portion of the first power line ELVDL connected to at least one pixel SP among all pixels SP in real time. The image display voltage detector 231 transmits the voltage magnitude value and the current amount data PV_Data of the first power line ELVDL detected for the one or more frame periods to the image display determiner 232.

The image display determiner 232 sets a still image display mode or a video display mode in response to a still image or video detection signal MSS, and when setting the still image display mode, may delay the image display period of the current frame and may control the image display timing and image display period of the next frame according to changes in the amount of current or voltage magnitude of the pixels displaying an image.

For example, the image display determiner 232 may receive the still image or video detection signal MSS input according to the determination of the image analyzer 203, and may set the still image or video display mode. The image display determiner 232 may supply a video display mode signal DM to the panel driver 233 during the video display mode setting period.

When the still image detection signal MSS according to the still image detection result is input from the image analyzer 203, the image display determiner 232 is set in a still image display mode, and an output of the video display mode signal DM is stopped.

When setting the still image display mode, the image display determiner 232 sets the current amount of the current amount data I_Data of the one or more frames received in at least one frame period from the image display current amount analyzer 221 to a current value of the reference current amount. In addition, the voltage magnitude value of the voltage magnitude data of the one or more frames received from the image display current amount analyzer 221 is set to the reference voltage magnitude value.

The image display determiner 232 compares the amount of current of the first power line ELVDL, which is received in at least one frame period through the image display voltage detector 231, with the reference current amount. An image display control signal SM of the next frame may be supplied to the panel driver 233 when the amount of current of the first power line ELVDL becomes equal to or less than the reference current amount.

Alternatively, the image display determiner 232 may compare the voltage magnitude value of the first power line ELVDL, which is received in at least one frame period through the image display voltage detector 231, with the reference voltage magnitude value. The image display control signal SM of the next frame may be supplied to the panel driver 233 when the voltage magnitude value of the first power line ELVDL becomes equal to or less than the reference voltage magnitude value.

When the video display mode signal DM is received from the image display determiner 232, the panel driver 233 may sequentially supply data voltages to the pixels SP in each frame period, and may supply the pixel-driving control signals to the gate driver 210 and to each of the pixels SP to control an image to be displayed for each frame period.

When setting the still image display mode, the panel driver 233 may stop outputting pixel-driving control signals, so that the image display state of the current frame may be maintained, and so that the image display period of the current frame may be delayed.

When the panel driver 233 receives the image display control signal SM from the image display determiner 232, the panel driver 233 may supply data voltages according to the next frame image data to the pixels SP in response to the image display control signal SM. Furthermore, the pixel-driving control signals may be supplied to the gate driver 210 and to each of the pixels SP to control the image of the next frame to be displayed.

FIG. 7 is a timing diagram illustrating changes in waveforms of pixel-driving control signals and driving voltage of a light-emitting element according to one or more embodiments.

Referring to FIG. 7, the image display determiner 232 of the display-driving circuit 200 supplies the video display mode signal DM to the panel driver 233 when setting the video display mode.

The panel driver 233 may sequentially supply data voltages to the pixels SP in each frame period in response to the video detection signal MSS or video display mode signal DM, and may sequentially supply scan signal and sensing signals to the gate line GL and the sensing signal line SSL to control images to be displayed for each frame period.

The panel driver 233 may divide each frame period into a data-voltage-charging period ChT and a pixel emission period LhT, and may drive each of the pixels SP.

The panel driver 233 may allow pixel-driving control signals, such as scan signal and sensing signal, to be supplied to the pixels SP in the data-voltage-charging period ChT to charge the data voltage to each of the pixels SP. In the data-voltage-charging period ChT among each frame period, the luminance niT and the brightness of the pixels SP may be reduced, and a voltage magnitude value SIR and the current amount of the first power line ELVDL connected to each of the pixels SP may be raised or increased.

During the pixel emission period LhT among each frame period, the light-emitting element LE formed in each of the pixels SP may emit light to display an image. The luminance niT and brightness of the pixels SP may be maintained high and large, and the voltage magnitude value SIR and current amount of the first power line ELVDL connected to each of the pixels SP may gradually decrease or be lowered.

When in still image display mode, the panel driver 233 may stop the output of the pixel-driving control signals, such as a scan signal or a sensing signal, to maintain the image display state of the current frame 1Frame, and to delay the image display period of the current frame 1Frame.

In the still image display mode, the image display determiner 232 may compare the voltage magnitude value SIR of the first power line ELVDL, which is received in at least one frame period through the image display voltage detector 231, with a reference voltage magnitude value ReV. In addition, at a point RTI (e.g., n-Frame period) in which the voltage magnitude value SIR of the first power line ELVDL becomes equal to the reference voltage magnitude value ReV, or becomes less than the reference voltage magnitude, the image display control signal SM of the next frame nFrame may be supplied to the panel driver