(2) may include a resistor 448 coupled between the nodes 444 and 430.

To further reduce the noise and power consumption as compared to the embodiment of the circuit 200 of FIG. 2, the gain compensation stage (gain compensation circuit 202) can be moved further in the signal chain as shown by including one or more circuits between the single-stage inverter-based amplifier (integrator) 140 and the gain compensation circuit 202. This separation allows noise and distortion from the gain compensation circuit 202 may be suppressed by gains from one or more preceding stages (such as the first resonator 402(1)). Additionally, by moving the gain compensation circuit 202 to a later stage, any additional delay added by the gain compensating circuit 202 does not impact the first and second order paths of the CTDSM and can be implemented using a multi-stage inverter-based configuration, such as the three-stage configuration shown in FIG. 1A. The capacitor 234 used in the gain compensation circuit 202 may be tuned together with the capacitance C₂₂₂of the first integrating capacitor 222 to minimize the process variation.

In the illustrated embodiment, the gain compensation circuit 202 is moved after the first resonator 402(1). Since there is no additional gain in the first-order and second-order paths, the feed-forward coefficients of the CTDSM may be tuned to restore the desired noise transfer function, as shown with respect to Equations 2 and 3 above.

FIG. 5 depicts a graph 500 of the output spectrum of a fifth order CTSDM with and without gain compensation, in accordance with certain embodiments. In this example, a CTSDM may be designed with a bandwidth of 120 MHz and an over-sampling ratio (OSR) of 18. As shown, without gain compensation, quantization noise suppression around DC is limited. When the gain compensation circuit 202 is included further in the signal chain, the overall SQNR in 120 MHz bandwidth is improved by 2.5 dB, which is significant in low OSR designs. By including the gain compensation circuit 202 at a stage of the CTDSM that is after one of the resonators 402, the distortion components around DC are also improved. In the embodiment shown in FIG. 4, the power consumed by the gain compensation circuit 202 may be less than ten percent (10%) of the power consumed by the single-stage inverter-based amplifier (integrator) 140.

FIG. 6 depicts an embodiment of a wideband CTSDM 600 including a fifth order loop filter that uses a cascaded-integrated-feedforward (CIFF) architecture with a cascade of an integrator (single-stage inverter-based amplifier 140), two resonators 402(1) and 402(2), and a gain compensation circuit 202, in accordance with certain embodiments. The CTSDM 600 may include all the elements of the circuit 400 of FIG. 4.

In the illustrated embodiment, the amplifier (integrator) 140 includes all the elements of the amplifier 140 in FIG. 4 and includes a capacitor 602 including a first terminal to receive a signal and a second terminal coupled to the node 102 at the input of the amplifier circuit 404. The capacitor 222 is depicted as a variable capacitor, which may be implemented using a capacitor bank including a fixed capacitor and a number of capacitors that may be selectively connected in parallel with the fixed capacitor. The number of capacitors may vary based on a desired variation in the capacitance. In one or more embodiments, the capacitor bank may be a six-bit programmable capacitor bank.

The first resonator 402(1) includes all the elements of the first resonator 402(1) in FIG. 4 and includes capacitors 604 and 606. The capacitor 604 may include a first terminal to receive a signal and includes a second terminal coupled to the node 408. The capacitor 606 includes a first terminal to receive a signal and a second terminal coupled to the node 418. The capacitors 414 and 424 are depicted as variable capacitors, each of which may be implemented using a capacitor bank including a fixed capacitor and a number of capacitors that may be selectively connected in parallel with the fixed capacitor. The number of capacitors may vary based on a desired variation in the capacitance. In one or more embodiments, the capacitor banks may be six-bit programmable capacitor banks.

The gain compensation circuit 202 may include all the elements of the gain compensation circuit 202 in FIG. 4. In one or more embodiments, the capacitor 234 may be implemented as a variable capacitance. In one or more embodiments, the capacitor 234 may include a capacitor bank including a fixed capacitor and a number of capacitors that may be selectively connected in parallel with the fixed capacitor. The number of capacitors may vary based on a desired variation in the capacitance. In one or more embodiments, the capacitor bank may be a six-bit programmable capacitor bank. In one or more embodiments, the capacitor bank of the gain compensation circuit 202 and the capacitor bank of the single-stage inverter-based amplifier (integrator) 140 may be programmed to minimize the process variation, for example, by altering the impact of one or more parameters caused by process variation.

The second resonator 402(2) may include all the elements of the resonator 402(2) in FIG. 4 and may include capacitors 608 and 610. The capacitor 608 may include a first terminal to receive a signal and includes a second terminal coupled to the node 434. The capacitor 610 may include a first terminal to receive a signal and a second terminal coupled to the node 440. The capacitors 436 and 424 are depicted as variable capacitors, each of which may be implemented using a capacitor bank including a fixed capacitor and a number of capacitors that may be selectively connected in parallel with the fixed capacitor. The number of capacitors may vary based on a desired variation in the capacitance. In one or more embodiments, the capacitor banks may be six-bit programmable capacitor banks.

The CTSDM 600 may include a summing element 612 coupled to the nodes 114, 412, 236, 434, and 444 to receive voltage V₁, V₂, V₃, V₄, and V₅, respectively. The summing element 612 may include an amplifier circuit 616 including an input coupled to a node 615 and an output coupled to a node 620. The summing element 612 may include a first resistor 614(1) coupled between the nodes 444 and 615, a second resistor 614(2) coupled between the nodes 434 and 615, a third resistor 614(3) coupled between the nodes 236 and 615, a further resistor 614(4) coupled between the nodes 412 and 615, and a fifth resistor 614(5) coupled between the nodes 114 and 615. The summing element 612 may include a resistor 618 coupled between the nodes 615 and 620.

The CTSDM 600 may include a quantizer 624 including an input coupled to the node 620, a second input to receive a sample frequency signal f_s, and an output. In one or more embodiments, the quantizer 624 may be a successive approximation register (SAR) configured to produce digital codes that may be provided to the shifter 628.

The CTSDM 600 may include a shifter circuit 628 including a first input coupled to the output of the quantizer 624, a second input coupled to a pseudo-random binary sequence (PRBS) 630, and an output coupled to an input of a digital-to-analog converter (DAC) 632, which has an output coupled to the node 102. In one or more embodiments, the shifter circuit 628 may be implemented as a barrel shifter, which may be configured to shift the digital output of the quantizer by a specified number of bits. In one or more embodiments, the shifter circuit 628 may be configured to receive a two-bit digital input from the quantizer 624 and may produce a three-bit digital output, which may be thermometer coded and which may be provided to the input of the DAC 632.

In one or more embodiments, the CTDSM 600 integrates a fifth-order noise transfer function (NTF) that may achieve high linearity and improved SQNR with reduced power consumption. To mitigate the effect of quantizer offset, the quantizer 624 operates while the DAC mismatch is calibrated digitally in the background. In one or more embodiments, the sampling frequency may be approximately 4 GHz.

To further improve the energy efficiency, the first integrator of the CTDSM 600 is implemented using a single-inverter amplifier 140, while its finite gain is compensated further in the signal chain by the gain compensation circuit 202 to restore the noise transfer function.

In one or more embodiments, the gain compensation circuit 202 may provide pole-zero compensation, which may compensate for the finite gain of the single-stage inverter-based amplifier 140 and which may restore the zero of the noise transfer function at DC. To compensate for the process spread of resistor-capacitor (RC) time constants, the capacitors 222, 414, 424, 234, 436, and 446 in the CTDSM 600 are implemented using capacitor banks consisting of a fixed part and a multi-bit programmable part. In one or more embodiments, the multi-bit programmable part may be a six-bit programmable part.

The CTDSM 600 uses a CIFF architecture with the summing amplifier 612 through resistors 614 for high linearity. The output of the CTDSM 600 may be provided to a node 620, which may be coupled to an input of the quantizer 624. The DAC 632 may be implemented as a dual return-to-open DAC to mitigate inter-symbol interference (ISI) errors while the DAC mismatch is randomized and then calibrated digitally using the PRBS 630 and the shifter 628.

Thus, the CTDSM 600 may include a power-efficient single-stage inverter-based amplifier 140 where the same bias current determines both the linearity and thermal noise level. The limited DC gain of the amplifier 140 may limit the quantization noise suppression at DC, but the gain compensation circuit 202 (added after the first resonator 402(1) may restore the noise transfer function. The gain compensation circuit 202 may utilize much lower power as both the thermal noise and distortion added by the gain compensation circuit 202 is suppressed by the gain of preceding stages.

FIG. 7 depicts a flow diagram of a method 700 of modulating a received signal, in accordance with certain embodiments. At 702, the method 700 may include receiving a signal at an input of a continuous-time delta-sigma modulator (CTDSM). In one or more embodiment, the CTDSM may have a selected order. In one particular embodiment, the CTDSM may be a fifth-order CTDSM.

At 704, the method 700 may include integrating the signal using an integrator circuit including a single inverter amplifier to produce an integrated output.

At 706, the method 700 may include shifting noise of the integrated output signal to a relatively higher frequency using a first resonator circuit of the CTDSM to produce a shifted signal. In one or more embodiments, the noise of the scaled output signal may be shifted noise to a second relatively higher frequency using a second resonator circuit of the CTDSM.

At 708, the method 700 may include scaling the shifted signal using a gain compensation circuit of the CTDSM that is configured to compensate a transfer function of the integrator circuit to produce a scaled output signal.

In conjunction with the circuits and methods described above with respect to FIGS. 1-7, a CTDSM is described that may include a single-stage inverter-based amplifier (integrator) 140, one or more resonators 402, and a gain compensation circuit 202 configured to implement a fifth-order noise transfer function having improved performance and reduced power consumption. The disclosure may be further understood in light of the following examples.

Example 1: A modulator circuit may include an integrator circuit including: a first amplifier with limited gain and including an input to receive a signal and including an output to provide an inverted signal; and a capacitor including a first terminal coupled to the input and a second terminal coupled to the output; and may include a gain compensation circuit including: a second inverter amplifier including a gain input coupled to the output of the first amplifier and including a gain output; a first resistor including a first terminal coupled to the gain output and including a second terminal; a second capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to the gain input; and where the integrator circuit has a finite direct current (DC) gain and the gain compensation circuit is configured to compensate for the finite DC gain to provide a selected transfer function from the input of the first amplifier to the gain output.

Example 2: The modulator circuit of Example 1, where the capacitor and the second capacitor are programmable; and a first capacitance of the capacitor and a second capacitance of the second capacitor are configurable to reduce one or more parameters caused by process variation.

Example 3: The modulator circuit of any of Examples 1 or 2, further including a resonator circuit coupled between the output of the first amplifier and the gain input of the gain compensation circuit.

Example 4: The modulator circuit of Example 3, where a signal gain produced by the resonator circuit suppresses noise and distortion of the gain compensation circuit.

Example 5: The modulator circuit of Example 3, where the resonator circuit includes: a second resistor including a first terminal coupled to the output of the first amplifier and including a second terminal; a third inverter amplifier including an input coupled to the second terminal of the second resistor and including an output; a third resistor including a first terminal coupled to the second terminal of the second resistor and a second terminal coupled to the output of the third inverter amplifier; a fourth resistor including a first terminal coupled to the output of the third inverter amplifier and including a second terminal; a fourth inverter amplifier including an input coupled to the second terminal of the fourth resistor and including an output coupled to the gain input; a fifth resistor including a first terminal coupled to the second terminal of the fourth resistor and including a second terminal coupled to the output of the fourth inverter amplifier; and a sixth resistor including a first terminal coupled to the second terminal of the second resistor and including a second terminal coupled to the output of the fourth inverter amplifier.