100 to bypass the terminal L2P table (e.g., a third-level L2P table), or a pointer to the terminal L2P table.

Although the discussion herein focuses on a three-level L2P table architecture, a similar approach may be used in other examples of multi-level L2P table architectures, such as a two-level L2P architecture, a four-level L2P architecture, etc., in which the terminal (e.g., last) L2P table may be eliminated (e.g., discarded, not generated, bypassed) if the data pointed to by the table is sequentially stored.

FIG. 2 illustrates an example of NAND circuit 200 that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples of the present disclosure. NAND circuit 200 may be an example of a portion of a memory device, such as memory device 100. Although some elements included in FIG. 2 are labeled with reference numbers, other corresponding elements are not labeled, though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

NAND circuit 200 includes multiple Flash memory cells 205 (which may be, for example, Flash memory cells such as described with reference to FIG. 1) connected in a NAND configuration. In a NAND memory configuration (referred to as NAND memory), multiple Flash memory cells 205 are connected in series with each other to form strings 210 of memory cells 205, in which the drain of each Flash memory cell 205 in the string 210 is coupled with the source of another Flash memory cell 205 in the string. In some examples, Flash memory cells that are connected in a NAND configuration to form a NAND memory may be referred to as NAND memory cells.

Each string 210 of memory cells 205 may be associated with a corresponding digit line 215 (e.g., digit line 215-a, 215-b) that is shared by the memory cells 205 in the string 210. Each memory cell 205 in a string 210 may be associated with a separate word line 230 (e.g., word line 230-a, 230-i, 230-n), such that the quantity of word lines 230 may be equal to the quantity of memory cells 205 in a string 210.

NAND memory may be hierarchically organized as strings 210 that include multiple memory cells 205, pages 255 that include one or more memory cells 205 that are connected to the same word line 230 (e.g., memory cells 205 from multiple strings 210), blocks 260 that include one or more pages 255, planes that include one or more blocks 260, and dice that include one or more planes. A die may include one plane, or may include two planes that can operate in parallel, in some examples. A page of memory may be, for example, 4 KB of memory, 8 KB of memory, or another size.

A NAND memory cell may be erased before it can be re-written. In some examples, NAND memory can be written to and read from at the page level of granularity (e.g., by activating the corresponding word line 230), but may not be erasable at the page level of granularity. In some examples, NAND memory may instead be erasable at a higher level of granularity, such as at the block level of granularity. That is, a page 255 may be the smallest unit that may be written, and a block 260 may be the smallest unit that may be erased in some examples. Different memory devices may have different read/write/erase characteristics.

Each string 210 of memory cells 205 in NAND circuit 200 is coupled with a select gate device for drain (SGD) transistor 220 at one end of the string 210 and a select gate device for source (SGS) transistor 235 at the other end of the string 210. SGD transistor 220 and SGS transistor 235 may be used to couple a string 210 of memory cells 205 to a digit line 215 and/or to a source node 250 (e.g., source node 250-a, 250-b) by applying a voltage at the gate 245 of SGD transistor 220 and/or at the gate 240 of SGS transistor 235, respectively.

During NAND memory operations, various voltage levels associated with source node 250, gate 240 of an SGS transistor 235 associated with source node 250, word lines 230, drain node 225, gate 245 of an SGD transistor 220 associated with drain node 225, and digit line 215 may be applied to perform one or more operations (e.g., program, erase, or read) on at least some NAND memory cells in a string 210.

In some examples, during a read operation, a positive voltage may be applied to digit line 215 connected to drain node 225 whereas source node 250 may be connected to a ground or a virtual ground (e.g., approximately 0 V). For example, the voltage applied to drain node 225 may be 1 V. Concurrently, voltages applied to gates 245 and 240 may be increased above the threshold voltages of the one or more SGS transistors 235 associated with source node 250 and the one or more SGD transistors 220 associated with drain node 225, such that a channel associated with string 210 may be electrically connected to drain node 225 and source node 250. A channel may be an electrical path through the memory cells 205 in a string 210 (e.g., through the transistors in the memory cells 205) that may conduct current under certain operating conditions.

Concurrently, multiple word lines 230 (e.g., word lines 230-a, 230-i, 230-n, or in some examples all word lines 230) except a selected word line (i.e., word lines associated with unselected cells in string 210) may be connected to a voltage (e.g., VREAD) that is higher than the highest threshold voltage (VT) of memory cells in string 210. VREAD may cause some or all of the unselected memory cells in string 210 to turn “ON” so that each unselected memory cell can maintain high conductivity in a channel associated with it. In some examples, a word line 230 associated with a selected cell may be connected to a voltage, VTarget. VTarget may be selected at a value between VT of an erased memory cell and VT of a programmed memory cell in string 210. When the selected memory cell exhibits an erased VT (e.g., VTarget>VT of the selected memory cell), the selected memory cell 205 may turn “ON” in response to the application of VTarget and thus allow a current to flow in the channel of string 210 from digit line 215 to source 250. When the selected memory cell exhibits a programmed VT (e.g., hence VTarget<VT of the selected memory cell), the selected memory cell may turn “OFF” in response to VTarget and thus prohibit a current to flow in the channel of string 210 from digit line 215 to source 250. The amount of current flow (or lack thereof), may be sensed by sense component 170 as described with reference to FIG. 1 to read stored information in the selected memory cell 205 within string 210.

FIG. 3 is an example of a system 300 that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples of the present disclosure. The system 300 includes a host device 305 coupled with a memory device 310.

Memory device 310 may be an example of memory device 100 as described with reference to FIG. 1, such as managed memory device, a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and a non-volatile dual in-line memory module (NVDIMM).

Memory device 310 may include a memory device controller 315, which may be an example of memory controller 155 described with reference to FIG. 1, and one or more memory arrays 320 for storing data. Memory arrays 320 may include one or more NAND memory arrays, for example, or other types of memory arrays for reading and writing data for host device 305; e.g., data that is provided by a host device 305 Memory arrays 320 may include a user data block 325 for storing user data.

Host device 305 may use memory device 310 to store data in one or more memory arrays 320 and read data from one or more memory arrays 320. Host device 305 may be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc.

In some examples, memory device 310 may include, in addition to memory arrays 320, SRAM 330 or other types of memory that may be used by memory device 310 for internal storage or calculations, for example. In some examples, SRAM 330 may be included within or coupled with memory device controller 315. In some examples, memory device 310 may store (e.g., write) a first-level L2P table (e.g., a set of entries) in SRAM 330.

In some examples, memory device 310 may include a system table block 335, which may be used, for example, for storing information related to the status of blocks of memory array 320. In some examples, system table block 335 may be included within memory arrays 320. System table block 335 may include non-volatile memory, such as NAND memory, DRAM, ferroelectric memory, other types of memory, or any combination thereof. In some examples, memory device 310 may store one or more second-level L2P tables and/or third-level L2P tables (or other levels of L2P tables, which may be referred to as sets of entries) in system table block 335.

In some examples, SRAM 330 and system table block 335 may be coupled with each other and SRAM 330 and/or system table block 335 may be coupled with memory device controller 315.

In some examples, memory device 310 may maintain one or more sets of entries (e.g., L2P look-up tables) for mapping LBAs generated by host device 305 to physical addresses (e.g., page addresses) of memory array 320. Such sets of entries may be generated based on receiving one or more write commands from the host device 305 that each include an LBA for writing data. In some examples, the L2P tables may include a first-level L2P table with entries pointing to second-level L2P tables, which in turn may include entries that point to third-level (e.g., terminal) L2P tables or that point directly to data stored sequentially in memory array 330.

In some examples, entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on. In some examples, if an entire terminal L2P table consists of sequential physical addresses (e.g., corresponding to the sequentially indexed LBAs of the table), memory device controller 315 may store an entry in a higher-level L2P table that includes the first physical address (e.g., the first physical address corresponding to the first LBA of the table, LBA N), along with an indication that the entry points directly to data in the memory array 320 rather than pointing to a terminal L2P table in the system table block 335.

Host device 305 includes host controller interface 340. Host controller interface 340 may provide an interface for passing control, address, data, and other signals between host device 305 and memory device 310. Host device 305 may transmit memory access commands, such as read or write commands, to memory device 310 using host controller interface 340.

Memory device controller 315 may receive signals from host device 305 via host controller interface 340 and may cause memory device 310 to perform certain operations in response to receiving such signals. For example, memory device controller 315 may receive a read or write command from host device 305 and, in response, may cause memory device 310 to read data or write data to memory array 330 based on the received command.

In some examples, memory device controller 315 may, during a read operation, access an entry in a first-level L2P table in SRAM 330 based on an LBA received in a read command from host device 305. The entry in the first-level L2P table may point to a page of system table block 335 that includes a second-level L2P table associated with the LBA received in the read command. Memory device controller 315 may access an entry of the second-level L2P table based on the LBA. The entry of the second-level L2P table may include a pointer to a physical address of memory array 320 (e.g., for accessing data within sequentially stored data in user data block 325) or a pointer to a third-level (e.g., terminal) L2P table in system table block 335. The entry of the second-level L2P table may also include a value of a flag that indicates whether the entry points to the data in user data block 325 or to a third-level L2P table in system table block 335.

If the entry in the second-level L2P table indicates that the entry points to sequential data in user data block 325, memory device controller 315 may read at least some, if not all, of the sequential data (e.g., one or more pages of data) in user data block 325 based on the starting physical address, and may transmit the data to the host device 305.

If the entry in the second-level L2P table indicates that the entry points to a third-level (terminal) L2P table in system table block 335, memory device controller 315 may read an entry of the third-level L2P table in system table block 335 to identify a physical address of the data in user data block 325. Memory device controller 315 may read the data (e.g., a page of data) in user data block 325 based on the physical address, and may transmit the data to the host device 305.

FIG. 4 illustrates an operational flow 400 for reading data from a memory array using hierarchical L2P tables (e.g., L2P tables 405, 415, 430) that support compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. In some examples, operational flow 400 may be performed by a memory device (such as memory device 310) in response to (e.g., based on) receiving a read command (e.g., from a host device 305) that includes or relates to an LBA, and may include or relate to mapping the LBA to a physical address in a user data block 425 of the memory device. Operational flow 400 may illustrate an example of flow for reading data that bypasses a terminal (e.g., third-level) L2P table.

Operational flow 400 depicts the use of a system table block 410, which may be an example of system table block 335 described with reference to FIG. 3. System table block 410 that may be included in or coupled with an SRAM of the memory device, such as SRAM 330. System table block 410 may be organized as multiple die (e.g., Die 0 and Die 1), each of which include one or more planes (e.g., Plane 0, Plane 1). Each plane may include multiple pages (e.g., page 0 through 9). In some examples, each square 440 (e.g., square 440-a) of system table block 410 may represent a page or a subset of a page. For example, if a page of system table block 410 is 16 kB, each square 440 (e.g., including square 440-a) may represent a 4 KB subset of the page.

Operational flow 400 further depicts the use of a user data block 425, which may be an example of user data block 325 described with reference to FIG. 3. User data block 425 that may be included in a memory array of the memory device, such as memory array 330. Like system table block 410, user data block 425 may be organized as multiple die (e.g., Die 0 and Die 1), each of which include one or more planes (e.g., Plane 0, Plane 1). Each plane may include multiple pages (e.g., page 0 through 9). Each square 440 (e.g., including square 440-b) of user data block 425 may represent a page or a subset of a page.

In some examples, a first-level L2P table 405 may be stored in system table block 410. In response to receiving a read command that includes an LBA, the memory device may read (e.g., retrieve, look up) an entry 405-a in the first-level L2P table 405 based on the LBA. In some examples, the entry 405-a may be associated with a group of LBAs that include the LBA received in the read command. The entry 405-a may include a physical address of a page of a system table block 410 that contains (e.g., stores) a second-level L2P table 415. In operational flow 400, for example, the entry 405-a may include a physical address that points to Page 5 (or a subset of Page 5) of Plane 0 of Die 0, which may contain second-level L2P table 415.

The memory device may then read an entry 415-a in second-level L2P table 415 based on the LBA. The entry 415-a may include a physical address of a page of a user data block 425 that corresponds to a first page of multiple pages of sequentially stored data. The multiple pages of sequentially stored data may include the page of data requested by the host device; e.g., the page of data indicated by the LBA in the read command.

In the example of operational flow 400, the entry 415-a may be a four-byte entry that includes a physical address that points to Page 4 (or a subset of Page 4) of Plane 0 of Die 1, where Page 4 may be the first page of multiple pages that include sequentially stored data. (The size of an entry of an L2P table may be different depending on various characteristics of a memory device.)

In some examples, the entry 415-a may include a flag 420 that may be set to a first value that indicates that the physical address in entry 415-a points directly to a page of data in user data block 425 or may be set to a second value that indicates that the physical address in entry 415-a points to a third-level L2P table in system table block 410. In operational flow 400, the value of the flag may be a first value, indicating that the physical address of entry 415-a points directly to a page of data in user data block 425. In some examples, a value of flag 420 may consume one or more bits in entry 415-a, such as a bit in the least significant byte (e.g., byte 3).

If the LBA included in the read command corresponds to the starting page 435 (e.g., first page, initial page) of the sequentially stored data (e.g., the page pointed to by the physical address in entry 415-a), the memory device may read the data from the starting page 435 and transmit the data to the host device.

If the LBA included in the read command corresponds to a different page (e.g., a page that is different than the starting page) of the sequentially stored data, the memory device may determine (e.g., calculate) a second physical address corresponding to the different page, such as by applying an offset to the physical address of entry 415-a to determine the second physical address. The memory device may read the data from the different page indicated by the second physical address, based on determining (e.g., calculating) the second physical address corresponding to the different page. The memory device may transmit the data to the host device.

FIG. 5 illustrates an operational flow 500 for reading data from a memory array using hierarchical L2P tables (e.g., L2P tables 405, 415, 430) that support compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. In some examples, operational flow 500 may be performed by a memory device (such as memory device 310) based on receiving a read command (e.g., from a host device 305) that includes an LBA, and may include mapping the LBA to a physical address in a user data block 425 of the memory device. Operational flow 500 may be similar to operational flow 400 but may illustrate an example of a flow for reading data that does not bypass a terminal (e.g., third-level) L2P table.

In response to receiving a read command that includes a different LBA (e.g., a different LBA than the LBA described with reference to operational flow 400). In operational flow 500 the different LBA may be included within the group of LBAs associated with entry 405-a. Thus, the memory device may read the entry 405-a in the first-level L2P table 405 based on the different LBA. As discussed with reference to operational flow 400, entry 405-a may include a physical address of a page of system table block 410 that contains second-level L2P table 415. In various examples, the different LBA may be within a different group of LBAs, and may therefore be associated with a different entry of first-level L2P table 405 that points to a different second-level L2P table than second-level L2P table 415.

The memory device may read an entry 415-b in second-level L2P table 415 based on the LBA. The entry 415-b may be associated with a group of LBAs that includes the different LBA, and may include a physical address of a page of system table block 410 that contains a third-level L2P table 430 for mapping the group of LBAs to physical addresses. In operational flow 500, for example, the entry 415-b may include a physical address that points to Page 8 (or a subset of page 8) of Plane 0 of Die 1, which may contain third-level L2P table 430.

In the example of operational flow 500, the entry 415-b may, like entry 415-a of operational flow 400, be a four-byte entry that includes a flag 420 whose value indicates whether the physical address in entry 415-b points directly to a page of data in user data block 425 or points to a third-level L2P table in system table block 410. In operational flow 500, the value of the flag may indicate that the physical address of entry 415-b points to a third-level L2P table.

The memory device may read an entry 430-a in third-level L2P table 430 based on the LBA and based on the value flag indicating that the physical address points to a third-level L2P table in system table block 410; e.g., based on the LBA and in response to determining that the value of the flag indicates that the physical address points to a third-level L2P table. The entry 430-a may include a physical address of a page of user data block 425 that the data requested by the host device; e.g., the data associated with the LBA included in the read command. The memory device may read the data at the page of user data block 425 pointed to by the physical address of entry 430-a and transmit the data to the host device.

Thus, operational flow 500 may incur additional latency for reading data requested by the host device relative to operational flow 400, because in operational flow 500 the memory device may traverse (e.g., read entries from) all three levels of L2P tables, while in operational flow 400 the memory device may bypass the terminal L2P table.

FIG. 6 illustrates an example of a flow 600 for building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. Flow 600 may be used to build or update an intermediate L2P table, such as a second-level L2P table, that may include entries that point directly to sequentially stored data and other entries that point to terminal L2P tables.

At 605, a memory device may initiate a process for building or updating one or more L2P tables in response to (e.g., based on), for example, receiving a write command from a host device. The write command may include an LBA associated with writing data to a user data block of the memory device.

In response to receiving the write command, at 610 the memory device may determine whether a sequential data stream is open. For example, the memory device may determine whether the LBA included in the write command received at 605 is sequential (having a sequential index, consecutive, contiguous) with an LBA included in a previous write command (e.g., a most recently received prior write command), or whether a physical address corresponding to the LBA included in the write command is consecutive with a physical address corresponding to an LBA of the previous write command, or whether other conditions or relationships exist, or any combination thereof.

In response to determining that a stream is not open, at 615 the memory device may determine whether the LBA included in the write command corresponds to the first LBA of a terminal L2P table (such as a third-level L2P table). That is, the memory device may determine whether a new stream may be initialized in case subsequent write commands cause the memory device to sequentially store data.

In response to determining that the LBA included in the write command does not correspond to the first LBA of a terminal L2P table, at 620 the memory device may store (e.g., write, save), in a L2P table, one or more physical addresses pointing to the data written in response to receiving the write command, and may end the current process at 650. In some examples, the L2P table may be a terminal table (e.g., if step 620 is performed after determining, at 610, that a stream is not open) or a higher-level table, such as a second-level table (e.g., if step 620 is performed after a stream is closed at 635 as described below).

In response to determining that the LBA included in the write command does correspond to the first LBA of a terminal L2P table, at 625 the memory device may initialize a stream. For example, the memory device may store an indication that a stream associated with the L2P table has been opened, or that data has been written at a physical address corresponding to a first entry of a terminal L2P table. In some examples, the memory device may save an indication of a number of entries in the L2P table that correspond to pages that have been sequentially stored. In some examples, the memory device may store the physical address in the first entry of the terminal L2P table.

Returning to the decision point of 610, in response to determining that a stream is open (e.g., that at least a first entry of a terminal L2P table has been written to the terminal L2P table or that data has been written to a user data block at a physical address corresponding to the first entry of the terminal table), at 630 the memory device may determine whether the stream is being continued (e.g., is related to one or more previous processes or operations, such as access operations). For example, the memory device may determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at a consecutive physical address) relative to data written in response to receiving a prior write command in the stream.

In response to determining that the stream is not being continued, at 635 the memory device may close the stream. For example, the memory device may update the indication, that the stream associated with the L2P table has been opened, to indicate that the stream is now closed. The memory device may proceed to 615 and perform other steps of flow 600 as previously discussed.

In response to determining that the stream is being continued, at 640 the memory device may update the stream. For example, the memory device may update (e.g., increment) the indication of the quantity of entries in the L2P table that correspond to pages that have been sequentially stored.

At 645, the memory device may determine whether the terminal L2P table has been filled with sequentially stored physical addresses.

In response to determining that the terminal L2P table has not been filled with sequentially stored physical addresses, the memory device may end the current process at 650.

In response to determining that the terminal L2P table has been filled with sequentially stored physical addresses, the memory device may close the stream at 635 as previously described. In this case, the memory device may, at 620, save the physical address of the first LBA of the terminal table in a higher-level L2P table, such as a second-level L2P table.

In some examples, a memory device may, while a stream is open, continue storing entries (physical addresses) in the terminal L2P table each time the memory device stores data at a sequential physical address, and may subsequently discard (e.g., erase, overwrite) the terminal L2P table if the memory device determines that the terminal L2P table has become full of sequentially stored physical addresses.

Thus, flow 600 describes a process for building or maintaining L2P tables that may enable a memory device to bypass accessing (or maintaining) a terminal L2P table when data is sequentially stored.

In some examples, a memory device may receive two or more interleaved streams of write commands, in which each stream includes may include write commands having consecutive logical block addresses that may cause the memory device to write the data for each stream to a corresponding set of consecutive physical addresses. In this example, the memory device may identify different blocks of memory at which to write the data for each stream to enable the multiple streams to be associated with corresponding entries in a second-level L2P table. For example, the memory device may write the first stream of data (e.g., associated with a first stream of write commands) at consecutive physical addresses of a first block of memory, and may write a second stream of data (e.g., associated with a second stream of write commands) at consecutive physical addresses of a second block of memory (e.g., different than the first block of memory). The memory device may store a first entry in an L2P table that includes the starting physical address of the first stream, and may store a second entry in an L2P table that includes the starting physical address of the second stream.

FIG. 7 shows a block diagram 700 of a memory device that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. The memory device 705 may be an example of aspects of a memory device as described with reference to FIGS. 1 through 5. The memory device 705 may include a command component 710, a location determination component 715, a data read component 720, a data transmission component 725, a data write component 730, and a table management component 735. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The command component 710 may receive, at a memory device from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, where the data spans a set of consecutive physical addresses.

In some examples, the command component 710 may receive, at a memory device from a host device, a set of write commands for writing data to the memory device, the set of write commands including: a first write command including a first logical block address corresponding to a first entry of a quantity of entries for mapping a set of consecutive logical block addresses to a corresponding set of physical addresses, and a set of remaining write commands of the set of write commands each including a respective consecutive logical block address.

In some examples, the command component 710 may receive, at the memory device from the host device, a second read command including a second logical block address associated with second data stored in the memory device.

In some examples, the command component 710 may receive, from the host device before receiving the read command, a set of write commands, a first write command of the set of write commands including the first logical block address corresponding to the first physical address, where the set of write commands is associated with writing the data to the set of consecutive physical addresses.

In some examples, the command component 710 may receive, at the memory device from the host device after storing the first physical address and the first value of the flag in the first entry, a read command including a third logical block address of the consecutive logical block addresses.

In some examples, the command component 710 may receive, at the memory device from the host device, a second set of write commands for writing second data to the memory device, the second set of write commands interleaved with the set of write commands and including: a second write command including a third logical block address corresponding to a first entry of a second quantity of entries for mapping a second set of consecutive logical block addresses to a corresponding second set of physical addresses, and a second set of remaining write commands of the second set of write commands each including a second respective consecutive logical block address.

In some examples, the first logical block address corresponds to the first physical address and each of the respective consecutive logical block addresses corresponding to respective consecutive physical addresses of the set of consecutive physical addresses.

The location determination component 715 may determine, based on the first logical block address, a memory location of a first set of entries for mapping a first set of logical block addresses including the first logical block address to a corresponding first set of physical addresses.

In some examples, the location determination component 715 may determine, based on the first physical address and the first value of the flag, the second physical address based on identifying an offset from the first physical address.

In some examples, the location determination component 715 may determine a third physical address indicating the location of the first set of entries based on the first logical block address.

In some examples, the location determine component 715 may determine, based on the second logical block address, the memory location of the first set of entries for mapping the first set of logical block addresses to the corresponding first set of physical addresses, where the first set of logical block addresses includes the second logical block address.

In some examples, the location determination component 715 may identify a second block different than the first block based on receiving the second set of write commands.

In some examples, the third physical address indicates a location of a first page of a first type of memory of the memory device, and the set of consecutive physical addresses indicates locations of a set of pages of a second type of memory in the memory device.

In some examples, the first type of memory includes SRAM of the memory device and the second type of memory includes NAND memory of the memory device.

The data read component 720 may read at least the portion of the data from a second physical address of the set of consecutive physical addresses based on the first physical address and the first value of the flag.

In some examples, the data read component 720 may read the second data from the fourth physical address based on identifying the first entry of the second set of entries.

In some examples, the data read component 720 may read a second portion of the data from the second physical address based on identifying the second physical address.

The data transmission component 725 may transmit the data to the host device.

In some examples, the data transmission component 725 may transmit the second data to the host device.

In some examples, the data transmission component 725 may transmit the second portion of the data to the host device.

The data write component 730 may store the data in the memory device at a set of consecutive physical addresses starting with a first physical address based on receiving the set of write commands.

In some examples, the data write component 730 may store the data at the set of consecutive physical addresses based on receiving the set of write commands.

In some examples, the data write component 730 may store the second data in the memory device at a second set of consecutive physical addresses of the second block starting with a fourth physical address.

The table management component 735 may read, based on the first logical block address, a first entry of the first set of entries, the first entry including a first physical address of the set of consecutive physical addresses and a first value of a flag.

In some examples, the table management component 735 may determine whether a quantity of logical block addresses including the first logical block address and the respective logical block addresses matches the quantity of entries.

In some examples, the table management component 735 may store, based on determining that the quantity of logical block addresses matches the quantity of entries, the first physical address and a first value of a flag in a first entry of a set of entries for mapping a set of logical block addresses including the quantity of logical block addresses to a corresponding set of physical block addresses including the set of consecutive physical addresses.

In some examples, the table management component 735 may read, based on determining the memory location of the first set of entries and on the second logical block address, a second entry of the first set of entries, the second entry including a second physical address and a second value of the flag, where the second physical address indicates a location of a second set of entries for mapping a subset of the first set of logical block addresses, including the second logical block address, to a corresponding subset of the first set of physical addresses.

In some examples, the table management component 735 may identify, based on the second entry of the first set of entries, a first entry of the second set of entries, the first entry of the second set of entries including a fourth physical address indicating a location of the second data.

In some examples, the table management component 735 may store, before receiving the read command, the first value of the flag and the first physical address of the set of consecutive physical addresses in the first entry of the first set of entries based on writing the data to the set of consecutive physical addresses.

In some examples, the table management component 735 may store, for each write command of the set of write commands, a respective entry in a second set of entries including the quantity of entries, the second set of entries for mapping the quantity of logical block addresses to the set of consecutive physical addresses.

In some examples, the table management component 735 may discard, based on determining that the quantity of logical block addresses matches the quantity of entries, the second set of entries.

In some examples, the table management component 735 may read the first entry of the set of entries to read the first physical address and the first value of the flag based on receiving the read command including the third logical block address.

In some examples, the table management component 735 may identify a second physical address of the set of consecutive physical addresses based on reading the first entry.

In some examples, the table management component 735 may determine whether a second quantity of logical block addresses including the third logical block address and the second respective logical block addresses matches the second quantity of entries.

In some examples, the table management component 735 may store, based on determining that the second quantity of logical block addresses matches the second quantity of entries, the fourth physical address and the first value of the flag in a first entry of a second set of entries for mapping a second set of logical block addresses including the second quantity of logical block addresses to a corresponding second set of physical block addresses including the second set of consecutive physical addresses.

In some examples, the first physical address corresponds to a starting page of a set of pages corresponding to the set of consecutive physical addresses.

In some examples, the first physical address and the second physical address are the same physical address.

In some examples, the first value of the flag indicates that the first physical address includes a location of the at least the portion of the data.

FIG. 8 shows a flowchart illustrating a method or methods 800 that supports compressed logical-to-physical mapping for sequentially stored data in accordance with aspects of the present disclosure. The operations of method 800 may be implemented by a memory device or its components as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to FIG. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using special-purpose hardware.

At 805, the memory device may receive, at a memory device from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, where the data spans a set of consecutive physical addresses. The operations of 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be performed by a command component as described with reference to FIG. 7.

At 810, the memory device may determine, based on the first logical block address, a memory location of a first set of entries for mapping a first set of logical block addresses including the first logical block address to a corresponding first set of physical addresses. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed by a location determination component as described with reference to FIG. 7.

At 815, the memory device may read, based on the first logical block address, a first entry of the first set of entries, the first entry including a first physical address of the set of consecutive physical addresses and a first value of a flag. The operations of 815 may be performed according to the methods described herein. In some examples, aspects of the operations of 815 may be performed by a table management component as described with reference to FIG. 7.

At 820, the memory device may read at least the portion of the data from a second physical address of the set of consecutive physical addresses based on the first physical address and the first value of the flag. The operations of 820 may be performed according to the methods described herein. In some examples, aspects of the operations of 820 may be performed by a data read component as described with reference to FIG. 7.

At 825, the memory device may transmit the data to the host device. The operations of 825 may be performed according to the methods described herein. In some examples, aspects of the operations of 825 may be performed by a data transmission component as described with reference to FIG. 7.

In some examples, an apparatus as described herein may perform a method or methods, such as the method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at a memory device from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, where the data spans a set of consecutive physical addresses, determining, based on the first logical block address, a memory location of a first set of entries for mapping a first set of logical block addresses including the first logical block address to a corresponding first set of physical addresses, reading, based on the first logical block address, a first entry of the first set of entries, the first entry including a first physical address of the set of consecutive physical addresses and a first value of a flag, reading at least the portion of the data from a second physical address of the set of consecutive physical addresses based on the first physical address and the first value of the flag, and transmitting the data to the host device.

Some examples of the method 800 and the apparatus described herein may further include operations, features, means, or instructions for determining, based on the first physical address and the first value of the flag, the second physical address based on identifying an offset from the first physical address.

In some examples of the method 800 and the apparatus described herein, the first physical address corresponds to a starting page of a set of pages corresponding to the set of consecutive physical addresses.

In some examples of the method 800 and the apparatus described herein, the first physical address and the second physical address may be the same physical address.

In some examples of the method 800 and the apparatus described herein, determining the memory location of the first set of entries may include operations, features, means, or instructions for determining a third physical address indicating the location of the first set of entries based on the first logical block address.

In some examples of the method 800 and the apparatus described herein, the third physical address indicates a location of a first page of a first type of memory of the memory device, and the set of consecutive physical addresses indicates locations of a set of pages of a second type of memory in the memory device.

In some examples of the method 800 and the apparatus described herein, the first type of memory includes SRAM of the memory device and the second type of memory includes NAND memory of the memory device.

Some examples of the method 800 and the apparatus described herein may further include operations, features, means, or instructions for receiving, at the memory device from the host device, a second read command including a second logical block address associated with second data stored in the memory device, determining, based on the second logical block address, the memory location of the first set of entries for mapping the first set of logical block addresses to the corresponding first set of physical addresses, where the first set of logical block addresses includes the second logical block address, reading, based on determining the memory location of the first set of entries and on the second logical block address, a second entry of the first set of entries, the second entry including a second physical address and a second value of the flag, where the second physical address indicates a location of a second set of entries for mapping a subset of the first set of logical block addresses, including the second logical block address, to a corresponding subset of the first set of physical addresses, identifying, based on the second entry of the first set of entries, a first entry of the second set of entries, the first entry of the second set of entries including a fourth physical address indicating a location of the second data, reading the second data from the fourth physical address based on identifying the first entry of the second set of entries, and transmitting the second data to the host device.

Some examples of the method 800 and the apparatus described herein may further include operations, features, means, or instructions for receiving, from the host device before receiving the read command, a set of write commands, a first write command of the set of write commands including the first logical block address corresponding to the first physical address, where the set of write commands may be associated with writing the data to the set of consecutive physical addresses, and storing the data at the set of consecutive physical addresses based on receiving the set of write commands.

Some examples of the method 800 and the apparatus described herein may further include operations, features, means, or instructions for storing, before receiving the read command, the first value of the flag and the first physical address of the set of consecutive physical addresses in the first entry of the first set of entries based on writing the data to the set of consecutive physical addresses.

In some examples of the method 800 and the apparatus described herein, the first value of the flag indicates that the first physical address includes a location of the at least the portion of the data.

FIG. 9 shows a flowchart illustrating a method or methods 900 that supports compressed logical-to-physical mapping for sequentially stored data in accordance with aspects of the present disclosure. The operations of method 900 may be implemented by a memory device or its components as described herein. For example, the operations of method 900 may be performed by a memory device as described with reference to FIG. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using special-purpose hardware.

At 905, the memory device may receive, at a memory device from a host device, a set of write commands for writing data to the memory device, the set of write commands including. The operations of 905 may be performed according to the methods described herein. In some examples, aspects of the operations of 905 may be performed by a command component as described with reference to