502, the microprocessor 112 in the flash memory controller 110 receives a read command, such as a read command from the host device 130, to start reading a first logical page of a physical page. Specifically, the microprocessor 112 sends a read request to the flash memory module 120 through the control logic 114 to request to read the first logical page. After receiving the read request, the flash memory module 120 uses a first set of threshold voltages to read a section of the first logical page to obtain readout information. In order to facilitate the following explanation, the physical page takes the physical page P_0 shown in FIG. 2 as an example, and each memory unit in the physical page P_0 can store four bits, that is, the physical page P_0 includes four logical pages, and the four logical pages are used to store the top bits, upper bits, middle bits and lower bits shown in FIG. 3, respectively. In addition, in the following description, the first logical page is used to store the upper bits.

In Step 504, the decoder 134 of the flash memory controller 110 performs a decoding operation on the readout information of a section of the first logical page. In this embodiment, since the first logical page is used to store the upper bits shown in FIG. 3, the first set of threshold voltages used to read the first logical page includes the threshold voltages VT2, VT8 and VT14 as shown in FIG. 3 or FIG. 6. In addition, the section in the first logical page can be a codec unit, and its size can be 4 kilo-bytes (KB) or other suitable sizes. The decoding process of this section by the decoder 134 may include a hard decoding and/or a soft decoding, where the hard decoding may be a Bose-Chaudhuri-Hocquenghem (BCH) code or a low-density parity code (LDPC) decoding method, and soft decoding can be the LDPC decoding method. Since the decoding operation of the decoder 134 is well known to those with ordinary knowledge in the art, the details of the decoding operation will not be described here.

In Step 506, the decoder 134 determines whether the readout information of the section of the first logical page is decoded successfully. If so, the flow enters Step 518 to end the read operation of the section of the first logical page; if not, the flow enters Step 508.

In Step 508, the flash memory controller 110 obtains first readout information, second readout information and third readout information of the section of the first logical page, wherein the first readout information, the second readout information and the third readout information are obtained by the flash memory module 120 using the first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted set of threshold voltages to read the section of the first logical page, respectively. In one embodiment, the first readout information may be the readout information obtained in Step 502, and the readout information temporarily stored in the control logic 114 may be directly used as the first readout information in Step 508. Taking FIG. 6 as an example, the control unit 136 of the flash memory controller 110 can send a read request to the flash memory module 120 to use the positively adjusted first set of threshold voltages (that is, the threshold voltage (VT2+Δ), (VT8+Δ) and (VT14+Δ)) to read the first logical page to obtain the second readout information, where “A” can be any suitable adjustment value (voltage value). Then the control unit 136 of the flash memory controller 110 can send a read request to the flash memory module 120 to use the negatively adjusted first set of threshold voltages (that is, the threshold voltage (VT2−Δ), (VT8−Δ) and (VT14−Δ)) to read the first logical page to obtain the third readout information. In this embodiment, the first readout information, the second readout information and the third readout information are temporarily stored in a buffer within the control logic 114.

In this embodiment, assuming that the size of the section of the first logical page is 4 KB (that is, 32768 bits), then each of the first readout information, the second readout information and the third readout information will also have 32768 bits.

In Step 510, the decoder 134 uses a default LLR mapping table to soft-decode the section of the first logical page. Specifically, each bit in the first readout information can be regarded as a hard bit or a sign bit, and each bit in the second readout information and the third readout information is regarded as a soft bit. For each memory unit, it will have three bits of information, namely a hard bit, a first soft bit and a second soft bit, which are represented by (BH, BS1, BS2) in the following description. The above three bits of information (BH, BS1, BS2) have eight possible combinations, which are (1, 1, 1), (1, 1, 0), (1, 0, 1), (1, 0, 0), (0, 1, 1), (0, 1, 0), (0, 0, 1) and (0, 0, 0). The default LLR mapping table records different combinations (BH, BS1, BS2) and the corresponding LLR values, where the LLR value is used to represent the reliability of the hard bit. For example, if (BH, BS1, BS2) is equal to (1, 1, 1), it means that the upper bit of the memory unit has the highest reliability of “1” (for example, the bit value is “1” with 99% reliability); if (BH, BS1, BS2) is equal to (1, 1, 0), it means that the upper bit of the memory unit has the second highest reliability is “1”; if (BH, BS1, BS2) is equal to (0, 1, 1), it means that the upper bit of the memory unit has the highest reliability of “0”, . . . , and so on. After determining the LLR value of each memory unit according to the default LLR mapping table, the LDPC decoding circuit in the decoder 134 can begin to soft-decode the section of the first logical page based on these LLR values. In addition, since the operations of the LLR mapping table and LDPC soft decoding are well known to those with ordinary knowledge in the art, these details will not be described here.

In Step 512, the decoder 134 determines whether the section can be decoded successfully. If the decoding operation fails, the flow enters Step 514; and if the decoding is successful, the flow enters Step 516.

In Step 514, if the control logic 114 includes other LLR mapping tables, the decoder 134 uses the other LLR mapping tables to soft-decode the section of the first logical page. In addition, if all the LLR mapping tables have been used and cannot successfully decode the section of the first logical page, the decoder 134 can use other suitable decoding methods, such as redundant array of independent disks (RAID) decoding method to decode.

In Step 516, the LLR mapping table generation/update unit 138 generates a new LLR mapping table according to the decoded data of the section of the first logical page, the first readout information, the second readout information and the third readout information, for subsequent use by the decoder 134 when decoding other sections. Specifically, the decoded data, the first readout information, the second readout information and the third readout information have the same number of bits, for example, 32768 bits. For each memory unit, it will have four bits of information, namely the decoded bit, the hard bit, the first soft bit and the second soft bit, which are represented by (DD, BH, BS