420 may be faster than the time to write or read data in or from the memory cell array (e.g., the memory cell array 140 of FIG. 2) of the nonvolatile memory device 100. That is, in a runtime state of the memory system (e.g., the memory system 10 of FIG. 1), the meta data and the journal data may be written in or read from the buffer memory 420, thereby speeding up data processing. The buffer memory 420 may include a meta memory 421 and a journal memory 422.

The buffer controller 410 may receive a plurality of meta data and a write or read command of the meta data from the accelerator 300 to write or read the meta data in or from the meta memory 421. The buffer controller 410 may also receive a plurality of journal data and a write or read command of the journal data from the accelerator 300 to write or read the journal data in or from the journal memory 422.

FIG. 4 is an example block diagram illustrating a first ECC engine and a second ECC engine according to some embodiments.

Referring to FIG. 4, the first ECC engine 411 may include a first encoding circuit 411_1 and a first decoding circuit 411_2, and the second ECC engine 412 may include a second encoding circuit 412_1 and a second decoding circuit 412_2. Each of the first and second encoding circuits 411_1 and 412_1 may receive a control command from the accelerator (e.g., the accelerator 300 of FIG. 1) to generate parity bits for write data received from the accelerator (e.g., the accelerator 300 of FIG. 1). Each of the first and second decoding circuits 411_2 and 412_2 may receive a control command from the accelerator (e.g., the accelerator 300 of FIG. 1), correct error bits of the read data by using the read data to be read and parity bits in accordance with the command of the accelerator 300 and transmit the error-corrected read data to the accelerator (e.g., the accelerator 300 of FIG. 1). Hereinafter, an operation of generating parity bits for the write data will be referred to as ‘encoding’, and an operation of correcting an error by using parity bits for the read data will be referred to as ‘decoding’.

In a decoding process, some data having an error may fail to be decoded through the ECC engine and thus cannot be corrected. In the present inventive concepts, such data (the data having an error uncorrectable through the ECC engine) will be referred to as an uncorrectable error correction code (UECC). On the contrary, some other data having an error may be decoded through the ECC engine and then their error may be corrected and output. In the present inventive concepts, such data (the data having an error correctable through the ECC engine) will be referred to as a correctable error correction code (CECC).

According to some embodiments, the first ECC engine 411 and the second ECC engine 412 may have different error correction performances. For example, the first ECC engine 411 and the second ECC engine 412 may have different unit sizes in write data to be encoded and read data to be decoded. In this case, the larger unit size of data may mean that the number of bits of data to be encoded or decoded is larger. The larger the unit size of write data to be encoded is and/or the larger the unit size of read data to be decoded is, the higher the error correction performance may be. For example, the second ECC engine 412 may have a larger unit size of data input and/or a larger unit size of data output than those of the first ECC engine 411.

However, encoding the larger write data or decoding the larger read data may increase overhead in a data transmission and reception process of the buffer controller 410. Therefore, there is a need to achieve an appropriate balance between improving reliability through the application of the ECC engines having higher performance and increasing overhead occurring in the data transmission and reception process. In addition, a plurality of ECC engines having different error correction performances may be configured by various other methods and are not limited to the above-described methods.

FIG. 5 is an example block diagram illustrating a process of writing and reading data with respect to a buffer memory.

Referring to FIG. 5, the accelerator 300 may divide a storage space of the buffer memory 420 into a first area AREA_1 and a second area AREA_2. The accelerator 300 may set the meta memory 421 in which the meta data is stored in the buffer memory 420 to the first area AREA_1, and may set the journal memory 422 in which the journal data is stored to the second area AREA_2.

The accelerator 300 may set the write data, which is written in the first area AREA_1, to be encoded through the first ECC engine 411, and may set the read data, which is stored in the first area AREA_1 and becomes a target for the read operation, to be decoded through the first ECC engine 411. The accelerator 300 may set the write data, which is to be written in the second area AREA_2, to be encoded through the second ECC engine 412, and may set the read data, which is stored in the second area AREA_2 and becomes a target for the read operation, to be decoded through the second ECC engine 412.

FIG. 6 is an example flow chart illustrating a process of recovering an error of some of data stored in a buffer memory when the error cannot be corrected. FIGS. 7 and 8 are example block diagrams illustrating a process of recovering an error of some of data stored in a buffer memory when the error cannot be corrected.

Referring to FIGS. 6 to 8, during the runtime of the memory system (e.g., the memory system 10 of FIG. 1), a plurality of meta data and a plurality of journal data may be written in and read from the buffer memory 420 through the accelerator 300 (S101). The buffer controller 410 may perform encoding for written data and perform decoding for read data.

While the data is being written or read, the accelerator 300 may check whether the UECC occurs (S102). When the UECC does not occur (S102—No), the writing or reading of the data may be repeated as it is (e.g., without correction). When the UECC occurs (S102—Yes), the accelerator 300 may determine whether the data in which the UECC occurs is meta data or journal data (S103).

When it is determined that the UECC has occurred in first data DATA_1 which is a portion of the meta data stored in the buffer memory 420 (S103-M), the accelerator 300 may load old meta data OMDs and old journal data OJDs, which are stored in the nonvolatile memory device 100, into the buffer memory (e.g., the buffer memory 420) through the memory interface 202 (S104). Also, the accelerator 300 may update the meta data based on journal data JDs that are stored in the journal memory 422 of the buffer memory 420 and include change details (indicate changes) of the meta data (S105). In other words, even though the first data DATA_1 is damaged or lost, the meta data may be recovered using a plurality of old meta data OMDs and a plurality of old journal data OJDs, which are stored in the nonvolatile memory device (e.g., the nonvolatile memory device 100 of FIG. 1), and a plurality of journal data JDs stored in (the journal memory 422 of) the buffer memory 420.

When it is determined that the UECC has occurred in the second data DATA_2, which is a portion of the journal data stored in the buffer memory 420 (S103-J), the accelerator 300 may transfer (flush) the meta data MDs stored in (the meta memory 421 of) the buffer memory 420 to the nonvolatile memory device 100 (S106). Therefore, the meta data may be preserved, so that reliability of the meta data may be ensured.

Referring to FIG. 5, the second ECC engine 412 of the buffer controller 410 may have higher error correction performance than that of the first ECC engine 411. The second ECC engine 412 may correct an error in data to be written in or read from the second area AREA_2, and the second area AREA_2 may include the journal memory 422. The first ECC engine 411 may correct an error in data to be written in or read from the first area AREA_1, and the first area AREA_1 may include the meta memory 421. That is, when writing or reading the journal data, the ECC engine having relatively high performance may be used, whereby reliability of the memory system may be increased.

Meanwhile, increasing the size of data written in or read from the buffer memory 420 to improve error correction performance may increase overhead during data transmission and reception of the buffer memory 420 as described above.

According to some embodiments, by differentially applying the ECC engine having high performance to a plurality of journal data stored in the buffer memory 420 (e.g., higher performance than a performance of an ECC engine applied to a plurality of meta data stored in the buffer memory 420), which are relatively small (smaller) in size as compared with a plurality of meta data stored in the buffer memory 420, an appropriate balance may be achieved between improving reliability through the application of the ECC engine having higher performance and increasing overhead occurring in the data transmission and reception process.

Also, as the ECC engine having relatively low (lower) performance is applied to the meta data, when reliability of the journal data stored in the buffer memory 420 is ensured even though the UECC occurs, the meta data may be recovered using the journal data stored in the buffer memory 420. As a result, it is possible to prevent damage or loss of the meta data without significantly increasing the overhead occurring in the data transmission and reception process, thereby providing a memory system with improved reliability.

FIG. 9 is an example block diagram illustrating a process of writing and reading data with respect to a buffer memory.

Referring to FIG. 9, the accelerator 300 may further include a first cache 330a. Although the first cache 330a is shown as being included in the journal management unit 320, the first cache 330a may be included by being packaged in the accelerator 300 or may be positioned outside the accelerator 300, but is not limited to any form. The first cache 330a may have a smaller storage capacity than the buffer memory 420, but may have a faster speed than the buffer memory 420.

According to some embodiments, the accelerator 300 may divide a storage space of the buffer memory 420 into a first area AREA_1 and a second area AREA_2. The accelerator 300 may set the meta memory 421, in which the meta data is stored in the buffer memory 420, to the first area AREA_1, and may set the journal memory 422, in which the journal data is stored, to the second area AREA_2.

Since the journal management unit 320 of the accelerator 300 directly generates journal data and stores the journal data in the buffer memory 420, the journal management unit 320 may generate journal data having a unit size as large as the size (capacity) of the first cache 330a. For example, when the capacity of the first cache 330a is 4 KB, the journal management unit 320 may generate journal data having a size of 4 KB and transmit the generated journal data to the buffer controller 410 (e.g., the second ECC engine 412).

Meanwhile, in case of the meta data, it is difficult to flexibly adjust the size of data to be cached in view of characteristics of the meta data. As described above, since the error correction performance of the ECC engine may be improved as the write data to be encoded is larger, the ECC engine of ultra-high reliability may be applied to the journal data to prevent damage or loss of the meta data, whereby a memory system with improved reliability may be provided.

FIG. 10 is an example block diagram illustrating a meta memory according to some embodiments.

Referring to FIG. 10, an internal storage space of the meta memory 421 may be divided into a plurality of meta load units (MLU). Each meta load unit may store at least a portion of the meta data stored in the meta memory 421. Each meta load unit may have the same size as the pages (e.g., the plurality of pages PAGE1 to PAGEk of FIG. 2) that are units for writing or reading data in or from the memory cell array (e.g., the memory cell array 140 of FIG. 2) of the nonvolatile memory device (e.g., the nonvolatile memory device 100 of FIG. 1).

FIG. 11 is an example flow chart illustrating a process, in which an accelerator arranges each meta load unit in a first area or a second area, according to some embodiments. FIG. 12 is an example block diagram illustrating a process, in which an accelerator arranges each meta load unit in a first area or a second area, according to some embodiments.

Referring to FIGS. 11 and 12, data may be written in and read from, for example, a first meta load unit 421_1 of the plurality of meta load units during the runtime of the memory system (e.g., the memory system 10 of FIG. 1). The accelerator 300 may count UECC and CECC, which are occurred in the first meta load unit 421_1 (S201). For example, the accelerator 300 may count the UECC and the CECC, which are occurred in the first meta load unit 421_1, for a predetermined number of times or a period of time, but the method in which the accelerator 300 counts the UECC and the CECC is not limited to any specific method.

The accelerator 300 may determine whether the first meta load unit 421_1 is defective by counting the UECC and the CECC, which are occurred in the first meta load unit 421_1 (S202). Whether the (n)th meta load unit is defective may be determined by the following equation, but this is only example, and may be obtained in other ways.

N_ECC[n]=α*N_UECC[n]+β*N_CECC[n]

In this case, a and B are preset constants, and may be determined as various values in accordance with embodiments. N_UECC[n] represents the number of occurrences of UECC in the (n)th meta load unit. In case of the first meta load unit 421_1, N_UECC[1] is obtained. N_CECC[n] represents the number of occurrences of CECC in the (n)th meta load unit. In case of the first meta load unit 421_1, N_CECC[1] is obtained.

The accelerator 300 may compare N_ECC[n] with a preset threshold value Nth and determine that the (n)th meta load unit is not defective when N_ECC[n] is less than Nth, that is, in case of N_ECC[n]<Nth. In addition, the accelerator 300 may determine that the (n)th meta load unit is defective when N_ECC[n] is greater than or equal to Nth, that is, in case of N_ECC[n]≥Nth. In this case, the Nth may be variously determined depending on the embodiments. For example, the accelerator 300 may determine whether a meta load unit is defective based on a ratio of a number of error correction successes (e.g., N_CECC[n]) and a number of error correction failures (e.g., N_UECC[n]).

When it is determined that the first meta load unit 421_1 is not defective (S202—No), the accelerator 300 may arrange the first meta load unit 421_1 in the first area AREA_1 (S203). When it is determined that the first meta load unit 421_1 is defective (S202—Yes), the accelerator 300 may arrange the first meta load unit 421_1 in the second area AREA_2 (S204). In this case, the meaning of “arrangement” may not mean a physical movement but mean an address change, etc. of the meta load unit.

The accelerator 300 may determine a defect with respect to each of the plurality of meta load units, and may arrange each meta load unit in the first area AREA_1 or the second area AREA_2 based on the determined result. For example, when the accelerator 300 determines that the first meta load unit 421_1 and a third meta load unit 421_3 have a defect, the accelerator 300 may arrange the first meta load unit 421_1 and the third meta load unit 421_3 in the second area AREA_2. The accelerator 300 may arrange a second meta load unit 421_2 and a fourth meta load unit 421_4, which are determined to have no defect, in the first area AREA_1.

In conclusion, the second area AREA_2 may include the journal memory 422 and a partial space of the meta memory 421 occupied by the meta load unit determined to have a defect among the plurality of meta load units, and the first area AREA_1 may include a partial space of the meta memory 421 occupied by the meta load unit determined to have no defect among the plurality of meta load units.

A defect may occur in a partial storage space of the buffer memory 420 due to various reasons such as a manufacturing defect. When a defect occurs in a partial storage space, a plurality of UECCs may occur when data is written in or read from a meta load unit, which includes or is adjacent to the corresponding space.

According to some embodiments, the accelerator 300 may allow the meta load unit to be arranged in the second area AREA_2 (when the meta load unit is defective), thereby correcting a data error (e.g., meta data error) through the ECC engine (e.g., the second ECC engine 412) having high performance (e.g., higher than the first ECC engine 411) differentially from other meta units. For example, when the meta load unit is not defective, the accelerator 300 may arrange the meta load unit to the first area AREA_1 so that the first ECC engine 411 may correct data error (e.g., meta data error). Therefore, an appropriate balance may be achieved between improving reliability through the application of the ECC engine having higher performance and increasing overhead occurring in the data transmission and reception process.

FIG. 13 is an example block diagram illustrating a process of writing and reading data with respect to a buffer memory.

Referring to FIG. 13, the memory controller (e.g., the memory controller 200 of FIG. 1) may further include a second cache 330b. Although the second cache 330b is shown as being positioned outside the accelerator (e.g., the accelerator 300 of FIG. 1), the second cache 330b may be included by being packaged inside the accelerator (e.g., the accelerator 300 of FIG. 1) or may be positioned outside the accelerator (e.g., the accelerator 300 of FIG. 1), but is not limited to any form.

The second cache 330b may have a smaller storage capacity than the buffer memory 420, but may have a faster speed than the buffer memory 420. The second cache 330b may include a plurality of cache lines. The plurality of cache lines may respectively have various sizes. For example, the second cache 330b may include a first cache line 331b and a second cache line 332b.

According to some embodiments, the accelerator 300 may divide a storage space of the buffer memory 420 into a first area AREA_1 and a second area AREA_2. The accelerator 300 may set a partial space of the meta memory 421 occupied by the meta load unit determined to have no defect among the plurality of meta load units to the first area AREA_1, and may set the journal memory 422 and a partial space of the meta memory 421 occupied by the meta load unit determined to have a defect among the plurality of meta load units to the second area AREA_2.

The accelerator 300 may set the write data, which is written in the first area AREA_1, to be encoded through the first ECC engine 411, and may set the read data, which is stored in the first area AREA_1 and becomes a target for the read operation, to be decoded through the first ECC engine 411. The accelerator 300 may also set the write data, which is to be written in the second area AREA_2, to be encoded through the second ECC engine 412, and may set the read data, which is stored in the second area AREA_