110 at the lower part of FIG. 5, point b corresponding to data “0” described with reference to FIG. 2 or point e corresponding to data “1” described with reference to FIG. 2 is shown.

Referring to FIG. 4, in operation S120, the memory device 100 may perform an operation of writing data into the memory cell MC including the ferroelectric cell capacitor FeCC.

The memory device 100 may activate the word line WL connected to the memory cell MC where data is to be written.

In some embodiments, the memory device 100 may apply a first driving voltage to the word line WL connected to the memory cell MC where data is to be written. For example, the level of the first driving voltage may be VDD+VT when writing data “1” and may be −VDD+VT when writing data “0”. VDD may be a second driving voltage applied to the bit line BL to write the data “1” into the memory cell MC, and −VDD may be a third driving voltage applied to the bit line BL to write the data “0” into the memory cell MC. In addition, VT may be a threshold voltage of the cell transistor CT.

Hereinafter, a case of writing data “1” into the memory cell MC is described first.

When the data “1” is written into the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 may apply the second driving voltage VDD to the bit line BL connected to the memory cell MC. In addition, the memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC.

The first driving voltage VDD+VT and the second driving voltage VDD, respectively applied to the word line WL and the bit line BL, may be applied in the form of pulses.

Referring to the upper part of FIG. 5, in operation S120, the level of the voltage applied to the bit line BL may be increased from the pre-charge voltage VPRE (e.g., 0 V in FIG. 5) to the second driving voltage VDD, maintained for a certain period of time, and then decreased back to the pre-charge voltage VPRE (e.g., 0 V in FIG. 5).

In addition, referring to the upper part of FIG. 5, in operations S120 and S130, the level of the voltage applied to the word line WL may be increased from the ground voltage GND (0 V in FIG. 5) to the first driving voltage (e.g., VDD+VT), maintained for a certain period of time, and then decreased to the ground voltage GND (0 V in FIG. 5). In operation S120, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 5, in operation S120, the ground voltage GND (0 V in FIG. 5) may be continuously applied to the plate line PL after operation S110.

As a result, in operation S120, the second driving voltage VDD may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC, and the ground voltage GND may be applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC. As shown in FIG. 3, the cell voltage Vcell may have the −VDD level according to a voltage convention based on a node where a lower part of the ferroelectric cell capacitor FeCC and the plate line PL are connected. It is assumed that the magnitude of VDD is greater than that of Vmax described with reference to FIG. 2.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 5, the state of the ferroelectric cell capacitor FeCC may be point d described with reference to FIG. 2 because the cell voltage Vcell has the −VDD level. As described above, regardless of the initial state of the ferroelectric cell capacitor FeCC before the write operation is performed, the state of the ferroelectric cell capacitor FeCC in operation S120 may be point d described with reference to FIG. 2.

Referring to FIG. 4, in operation S130, the memory device 100 (e.g., the bit line sense amplifier BLSA) may perform a second pre-charge operation (pre-charge 2).

The memory device 100 may deactivate the word line WL connected to the memory cell MC where data has been written.

In some embodiments, in operation S130, the memory device 100 may apply the ground voltage GND to the word line WL connected to the memory cell MC where data is to be written. Since the level of the voltage applied to the gate end of the cell transistor CT is lower than the level of the threshold voltage, the word line WL connected to the memory cell MC may be deactivated.

Referring to the upper part of FIG. 5, in operation S130, the level of the voltage applied to the bit line BL may be the pre-charge voltage VPRE (e.g., 0 V in FIG. 5).

In addition, referring to the upper part of FIG. 5, in operation S130, the level of the voltage applied to the word line WL may decrease from the first driving voltage (e.g., VDD+VT) to the ground voltage GND (0 V in FIG. 5). In operation S130, the word line WL may be deactivated.

In addition, referring to the upper part of FIG. 5, in operation S130, the ground voltage GND (0 V in FIG. 5) may be continuously applied to the plate line PL after S110 and S120.

Due to the characteristics of the ferroelectric cell capacitor FeCC, the cell voltage Vcell exists although the level of the external voltage is 0 V. Thus, in operation S130, when the ground voltage GND is applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC, the cell voltage Vcell 1 corresponding to data “1” may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 5, since the cell voltage Vcell has a cell voltage level corresponding to data “1”, the state of the ferroelectric cell capacitor FeCC may be point e described with reference to FIG. 2.

Hereinafter, a case of writing data “0” into the memory cell MC is described.

After operation S110, in operation S120, when the data “0” is written into the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 may apply the third driving voltage −VDD to the bit line BL connected to the memory cell MC. In addition, the memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC.

The second driving voltage +VDD applied to the bit line BL when the data “1” is written and the third driving voltage −VDD applied to the bit line BL when the data “0” is written may have the same voltage magnitude but have opposite voltage directions. That is, the third driving voltage −VDD may be a reverse voltage −VDD of the second driving voltage VDD, which has the same magnitude as the second drive voltage VDD.

The first driving voltage (e.g., −VDD+VT) and the third driving voltage-VDD applied to the word line WL and the bit line BL may be applied in the form of pulses.

Referring to the upper part of FIG. 5, in operation S120, the level of the voltage applied to the bit line BL may be decreased from the pre-charge voltage VPRE (e.g., 0 V in FIG. 5) to the third driving voltage −VDD, maintained for a certain period of time, and then increased back to the pre-charge voltage VPRE (e.g., 0 V in FIG. 5).

In addition, referring to the upper part of FIG. 5, in operations S120 and S130, the level of the voltage applied to the word line WL may be increased from the ground voltage GND (0 V in FIG. 5) to the first driving voltage (e.g., −VDD+VT), maintained for a certain period of time, and then decreased to the ground voltage GND (0 V in FIG. 5). In operation S120, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 5, in operation S120, the ground voltage GND (0 V in FIG. 5) may be continuously applied to the plate line PL after operation S110.

As a result, in operation S120, the third driving voltage −VDD may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC, and the ground voltage GND may be applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC. As shown in FIG. 3, the cell voltage Vcell may have the +VDD level according to the voltage convention based on the node where the lower part of the ferroelectric cell capacitor FeCC and the plate line PL are connected. It is assumed that the magnitude of VDD is greater than that of Vmax described with reference to FIG. 2.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 5, the state of the ferroelectric cell capacitor FeCC may be point a described with reference to FIG. 2 because the cell voltage Vcell has the +VDD level. As described above, regardless of the initial state of the ferroelectric cell capacitor FeCC before the write operation is performed, the state of the ferroelectric cell capacitor FeCC in operation S120 may be point a described with reference to FIG. 2.

Referring to FIG. 4, in operation S130, the memory device 100 (e.g., the bit line sense amplifier BLSA) may perform a second pre-charge operation (pre-charge 2).

The memory device 100 may deactivate the word line WL connected to the memory cell MC where the data has been written.

In some embodiments, in operation S130, the memory device 100 may apply the ground voltage GND to the word line WL connected to the memory cell MC where data is to be written. Since the level of the voltage applied to the gate end of the cell transistor CT is lower than the level of the threshold voltage, the word line WL connected to the memory cell MC may be deactivated.

Referring to the upper part of FIG. 5, in operation S130, the level of the voltage applied to the bit line BL may be the pre-charge voltage VPRE (e.g., 0 V in FIG. 5).

In addition, referring to the upper part of FIG. 5, in operation S130, the level of the voltage applied to the word line WL may be decreased from the first driving voltage (e.g., −VDD+VT) to the ground voltage GND (0 V in FIG. 5). That is, in operation S130, the word line WL may be deactivated.

In addition, referring to the upper part of FIG. 5, in operation S130, the ground voltage GND (0 V in FIG. 5) may be continuously applied to the plate line PL after operations S110 and S120.

At this time, due to the characteristics of the ferroelectric cell capacitor FeCC, although the external voltage level is 0 V, there may exist the cell voltage Vcell. Therefore, in operation S130, when the ground voltage GND is applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC, the cell voltage Vcell 0 corresponding to data “0” may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 5, the state of the ferroelectric cell capacitor FeCC may be point b described with reference to FIG. 2 since the cell voltage Vcell has a cell voltage level corresponding to data “0”.

Hereinafter, an operation of the memory device 100 to read data stored in one memory cell MC is described with reference to FIGS. 6, 7, and 8.

Referring to FIG. 6, in operation S210, the memory device 100 (e.g., the bit line sense amplifier BLSA) may perform a third pre-charge operation (pre-charge 3). The bit line sense amplifier BLSA may pre-charge the bit line BL to be read to the pre-charge voltage VPRE. The level of the pre-charge voltage VPRE may be 0 V. Since the word line WL and the plate line PL are in the deactivated state, the word line WL and the plate line PL may have the level of the ground voltage GND. The ground voltage level may be 0 V.

Referring to the upper part of FIG. 7, the level of the voltage applied to the bit line BL, the word line WL and the plate line PL, each connected to the memory cell MC, is shown over time.

Referring to the upper part of FIG. 7, it may be seen that in operation S210, the bit line BL is pre-charged to 0 V, which is the pre-charge voltage VPRE, and since the word line WL and plate line PL are in a deactivated state, the ground voltage of 0 V is applied thereto.

In addition, referring to the lower part of FIG. 7, the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC is shown.

The initial state of the ferroelectric cell capacitor FeCC may be a state of point e described with reference to FIG. 2 to store data “1” or a state of point b described with reference to FIG. 2 to store data “0”.

Referring to FIG. 6, in operation S220, the memory device 100 may perform an operation of reading data from the memory cell MC including the ferroelectric cell capacitor FeCC.

The memory device 100 may activate the word line WL connected to the memory cell MC from which the data is to be read.

In some embodiments, the memory device 100 may apply the first driving voltage to the word line WL connected to the memory cell MC from which data is to be read. For example, the level of the first driving voltage may be any level above VT. The VT may be a threshold voltage of the cell transistor CT.

In operation S220, when the word line WL connected to the memory cell MC is activated, the bit line sense amplifier BLSA may perform a charge sharing operation.

Specifically, since the voltage applied to the bit line BL is pre-charged to the pre-charge voltage VPRE (e.g., 0 V) in operation S110, a part of the charge stored in the ferroelectric cell capacitor FeCC is transferred to the bit line BL connected to the memory cell MC in operation S120, thereby increasing the charge stored in the parasitic capacitor CBL of the bit line BL in the equivalent circuit shown in FIG. 3. That is, the charge-sharing operation may be understood as that the parasitic capacitor CBL shown in FIG. 3 is further connected in parallel to the ferroelectric cell capacitor FeCC to which the cell voltage Vcell is applied.

Therefore, in operation S220, the magnitude of the cell voltage Vcell of the ferroelectric cell capacitor FeCC may decrease, and the degree of decrease may vary depending on the stored data. In addition, the magnitude of the existing cell voltage Vcell may also vary depending on the stored data.

FIG. 8 is a graph of the hysteresis loop linearized with two linear capacitors C₀and C₁. C₀represents a capacitance CFeCC 0 of the ferroelectric cell capacitor FeCC having data “0” stored therein, and C₁represents a capacitance CFeCC 1 of the ferroelectric cell capacitor FeCC having data “1” stored therein.

In operation S220, the level of the voltage VCBL applied to the bit line BL may be approximated as follows in Equation 1:

Equation
⁢

1

VCBL
x

=

{

VCBL
1

=

CFeCC
⁢

1

CFeCC
⁢

1

+
CBL

⋆

−
⁢
VCELL

⁢

1
⁢

(

if
⁢

the
⁢

stored
⁢

data
⁢

is
⁢

a
⁢

“
1
”

)

VCBL
0

=

CFeCC
⁢

0

CFeCC
⁢

0

+
CBL

⋆

-
VCELL

⁢

0
⁢

(

i
⁢
f

⁢

the
⁢

stored
⁢

data
⁢

is
⁢

a
⁢

“
0
”

)

VCBLx represents a level of a sense voltage sensed on the bit line BL according to data x, CFeCC 0 represents a capacitance of the ferroelectric cell capacitor FeCC in which data “0” is stored, CFeCC 1 represents a capacitance of the ferroelectric cell capacitor FeCC in which data “1” is stored, CBL represents a total parasitic capacitance of the bit line BL connected to the memory cell MC, VCELL 1 represents a cell voltage Vcell corresponding to data “1” immediately after the write operation, and VCELL 0 represents a cell voltage Vcell corresponding to data “0” immediately after the write operation.

That is, during the read operation, the memory device 100 may read the data stored in the memory cell MC based on the cell voltage Vcell of the ferroelectric cell capacitor FeCC before the word line WL connected to the memory cell MC is activated.

Alternatively, during the read operation, the memory device 100 may read the data stored in the memory cell MC based on the level of the voltage sensed on the bit line BL after the word line WL connected to the memory cell MC is activated. The level of the voltage applied to the bit line BL after the word line WL connected to the memory cell MC is activated may vary depending on the data stored in the memory cell MC.

Hereinafter, a case of reading data “1” stored in the memory cell MC is described first.

After operation S210, in operation S220, the memory device 100 may apply the first driving voltage to the word line WL connected to the memory cell MC from which the data is to be read. For example, the level of the first driving voltage may be any level above VT. The VT may be a threshold voltage of the cell transistor CT.

When reading the data “1” stored in the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 (e.g., bit line sense amplifier BLSA) may read the data by sensing a first sense voltage (e.g., VCBL1) applied to the bit line BL connected to the memory cell MC. The memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC.

Referring to the upper part of FIG. 7, in operation S220, the level of the voltage sensed on the bit line BL connected to the memory cell MC may be increased from the pre-charge voltage VPRE (e.g., 0 V in FIG. 7) to the first sense voltage (e.g., VCBL1), and may be maintained for a period of time.

The first driving voltage applied to the word line WL may be applied in the form of pulses. Referring to the upper part of FIG. 7, in operation S220 and operation S230 to be described below, the level of the voltage applied to the word line WL may be increased from the ground voltage GND (0 V in FIG. 7) to the first driving voltage, maintained for a certain period of time, and then decreased to the ground voltage GND (0 V in FIG. 7). That is, in operations S220 and S230, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 7, in operation S220, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operation S210.

When the memory device 100 performs the read operation, the bit line sense amplifier circuitry 161 may compare the level of the reference voltage VREF with the level of the voltage applied to the parasitic capacitor CBL to output the first output voltage VOUT 1 corresponding to “1” which is data stored in the memory cell MC. The voltage applied to the parasitic capacitor CBL may correspond to the first sense voltage (e.g., VCBL1) sensed on the bit line BL connected to the memory cell MC.

In some embodiments, since the level of the voltage applied to the parasitic capacitor CBL (e.g., the first sense voltage (e.g., VCBL1)) is greater than that of the reference voltage VREF, the bit line sense amplifier circuitry 161 may output the first output voltage VOUT 1 corresponding to “1”, which is data stored in the memory cell MC.

Referring to FIG. 6, in operation S230, the memory device 100 may perform a rewrite operation.

Specifically, by adjusting the voltage applied to the bit line BL connected to the memory cell MC according to the sensed data, the memory device 100 may restore the ferroelectric cell capacitor FeCC included in the memory cell MC as a charge (e.g., the cell voltage Vcell 1 in operation S210) corresponding to the sensed data.

When the data “1” is rewritten to the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 may apply the second driving voltage VDD to the bit line BL connected to the memory cell MC. In addition, the memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC. The word line WL may continue to be activated in operation S230 after being activated in the operation S220. That is, following operation S220, in operation S230, the memory device 100 may continuously apply the first driving voltage to the word line WL.

Referring to the upper part of FIG. 7, in operation S230, the level of the voltage applied to the bit line BL may be increased from the first sense voltage (e.g., VCBL1) to the second driving voltage VDD, maintained for a period of time, and then decreased to the pre-charge voltage VPRE (e.g., 0 V in FIG. 7).

Furthermore, referring to the upper part of FIG. 7, in operation S230, the level of the voltage applied to the word line WL may be maintained at the first driving voltage. That is, in operations S220 and S230, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 7, in operation S230, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operation S220.

As a result, in operation S230, the second driving voltage VDD may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC, and the ground voltage GND may be applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC. As shown in FIG. 3, the cell voltage Vcell may have the −VDD level according to the voltage convention based on the node where the lower part of the ferroelectric cell capacitor FeCC and the plate line PL are connected. It is assumed that the magnitude of VDD is greater than that of Vmax described with reference to FIG. 2.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 7, the state of the ferroelectric cell capacitor FeCC may be point d described with reference to FIG. 2 because the cell voltage Vcell has the −VDD level.

Referring to FIG. 6, in operation S240, the memory device 100 (e.g., the bit line sense amplifier BLSA) may perform a fourth pre-charge operation (pre-charge 4).

The memory device 100 may deactivate the word line WL connected to the memory cell MC where the data has been rewritten.

In some embodiments, in operation S240, the memory device 100 may apply the ground voltage GND to the word line WL connected to the memory cell MC from which the data is to be read. Since the level of the voltage applied to the gate end of the cell transistor CT is lower than the level of the threshold voltage, the word line WL connected to the memory cell MC may be deactivated.

Referring to the upper part of FIG. 7, in operation S240, the level of the voltage applied to the bit line BL may be the pre-charge voltage VPRE (e.g., 0 V in FIG. 7).

In addition, referring to the upper part of FIG. 7, in operation S240, the level of the voltage applied to the word line WL may be decreased from the first driving voltage to the ground voltage GND (0 V in FIG. 7). That is, in operation S240, the word line WL may be deactivated.

In addition, referring to the upper part of FIG. 7, in operation S240, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operations S210, S220, and S230.

At this time, due to the characteristics of the ferroelectric cell capacitor FeCC, although the external voltage level is 0 V, there may exist the cell voltage Vcell. Therefore, in operation S240, when the ground voltage GND is applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC, the cell voltage Vcell 1 corresponding to data “1” may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 7, since the cell voltage Vcell has a cell voltage level corresponding to data “1”, the state of the ferroelectric cell capacitor FeCC may be point e described with reference to FIG. 2.

Hereinafter, a case of reading data “0” stored in the memory cell MC is described. After operation S210, in operation S220, the memory device 100 may apply the first driving voltage to the word line WL connected to the memory cell MC from which the data is to be read. For example, the level of the first driving voltage may be any level above VT. The VT may be a threshold voltage of the cell transistor CT.

When reading the data “0” stored in the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 (e.g., bit line sense amplifier BLSA) may read the data by sensing the second sense voltage (e.g., VCBL0) applied to the bit line BL connected to the memory cell MC. The memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC.

Referring to the upper part of FIG. 7, in operation S220, the level of the voltage sensed on the bit line BL connected to the memory cell MC may be decreased from the pre-charge voltage VPRE (e.g., 0 V in FIG. 7) to the second sense voltage (e.g., VCBL0) and may be maintained for a period of time.

The first driving voltage applied to the word line WL may be applied in the form of pulses. Referring to the upper part of FIG. 7, in operation S220 and operation S230 to be described below, the level of the voltage applied to the word line WL may be increased from the ground voltage GND (0 V in FIG. 7) to the first driving voltage, maintained for a certain period of time, and then decreased to the ground voltage GND (0 V in FIG. 7). That is, in operations S220 and S230, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 7, in operation S220, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operation S210.

When the memory device 100 performs the read operation, the bit line sense amplifier circuitry 161 may compare the level of the reference voltage VREF with the level of the voltage applied to the parasitic capacitor CBL to output the second output voltage VOUT 0 corresponding to “0”, which is data stored in the memory cell MC. The voltage applied to the parasitic capacitor CBL may correspond to the second sense voltage (e.g., VCBL0) sensed on the bit line BL connected to the memory cell MC.

In some embodiments, the bit line sense amplifier circuitry 161 may output the second output voltage VOUT 0 corresponding to “0”, which is data stored in the memory cell MC, because the level of the voltage applied to the parasitic capacitor CBL (e.g., the second sense voltage (e.g., VCBL0)) is lower than that of the reference voltage VREF.

Referring to FIG. 6, in operation S230, the memory device 100 may perform a rewrite operation.

Specifically, by adjusting the voltage applied to the bit line BL connected to the memory cell MC according to the sensed data, the memory device 100 may restore the ferroelectric cell capacitor FeCC included in the memory cell MC as a charge (e.g., the cell voltage Vcell 1 in operation S210) corresponding to the sensed data.

When the data “0” is rewritten into the memory cell MC including the ferroelectric cell capacitor FeCC, the memory device 100 may apply the third driving voltage −VDD to the bit line BL connected to the memory cell MC.

The second driving voltage +VDD applied to the bit line BL when the data “1” is rewritten and the third driving voltage −VDD applied to the bit line BL when the data “0” is rewritten may have the same voltage magnitude but have opposite voltage directions. That is, the third driving voltage −VDD may be a reverse voltage −VDD of the second driving voltage VDD, which has the same magnitude as the second drive voltage VDD.

In addition, the memory device 100 may apply the ground voltage GND to the plate line PL connected to the memory cell MC. The word line WL may continue to be activated in operation S230 after being activated in operation S220. That is, following operation S220, in operation S230, the memory device 100 may continuously apply the first driving voltage to the word line WL.

Referring to the upper part of FIG. 7, in operation S230, the level of the voltage applied to the bit line BL may be decreased from the second sense voltage (e.g., VCBL0) to the second driving voltage VDD, maintained for a certain period of time, and then increased to the pre-charge voltage VPRE (e.g., 0 V in FIG. 7).

Furthermore, referring to the upper part of FIG. 7, in operation S230, the level of the voltage applied to the word line WL may be maintained at the first driving voltage. That is, in operations S220 and S230, the word line WL may continue to be activated after being activated.

In addition, referring to the upper part of FIG. 7, in operation S230, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operation S220.

As a result, in operation S230, the third driving voltage −VDD may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC, and the ground voltage GND may be applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC. As shown in FIG. 3, the cell voltage Vcell may have the +VDD level according to the voltage convention based on the node where the lower part of the ferroelectric cell capacitor FeCC and the plate line PL are connected. It is assumed that the magnitude of VDD is greater than that of Vmax described with reference to FIG. 2.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 7, the state of the ferroelectric cell capacitor FeCC may be point a described with reference to FIG. 2 because the cell voltage Vcell has the +VDD level.

Referring to FIG. 6, in operation S240, the memory device 100 (e.g., the bit line sense amplifier BLSA) may perform a fourth pre-charge operation (pre-charge 4).

The memory device 100 may deactivate the word line WL connected to the memory cell MC where the data has been rewritten.

In some embodiments, in operation S240, the memory device 100 may apply the ground voltage GND to the word line WL connected to the memory cell MC from which the data is to be read. Since the level of the voltage applied to the gate end of the cell transistor CT is lower than the level of the threshold voltage, the word line WL connected to the memory cell MC may be deactivated.

Referring to the upper part of FIG. 7, in operation S240, the level of the voltage applied to the bit line BL may be the pre-charge voltage VPRE (e.g., 0 V in FIG. 7).

In addition, referring to the upper part of FIG. 7, in operation S240, the level of the voltage applied to the word line WL may be decreased from the first driving voltage to the ground voltage GND (0 V in FIG. 7). That is, in operation S240, the word line WL may be deactivated.

In addition, referring to the upper part of FIG. 7, in operation S240, the ground voltage GND (0 V in FIG. 7) may be continuously applied to the plate line PL after operations S210, S220, and S230.

At this time, due to the characteristics of the ferroelectric cell capacitor FeCC, although the external voltage level is 0 V, there may exist the cell voltage Vcell. Therefore, in operation S240, when the ground voltage GND is applied to the lower part of the memory cell MC including the ferroelectric cell capacitor FeCC, the cell voltage Vcell 0 corresponding to data “0” may be applied to the upper part of the memory cell MC including the ferroelectric cell capacitor FeCC.

Referring to the hysteresis loop characteristic of the ferroelectric cell capacitor FeCC included in the memory cell MC in the lower part of FIG. 7, the state of the ferroelectric cell capacitor FeCC may be point b described with reference to FIG. 2 since the cell voltage Vcell has a cell voltage level corresponding to data “0”.

FIG. 9 is a flowchart of a write operation of a memory device according to a comparative example. FIG. 10 is a diagram for explaining a write operation of a memory device according to a comparative example. FIG. 11 is a flowchart of a read operation of a memory device according to a comparative example. FIG. 12 is a diagram for explaining a read operation of a memory device according to a comparative example.

Hereinafter, a write operation of the memory device 100 according to a comparative example is described with reference to FIG. 9 and FIG. 10.

Referring to FIG. 9, in operation S310, the memory device 100 performs a fifth pre-charge operation (pre-charge 5). Referring to FIG. 10, it may be seen that the bit line BL is pre-charged to the pre-charge voltage VPRE, and the ground voltage GND is applied to the word line WL and the plate line PL.

Hereinafter, a case of writing data “1” into the memory cell MC is described.

After operation S310, in operation S320, the memory device 100 applies a fourth driving voltage to the word line WL connected to the memory cell MC where data is to be written, and the memory device 100 applies a fifth driving voltage +VDD to the bit line BL connected to the memory cell MC where data is to be written. Referring to the lower part of FIG. 10, the state of the ferroelectric cell capacitor FeCC corresponds to point d described with reference to FIG. 2.

Referring to FIG. 9, in operation S330, the memory device 100 applies a sixth driving voltage to the plate line PL connected to the memory cell MC where data is to be written, and pre-charges the bit line BL to the pre-charge voltage VPRE. Referring to FIG. 10, the sixth driving voltage applied to the plate line PL is applied in the form of pulses to the plate line PL in operation S330.

Referring to FIG. 9, in operation S340, the memory device 100 performs a sixth pre-charge operation (pre-charge 6). By applying the ground voltage GND to the word line WL, the word line WL is deactivated.

Since the method of writing data “0” into the memory cell MC is similar to the method of writing data “1” into the memory cell MC described above, description thereof is omitted here in the interest of brevity.

Hereinafter, the read operation of the memory device 100 according to the comparative example is described below with reference to FIGS. 11 and 12.

Referring to FIG. 11, in operation S410, the memory device 100 performs the fifth pre-charge operation (pre-charge 5). Referring to FIG. 12, it may be seen that the bit line BL is pre-charged to the pre-charge voltage VPRE, and the ground voltage GND is applied to the word line WL and the plate line PL.

Hereinafter, a case of reading data “1” stored in the memory cell MC is described.

Referring to FIG. 11, after operation S410, in operation S420, the memory device 100 activates the word line WL and the plate line PL, each connected to the memory cell MC, and the bit line sense amplifier BLSA performs a charge sharing operation. The memory device 100 applies the fourth driving voltage to the word line WL connected to the memory cell MC where data is to be read, and applies the sixth driving voltage to the plate line PL connected to the memory cell MC where data is to be read.

Referring to FIG. 12, in operation S420, the memory device 100 reads the data stored in the memory cell MC based on the level of the voltage sensed on the bit line BL after the word line WL connected to the memory cell MC is activated.

Referring to FIG. 11, in operation S430, the memory device 100 applies the fifth driving voltage +VDD to the bit line BL connected to the memory cell MC where data is to be rewritten. Referring to the lower part of FIG. 12, the state of the ferroelectric cell capacitor FeCC corresponds to point b described with reference to FIG. 2.

In addition, after the sixth driving voltage is applied to the plate line PL for a certain period of time, operation S440 in FIG. 11 is started while applying the ground voltage GND to the plate line PL.

Referring to the lower part of FIG. 12, the state of the ferroelectric cell capacitor FeCC in operation S440 corresponds to point d described with reference to FIG. 2.

In addition, after the fifth driving voltage +VDD is applied to the bit line BL for a certain period of time in operation S440, operation S450 in FIG. 11 is started while applying the pre-charge voltage VPRE to the bit line BL.

Referring to FIG. 11, in operation S450, the memory device 100 performs an eighth pre-charge operation (pre-charge 8). By applying the ground voltage GND to the word line WL, the word line WL is deactivated. Referring to the lower part of FIG. 12, the state of the ferroelectric cell capacitor FeCC in operation S450 corresponds to point e described with reference to FIG. 2.

FIGS. 13A and 13B are diagrams for comparing and explaining an operation of a memory device according to some embodiments and an operation of a memory device according to a comparative example.

Referring to the upper part of FIG. 13A, the level of the voltage applied to or sensed on the bit line BL, the word line WL, and the plate line PL over time during the write operation of the memory device according to some embodiments and described with reference to FIG. 5 is shown, and referring to the lower part of FIG. 13A, the level of the voltage applied to or sensed on the bit line BL, the word line WL, and the plate line PL over time during the write operation of the memory device according to a comparative example described with reference to FIG. 10 is shown.

Referring to the upper part of FIG. 13B, the level of the voltage applied to or sensed on the bit line BL, the word line WL, and the plate line PL over time during the read operation of the memory device according to some embodiments and described with reference to FIG. 7 is shown, and referring to the lower part of FIG. 13B, the level of the voltage applied to or sensed on the bit line BL, the word line WL, and the plate line PL over time during the read operation of the memory device according to a comparative example described with reference to FIG. 12 is shown.

Compared with the write/read operation of the memory device according to a comparative example, the ground voltage GND may be continuously applied to the plate line PL during the write/read operation of the memory device according to some embodiments.

Referring to the lower parts of FIGS. 13A and 13B, a voltage 21 applied to the plate line PL in the form of a pulse in operation S330 during the write operation of the memory device according to a comparative example and a voltage 23 applied to the plate line PL in the form of a pulse through operations S420 and S430 during the read operation of the memory device according to a comparative example are essential for the write or read operation of the memory device according to a comparative example.

On the other hand, referring to the upper part of FIG. 13A, the voltage 13 continuously applied to the plate line PL through operations S110, S120, and S130 during the write operation of the memory device according to some embodiments may be the ground voltage GND. As the memory device according to an embodiment applies the third driving voltage −VDD 11 in the form of a pulse to the bit line BL when writing data “0” into the ferroelectric cell capacitor FeCC, the voltage 13 continuously applied to the plate line PL through operations S110, S120, and S130 during the write operation of the memory device may be the ground voltage GND. The second driving voltage +VDD applied to the bit line BL when the data “1” is written and the third driving voltage −VDD applied to the bit line BL when the data “0” is written have the same voltage magnitude but have opposite voltage directions. That is, the third driving voltage −VDD may be a reverse voltage −VDD of the second driving voltage VDD, which has the same magnitude as the second drive voltage VDD.

In addition, referring to the upper part of FIG. 13B, the voltage 15 continuously applied to the plate line PL in operations S210, S220, S230, and S240 during the read operation of the memory device according to some embodiments may be the ground voltage GND. As the memory device according to some embodiments applies the third driving voltage −VDD 17 in the form of a pulse to the bit line BL when reading and rewriting data “0” from the ferroelectric cell capacitor FeCC, the voltage 15 applied to the plate line PL through operations S210, S220, S230, and S240 during the write operation of the memory device may be the ground voltage GND. The second driving voltage +VDD applied to the bit line BL when the data “1” is written and the third driving voltage −VDD applied to the bit line BL when the data “0” is written have the same voltage magnitude but have opposite voltage directions. That is, the third driving voltage −VDD may be a reverse voltage −VDD of the second driving voltage VDD, which has the same magnitude as the second drive voltage VDD.

Therefore, the plate line decoder (or plate line voltage generator) that applies a voltage to the plate line PL during the write or read operation of the memory device according to a comparative example must be implemented essentially, but the plate line decoder (or plate line voltage generator) that applies a voltage to the plate PL during the write or read operation of the memory device according to some embodiments does not necessarily have to be implemented.

That is, the memory device according to some embodiments may perform the write or read operation with only the word line decoder and the bit line decoder without the plate line decoder.

As a result, the memory device according to some embodiments may reduce the resources for the area previously occupied by the plate line decoder, thereby increasing the efficiency of the area available for design during circuit design. This is described in greater detail with reference to FIGS. 14A to 15B.