64 detects the abnormality of the semiconductor element, and outputs the abnormality detection signal of the valid signal to the logic circuit 65.

When the ASC mode determination circuit 63 determines that the ASC mode is executed and when the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element, the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. According to such a configuration, during the ASC mode, the operation in the ASC mode can be continued regardless of the detection result of the abnormality detection and protection operation circuit 64.

Summary of First Preferred Embodiment

According to the semiconductor element driving apparatus of the first preferred embodiment, the ASC mode determination circuit 63 of the secondary circuit 5 determines whether the normal mode or the ASC mode is executed based on the transmission transition signal corresponding to the transition signal. According to such a configuration, the secondary circuit 5 can make the operation in the ASC mode during the abnormality detection different from the operation during the normal mode during the abnormality detection based on the determination result of the ASC mode determination circuit 63.

Second Preferred Embodiment

FIG. 4 is a circuit diagram illustrating a configuration of a semiconductor element driving apparatus according to a second preferred embodiment. The configuration of the primary circuit 1 in FIG. 4 is similar to a configuration in which a demodulation circuit 16, an FO output circuit 17 that is an output circuit, an input priority determination circuit 18, and an FO terminal that is a terminal are added to the configuration of the primary circuit 1 in FIG. 1, and the modulation circuits 13, 14 are deleted. The configuration of the secondary circuit 5 in FIG. 4 is similar to the configuration, in which the modulation circuit 56 is added to the configuration of the secondary circuit 5 in FIG. 1 and the demodulation circuits 53, 54 and the pulse restoration circuit 62 are deleted.

The modulation circuit 56 of the secondary circuit 5 generates the modulation signal including the burst pulse based on the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64.

The demodulation circuit 16 of the primary circuit 1 generates a burst signal including the burst pulse based on the modulation signal transmitted from the secondary circuit 5 through the signal transmission circuit 3. The FO output circuit 17 smooths the burst signal generated by the demodulation circuit 16, and generates a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64. In the second preferred embodiment, the transmission result signal corresponds to an OR signal of the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64, but may correspond to either the determination signal or the abnormality detection signal.

The input priority determination circuit 18 selects the first control signal of the IN terminal and the second control signal of the ASC_IN terminal based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal, and outputs one of the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 through the modulation circuits 11, 12. The FO terminal is a terminal that outputs the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 to the outside.

FIG. 5 is a timing chart illustrating the operation of the semiconductor element driving apparatus according to the second preferred embodiment. The normal mode, the normal mode during the abnormality detection, the ASC mode, and the ASC mode during the abnormality detection will be described below. In the following description of each mode, an overlapping content will be omitted as appropriate.

The transition signal of an invalid signal is input to the ASC_EN terminal during the normal mode. When the transition signal is the invalid signal, the input priority determination circuit 18 determines that the normal mode is executed regardless of the output signal of the FO output circuit 17. In this case, the input priority determination circuit 18 rejects the second control signal of the ASC_IN terminal, and outputs the first control signal of the IN terminal to the modulation circuits 11, 12.

The modulation circuits 11, 12 generate the modulation signals by performing the edge trigger modulation on the first control signal. The modulation signals generated by the modulation circuits 11, 12 are provided to the demodulation circuits 51, 52 through the signal transmission circuit 3, respectively.

The demodulation circuits 51, 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11, 12 to an S terminal and a R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates the first transmission control signal having substantially the same waveform as the first control signal input to the primary circuit 1 based on the edge trigger signals output from the demodulation circuits 51, 52, and outputs the first transmission control signal from a Q terminal to the logic circuit 65.

When the transition signal of the invalid signal is input to the modulation circuit 15, the modulation circuit 15 outputs the invalid signal, the invalid signal is transmitted to the demodulation circuit 55 through the signal transmission circuit 3, and the demodulation circuit 55 outputs the transmission transition signal of the invalid signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is executed based on the transmission transition signal of the invalid signal, and outputs the determination signal of the invalid signal indicating the determination result to the logic circuit 65.

When the ASC mode determination circuit 63 determines that the normal mode is executed, the logic circuit 65 outputs the driving signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal of the IN terminal.

When the abnormality is generated in the semiconductor element or the like during the normal mode, the valid signal is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element and outputs the abnormality detection signal of the valid signal to the logic circuit 65 and the modulation circuit 56.

When the ASC mode determination circuit 63 determines that the normal mode is executed and when the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element, the logic circuit 65 outputs the signal that shuts down the semiconductor element to the OUT terminal regardless of the first transmission control signal.

When the abnormality detection signal of the abnormality detection and protection operation circuit 64 is the valid signal, the modulation circuit 56 generates the modulation signal including the burst pulse by OOK. The modulation signal is transmitted to the demodulation circuit 16 through the signal transmission circuit 3, and the demodulation circuit 16 outputs the burst signal corresponding to the modulation signal to the FO output circuit 17. The burst signal has substantially the same waveform as the modulation signal of the modulation circuit 56.

The FO output circuit 17 smooths the burst signal of the demodulation circuit 16 and generates the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64.

The transmission result signal is output to the FO terminal, and an external apparatus on the side of the primary circuit 1 can check the abnormality of the semiconductor element from the transmission result signal of the FO terminal. In addition, the transmission of the transmission result signal can be implemented by a pair of insulating elements (in this case, a pair of transformers).

Although the transmission result signal is also output to the input priority determination circuit 18, the transition signal of the ASC_EN terminal is the invalid signal, so that the input priority determination circuit 18 determines that the normal mode is executed, and outputs the first control signal of the IN terminal to the modulation circuits 11, 12.

During the ASC mode, the transition signal of the valid signal is input to the ASC_EN terminal. When the transition signal is the valid signal, the modulation circuit 15 generates the modulation signal including a burst pulse by OOK. The modulation signal is transmitted to the demodulation circuit 55 through the signal transmission circuit 3, and the demodulation circuit 55 outputs the transmission transition signal corresponding to the modulation signal to the ASC mode determination circuit 63. The transmission transition signal has substantially the same waveform as the modulation signal of the modulation circuit 15.

The ASC mode determination circuit 63 determines that the ASC mode is executed when the pulse of the transmission transition signal is counted N times within the determination cycle. When determining that the ASC mode is executed, the ASC mode determination circuit 63 outputs the determination signal of the valid signal indicating the determination result not only to the logic circuit 65 but also to the modulation circuit 56. On the other hand, when determining that the normal mode is executed, the ASC mode determination circuit 63 outputs the determination signal of the invalid signal indicating the determination result not only to the logic circuit 65 but also to the modulation circuit 56.

The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform operations similar to the operations during the normal mode during the abnormality detection. Accordingly, the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 are output to the FO terminal and the input priority determination circuit 18. The determination signal of the ASC mode determination circuit 63 is the valid signal, so that the transmission result signal also becomes the valid signal.

When the transition signal of the ASC_EN terminal is the valid signal and when the transmission result signal of the FO output circuit 17 is the valid signal, the input priority determination circuit 18 determines that the ASC mode is accepted by the secondary circuit 5. In this case, the input priority determination circuit 18 rejects the first control signal of the IN terminal and outputs the second control signal of the ASC_IN terminal to the modulation circuits 11, 12.

The modulation circuits 11, 12, the signal transmission circuit 3, the demodulation circuits 51, 52, and the pulse restoration circuit 61 perform the same operations as the operations during the normal mode on the second control signal. Accordingly, the second transmission control signal corresponding to the second control signal of the ASC_IN terminal is output to the logic circuit 65. When the ASC mode determination circuit 63 determines that the ASC mode is executed, the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal of the ASC_IN terminal.

When the abnormality is generated in the semiconductor element or the like during the ASC mode, the valid signal is input to the ErrIN terminal of the secondary circuit 5. When the valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element and outputs the abnormality detection signal of the valid signal to the logic circuit 65 and the modulation circuit 56.

When the ASC mode determination circuit 63 determines that the ASC mode is executed and when the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element, the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. According to such a configuration, during the ASC mode, the operation in the ASC mode can be continued regardless of the detection result of the abnormality detection and protection operation circuit 64.

The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform operations similar to the operations during the normal mode during the abnormality detection. Accordingly, the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 are output to the FO terminal and the input priority determination circuit 18. Both the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 are the valid signals, so that the transmission result signal also becomes the valid signal.

Summary of Second Preferred Embodiment

According to the second preferred embodiment, the input priority determination circuit 18 of the primary circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transition signal of the ASC_EN terminal. According to such a configuration, the numbers of modulation circuits and demodulation circuits can be reduced as compared with the configuration of the first preferred embodiment, so that the area and the number of components of the semiconductor element driving apparatus can be reduced.

In addition, the input priority determination circuit 18 of the primary circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal. According to such a configuration, the input priority determination circuit 18 can perform control to switch the first control signal and the second control signal in consideration of the transmission result signal reflecting the determination result of the ASC mode determination circuit 63.

Third Preferred Embodiment

FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor element driving apparatus according to a third preferred embodiment. The configuration of the primary circuit 1 in FIG. 6 is similar to the configuration of the primary circuit 1 in FIG. 4, in which the transition signal of the ASC_EN terminal is input to the modulation circuits 11, 12 and the modulation circuit 15 is deleted. The configuration of the secondary circuit in FIG. 6 is similar to the configuration, in which the OR circuit 70 is added to the configuration of the secondary circuit 5 in FIG. 4 and the demodulation circuit 55 is removed.

When the transition signal of the ASC_EN terminal is the invalid signal, the modulation circuits 11, 12 of the primary circuit 1 perform the edge trigger modulation on the output signal of the input priority determination circuit 18 in the same operation as the modulation circuits 11, 12 of the second preferred embodiment. On the other hand, when the transition signal of the ASC_EN terminal is the valid signal, the modulation circuits 11, 12 generate the modulation signal including the burst pulse by performing OOK on the output signal of the input priority determination circuit 18.

The OR circuit 70 of the secondary circuit 5 outputs the OR signal of the output signals of the demodulation circuits 51, 52 to the ASC mode determination circuit 63.

FIG. 7 is a timing chart illustrating the operation of the semiconductor element driving apparatus according to the third preferred embodiment. The normal mode, the normal mode during the abnormality detection, the ASC mode, and the ASC mode during the abnormality detection will be described below. In the following description of each mode, an overlapping content will be omitted as appropriate.

In the third preferred embodiment, the OR signal from the OR circuit 70 is input to the ASC mode determination circuit 63. However, the interval of the pulses of the OR signal during the normal mode is relatively long, so that the ASC mode determination circuit 63 determines that the normal mode is executed without counting the pulses of the transmission transition signal N times within the determination cycle.

The subsequent normal mode according to the third preferred embodiment is similar to the normal mode according to the second preferred embodiment. That is, the input priority determination circuit 18 outputs the first control signal of the IN terminal, and the logic circuit 65 outputs the driving signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

The normal mode during the abnormality detection according to the third preferred embodiment is similar to the normal mode during the abnormality detection according to the second preferred embodiment. That is, the abnormality detection and protection operation circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the signal that shuts down the semiconductor element to the OUT terminal regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

During the ASC mode, the transition signal of the valid signal is input to the ASC_EN terminal. In this case, the modulation circuits 11, 12 generate the modulation signal including the burst pulse according to the period of the output signal of the input priority determination circuit 18 by performing OOK on the output signal without performing the edge trigger modulation.

The modulation signal is transmitted to the demodulation circuits 51, 52 through the signal transmission circuit 3, and the demodulation circuits 51, 52 output the signals corresponding to the modulation signal to the S terminal and the R terminal of the pulse restoration circuit 61, respectively. Furthermore, the demodulation circuits 51, 52 output the signal corresponding to the modulation signal to the OR circuit 70.

The OR circuit 70 outputs the OR signal of the output signals of the demodulation circuits 51, 52 to the ASC mode determination circuit 63 as the transmission transition signal. Similarly to the transmission transition signal of the second preferred embodiment, the ASC mode determination circuit 63 counts the pulses of the transmission transition signal including the burst pulses predetermined N times within the determination cycle, and thus determines that the ASC mode is executed.

The subsequent ASC mode according to the third preferred embodiment is similar to the ASC mode according to the second preferred embodiment. That is, the input priority determination circuit 18 outputs the second control signal of the ASC_IN terminal, and the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

As described in the ASC mode, the ASC mode during the abnormality detection according to the third preferred embodiment is similar to the ASC mode during the abnormality detection according to the second preferred embodiment except that a process of generating the transmission transition signal is different from that in the second preferred embodiment. That is, the abnormality detection and protection operation circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

Summary of Third Preferred Embodiment

According to the third preferred embodiment, the numbers of modulation circuits and demodulation circuits can be reduced as compared with the configuration of the second preferred embodiment, so that the area and the number of components of the semiconductor element driving apparatus can be reduced. The modulation circuits 11, 12 may generate and output the modulation signals by OOK also during the normal mode as long as the modulation signals do not affect the determination of the ASC mode determination circuit 63. According to such a configuration, the secondary circuit 5 can check a start of the primary power supply of the primary circuit 1.

Fourth Preferred Embodiment

FIG. 8 is a circuit diagram illustrating a configuration of a semiconductor element driving apparatus according to a fourth preferred embodiment. The configuration of the primary circuit 1 in FIG. 8 is similar to the configuration of the primary circuit 1 in FIG. 6 in which the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 are deleted. The configuration of the secondary circuit 5 in FIG. 8 is similar to the configuration of the secondary circuit 5 in FIG. 6 in which a waveform shaping circuit 72 is added.

In the fourth preferred embodiment, a plurality of signals are selectively input to the IN terminal of the primary circuit 1. The plurality of signals include the first control signal and the control transition signal. The control transition signal corresponds to the second control signal and to the transition signal described above, and includes the burst pulse having a pulse width shorter than that of the first control signal.

The ASC mode determination circuit 63 determines whether the normal mode or the ASC mode is executed based on the transmission transition signal corresponding to the control transition signal.

The modulation circuits 11, 12, the demodulation circuits 51, 52, and the pulse restoration circuit 61 generate the signal including the burst pulse corresponding to the control transition signal. In the fourth preferred embodiment, the signal output from the pulse restoration circuit 61 has substantially the same waveform as the control transition signal. The waveform shaping circuit 72 generates the second transmission control signal that is a square wave signal based on the signal output from the pulse restoration circuit 61. When the ASC mode determination circuit 63 determines that the ASC mode is executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal that is the square wave signal generated by the waveform shaping circuit 72.

FIG. 9 is a timing chart illustrating the operation of the semiconductor element driving apparatus according to the fourth preferred embodiment. The normal mode, the normal mode during the abnormality detection, the ASC mode, and the ASC mode during the abnormality detection will be described below. In the following description of each mode, an overlapping content will be omitted as appropriate.

The first control signal is input to the IN terminal during the normal mode. The modulation circuits 11, 12 generate the modulation signals by performing the edge trigger modulation on the first control signal. The modulation signals generated by the modulation circuits 11, 12 are provided to the demodulation circuits 51, 52 through the signal transmission circuit 3, respectively.

The demodulation circuits 51, 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11, 12 to an S terminal and a R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates the first transmission control signal having substantially the same waveform as the first control signal input to the primary circuit 1 based on the edge trigger signals output from the demodulation circuits 51, 52, and outputs the first transmission control signal from the Q terminal to the waveform shaping circuit 72. The first transmission control signal has a frequency less than the threshold, so that the waveform shaping circuit 72 outputs the first transmission control signal to the logic circuit 65.

The ASC mode determination circuit 63 does not count the pulses of the transmission transition signal N times within the determination cycle, and thus determines that the normal mode is executed. Unlike the ASC mode determination circuit 63 according to the first to third preferred embodiments, the ASC mode determination circuit 63 according to the fourth preferred embodiment sequentially determines, for each signal provided to the IN terminal, whether the signal is the first control signal during the normal mode or the control transition signal during the ASC mode.

As a result of the above operation, the logic circuit 65 outputs the driving signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

The normal mode during the abnormality detection according to the fourth preferred embodiment is similar to the normal mode during the abnormality detection according to the third preferred embodiment. That is, the abnormality detection and protection operation circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the signal that shuts down the semiconductor element to the OUT terminal regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

The control transition signal is input to the IN terminal during the ASC mode. The modulation circuits 11, 12 generate the modulation signal including the burst pulse by performing the edge trigger modulation on the control transition signal. The modulation signals generated by the modulation circuits 11, 12 are provided to the demodulation circuits 51, 52 through the signal transmission circuit 3, respectively.

The demodulation circuits 51, 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11, 12 to an S terminal and a R terminal of the pulse restoration circuit 61, respectively. In addition, the demodulation circuits 51, 52 output the edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11, 12 to the OR circuit 70.

The pulse restoration circuit 62 generates the signal having substantially the same waveform as the control transition signal input to the primary circuit 1 based on the edge trigger signal output from the demodulation circuits 51, 52, and outputs the signal from the Q terminal to the waveform shaping circuit 72. The signal output from the pulse restoration circuit 62 has the frequency equal to or higher than the threshold, so that the waveform shaping circuit 72 generates the second transmission control signal that is the square wave signal based on the signal, and outputs the second transmission control signal to the logic circuit 65.

The OR circuit 70 outputs the OR signal of the edge trigger signals output from the demodulation circuits 51, 52 to the ASC mode determination circuit 63. Similarly to the transmission transition signal of the third preferred embodiment, the ASC mode determination circuit 63 counts the pulses of the OR signal including the burst pulse predetermined N times within the determination cycle, and thus determines that the ASC mode is executed.

The subsequent ASC mode according to the third preferred embodiment is similar to the ASC mode according to the third preferred embodiment. That is, the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

When the ASC mode determination circuit 63 determines that the ASC mode is executed and when the abnormality detection and protection operation circuit 64 detects the abnormality of the semiconductor element, the logic circuit 65 outputs the driving signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and to the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary circuit 1.

Summary of Fourth Preferred Embodiment

According to the semiconductor element driving apparatus of the fourth preferred embodiment, similarly to the first to third preferred embodiment, the ASC mode determination circuit 63 of the secondary circuit 5 determines whether the normal mode or the ASC mode is executed based on the transmission transition signal corresponding to the transition signal. According to such a configuration, the secondary circuit 5 can make the operation in the ASC mode during the abnormality detection different from the operation during the normal mode during the abnormality detection based on the determination result of the ASC mode determination circuit 63.

Furthermore, according to the fourth preferred embodiment, the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 can be reduced from the configuration of the third preferred embodiment, the reduction in the area and the number of components of the semiconductor element driving apparatus can be expected.

The preferred embodiments can be freely combined, and the preferred embodiments can be appropriately modified or omitted.

Hereinafter, various aspects of the present disclosure will be collectively described as appendixes.

(Appendix 1)

A semiconductor element driving apparatus comprising:

- a primary circuit to which a plurality of signals including a first control signal controlling driving of a semiconductor element during a normal mode, a second control signal controlling driving of the semiconductor element during an ASC mode, and a transition signal transitioning from the normal mode to the ASC mode, or including the first control signal and a control transition signal corresponding to the second control signal and to the transition signal are input;
- a signal transmission circuit including an insulating element capable of transmitting a signal; and
- a secondary circuit that drives the semiconductor element based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary circuit through the signal transmission circuit,
- wherein the secondary circuit includes:
  - an ASC mode determination circuit that determines whether the normal mode or the ASC mode is executed based on a transmission transition signal corresponding to the transition signal or to the control transition signal among the plurality of transmission signals; and
  - a logic circuit that drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the plurality of transmission signals when the ASC mode determination circuit determines that the normal mode is executed, and drives the semiconductor element based on a second transmission control signal corresponding to the second control signal or to the control transition signal among the plurality of transmission signals when the ASC mode determination circuit determines that the ASC mode is executed.
    
    (Appendix 2)

The semiconductor element driving apparatus according to appendix 1, wherein

- the transmission transition signal includes a burst pulse, and
- the ASC mode determination circuit determines that the ASC mode is executed when the pulse of the transmission transition signal is counted a predetermined number of times within a predetermined period.
  
  (Appendix 3)

The semiconductor element driving apparatus according to appendix 1 or 2, wherein