146 may be a programmable logic device, a microcontroller, a microprocessor, or any suitable combination of the preceding. The one or more processors are configured to process data and may be implemented in hardware or software. For example, the processor 146 may be 8-bit, 16-bit, 32-bit, 64-bit, or of any other suitable architecture. The one or more processors are configured to implement various software instructions to perform the operations described herein. For example, the one or more processors are configured to execute software instructions 166 to implement the machine learning (ML) module 148 and perform one or more functions described herein. In this way, processor 146 may be a special-purpose computer designed to implement the functions disclosed herein.

Network interface 144 is configured to enable wired and/or wireless communications (e.g., via network 102). The network interface 144 is configured to communicate data between the image creation system 142 and other components of the system 100. For example, the network interface 144 may comprise a WIFI interface, a local area network (LAN) interface, a wide area network (WAN) interface, a modem, a switch, or a router. The processor 146 is configured to send and receive data using the network interface 144. The network interface 144 may be configured to use any suitable type of communication protocol as would be appreciated by one of ordinary skill in the art.

Memory 164 may be volatile or non-volatile and may comprise a read-only memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), dynamic random-access memory (DRAM), and static random-access memory (SRAM). Memory 164 may be implemented using one or more disks, tape drives, solid-state drives, and/or the like. Memory 164 is operable to store software instructions 166, and/or any other data and instructions. The software instructions 166 may comprise any suitable set of software instructions, logic, rules, or code.

Memory 164 may comprise a code repository 168. The code repository 168 may store the latest versions of the server images 170. In certain embodiments, the latest versions of the server images 170 may comprise the latest version of the application server image, the latest version of the middleware server image, and/or the latest version of the database server image.

The image creation system 142 may be configured to create a performance-optimized version of a server image 158 from the latest version of the server image 170 based on the performance of the servers 104. In certain embodiments, the image creation system 142 may be configured to receive the logs 140 from the monitoring and logging system 118 and determine current values for the performance parameters of the servers 104 based on the logs 140. The performance parameters may comprise an input-output operations per second (IOPS) performance, a response time, a computing performance, and/or a number of error messages for a pre-determined time interval. The current values for the performance parameters 150 are compared to optimal values for the performance parameters 154 to determine incremental changes 156 that are to be applied to the latest version of the server image 170. The incremental changes 156 may comprise incremental changes to memory allocation parameters, processor allocation parameters, and/or network bandwidth allocation parameters. The incremental changes 156 are applied to the latest version of the server image 170 to create the performance-optimized version of the server image 158. The performance-optimized version of the server image 158 may be stored in the code repository 168 of the image creation system 142. The performance-optimized version of the server image 158 may be also stored in the code repository system 172.

Machine Learning Module

Machine learning (ML) module 148 may be implemented by the processor 146 executing the software instructions 166 and is generally configured to create a performance-optimized image of a server. In certain embodiments, the processor 146 may execute the operations described herein as being associated with the ML module 148 without implementing the ML module 148 itself.

In certain embodiments, the ML module 148 may be implemented by a support vector machine, neural network, random forest, k-means clustering, etc. In certain embodiments, the ML module 148 may be implemented by a plurality of neural network layers, convolutional neural network layers, Long-Short-Term-Memory (LSTM) layers, Bi-directional LSTM layers, recurrent neural network layers, and the like. In certain embodiments, the ML module 148 may be implemented by a text processing, natural language processing, and the like. In certain embodiments, the ML module 148 may be implemented by unsupervised, semi-supervised, and/or supervised machine learning techniques.

In certain embodiments, the ML module 148 may be implemented by a machine learning algorithm that is executed by processor 146. Machine learning algorithm may be any suitable machine learning algorithm, such as a neural network machine learning algorithm, a naïve bayes algorithm, a nearest neighbor algorithm, a support vector machine, and/or any other suitable machine learning algorithm. Machine learning algorithm may be a supervised machine learning algorithm, an unsupervised machine learning algorithm, a semi-supervised learning algorithm, or a reinforcement learning algorithm.

In certain embodiments, the ML module 148 may be configured to perform operations of method 200 (see FIGS. 2A and 2B) as described below in greater detail. In other embodiments, the processor 146 may be configured to perform operations of the method 200 without implementing the ML module 148 itself.

Code Repository System

Code repository system 172 is generally any device that is configured to process data and communicate with other components of the system 100 via the network 102. The code repository system 172 may comprise a processor 174 in signal communication with a memory 178 and a network interface 176. The code repository system 172 may be also referred to as a central code repository system.

Processor 174 comprises one or more processors operably coupled to the memory 178. The processor 174 is any electronic circuitry, including, but not limited to, state machines, one or more central processing unit (CPU) chips, logic units, cores (e.g., a multi-core processor), field-programmable gate array (FPGAs), application-specific integrated circuits (ASICs), or digital signal processors (DSPs). The processor 174 may be a programmable logic device, a microcontroller, a microprocessor, or any suitable combination of the preceding. The one or more processors are configured to process data and may be implemented in hardware or software. For example, the processor 174 may be 8-bit, 16-bit, 32-bit, 64-bit, or of any other suitable architecture. The one or more processors are configured to implement various software instructions to perform the operations described herein. For example, the one or more processors are configured to execute software instructions 180 and perform one or more functions described herein.

Network interface 176 is configured to enable wired and/or wireless communications (e.g., via network 102). The network interface 176 is configured to communicate data between the code repository system 172 and other components of the system 100. For example, the network interface 176 may comprise a WIFI interface, a local area network (LAN) interface, a wide area network (WAN) interface, a modem, a switch, or a router. The processor 174 is configured to send and receive data using the network interface 176. The network interface 176 may be configured to use any suitable type of communication protocol as would be appreciated by one of ordinary skill in the art.

Memory 178 may be volatile or non-volatile and may comprise a read-only memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), dynamic random-access memory (DRAM), and static random-access memory (SRAM). Memory 178 may be implemented using one or more disks, tape drives, solid-state drives, and/or the like. Memory 178 is operable to store software instructions 180, and/or any other data and instructions. The software instructions 180 may comprise any suitable set of software instructions, logic, rules, or code. Memory 178 may be further operable to store the latest versions of the server images 170 and the performance-optimized versions of the server images 158.

Provisioning System

Provisioning system 182 is generally any device that is configured to process data and communicate with other components of the system 100 via the network 102. The provisioning system 182 may comprise a processor 184 in signal communication with a memory 188 and a network interface 186.

Processor 184 comprises one or more processors operably coupled to the memory 188. The processor 184 is any electronic circuitry, including, but not limited to, state machines, one or more central processing unit (CPU) chips, logic units, cores (e.g., a multi-core processor), field-programmable gate array (FPGAs), application-specific integrated circuits (ASICs), or digital signal processors (DSPs). The processor 184 may be a programmable logic device, a microcontroller, a microprocessor, or any suitable combination of the preceding. The one or more processors are configured to process data and may be implemented in hardware or software. For example, the processor 184 may be 8-bit, 16-bit, 32-bit, 64-bit, or of any other suitable architecture. The one or more processors are configured to implement various software instructions to perform the operations described herein. For example, the one or more processors are configured to execute software instructions 190 and perform one or more functions described herein.

Network interface 186 is configured to enable wired and/or wireless communications (e.g., via network 102). The network interface 186 is configured to communicate data between the provisioning system 182 and other components of the system 100. For example, the network interface 186 may comprise a WIFI interface, a local area network (LAN) interface, a wide area network (WAN) interface, a modem, a switch, or a router. The processor 184 is configured to send and receive data using the network interface 186. The network interface 186 may be configured to use any suitable type of communication protocol as would be appreciated by one of ordinary skill in the art.

Memory 188 may be volatile or non-volatile and may comprise a read-only memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), dynamic random-access memory (DRAM), and static random-access memory (SRAM). Memory 188 may be implemented using one or more disks, tape drives, solid-state drives, and/or the like. Memory 188 is operable to store software instructions 190, and/or any other data and instructions. The software instructions 190 may comprise any suitable set of software instructions, logic, rules, or code.

The provisioning system 182 may be configured to receive the performance-optimized versions of the server images 158 from the code repository system 172 and store them in the memory 188. The provisioning system 182 may be further configured to provision new servers (e.g., new server 192) with the performance-optimized versions of the server images 158.

New Server

New server 192 is generally any device that is configured to process data and communicate with other components of the system 100 via the network 102. The new server 192 may be an application server, a middleware server, or a database server. The new server 192 may comprise a processor 194 in signal communication with a memory 198 and a network interface 196.

Processor 194 comprises one or more processors operably coupled to the memory 198. The processor 194 is any electronic circuitry, including, but not limited to, state machines, one or more central processing unit (CPU) chips, logic units, cores (e.g., a multi-core processor), field-programmable gate array (FPGAs), application-specific integrated circuits (ASICs), or digital signal processors (DSPs). The processor 194 may be a programmable logic device, a microcontroller, a microprocessor, or any suitable combination of the preceding. The one or more processors are configured to process data and may be implemented in hardware or software. For example, the processor 194 may be 8-bit, 16-bit, 32-bit, 64-bit, or of any other suitable architecture. The one or more processors are configured to implement various software instructions to perform the operations described herein. For example, the one or more processors are configured to execute software instructions 199 and perform one or more functions described herein.

Network interface 196 is configured to enable wired and/or wireless communications (e.g., via network 102). The network interface 196 is configured to communicate data between the new server 192 and other components of the system 100. For example, the network interface 196 may comprise a WIFI interface, a local area network (LAN) interface, a wide area network (WAN) interface, a modem, a switch, or a router. The processor 194 is configured to send and receive data using the network interface 196. The network interface 196 may be configured to use any suitable type of communication protocol as would be appreciated by one of ordinary skill in the art.

Memory 198 may be volatile or non-volatile and may comprise a read-only memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), dynamic random-access memory (DRAM), and static random-access memory (SRAM). Memory 198 may be implemented using one or more disks, tape drives, solid-state drives, and/or the like. Memory 198 is operable to store software instructions 199, and/or any other data and instructions. The software instructions 199 may comprise any suitable set of software instructions, logic, rules, or code.

In certain embodiments, the new server 192 is provisioned by the provisioning system 182 with the performance-optimized version of the server image 158. In such embodiments, the memory 198 may further store the performance-optimized version of the server image 158. The new server 192 may be added to the plurality of servers 104 and may be integrated into the full-stack environment.