Referring to FIG. 2, for example, in a positive half cycle when the power output stage circuit 110 is configured to operate (for the waveform Spwm-A, the positive half cycle is the time point P1 to the time point P3), the control signal Spwm1 is at the high level and the ramp voltage Vramp is less than the response voltage Vea, the high-side switch Ta is turned on and the low-side switch Tb is turned off. The input voltage Vin charges the output capacitor Cout and the inductor L1 to form an output current Is1 flowing from the phase node N1 to the output capacitor Cout. Then, the current detection circuit 121 receives the voltages Lx1~Lxn of the phase nodes N1~Nn and calculates the output currents Is1~Isn according to the voltages Lx1~Lxn. As shown in FIG. 1B and FIG. 2, the current detection circuit 121 compares the output currents Is1~Isn with the current average of these currents (i.e., the average current Iavg, or the aforementioned threshold current). For example, when the output current Is1 is greater than the average current Iavg, the duty cycle of the control signal Spwm1 should be decreased to decrease the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 delays a time point at which the control signal Spwm1 increase from low level to high level (e.g., as shown in the waveform Spwm-B, the time point is delayed from the time point P1 to the time point P2) to decrease the duty cycle of the control signal Spwm1. Accordingly, by decreasing the duty cycle of the control signal Spwm1, the time during which the high-side switch Ta is turned on is shortened, thereby decreasing the output current Is1.

Similarly, when the output current Is1 is less than the average current Iavg, the duty cycle of the control signal Spwm1 should be increased to increase the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 delays the time point at which the control signal Spwm1 decreases from the high level to the low level (for example, as shown in the waveform Spwm-C, the time point is delayed from the time point P3 to the time point P4) to increase the duty cycle of the control signal Spwm1. Accordingly, by increasing the duty cycle of the control signal Spwm1, the time during which the high-side switch Ta is turned on becomes longer, thereby increasing the output current Is1.

The following describes the method and corresponding circuit of the voltage regulator circuit 200 configured to adjust the time point at which the levels of the control signals Spwm1~Spwmn are changed. As shown in FIG. 1A, the voltage regulator circuit 200 comprises a current comparison circuit 210 and a delay circuit 220, and the current comparison circuit 210 is coupled to the delay circuit 220. The current comparison circuit 210 is coupled to the current detection circuit 121 to obtain one error signal. For example, the current comparison circuit 210 receives the corresponding one of the error currents Idiff1~Idiffn from the current detection circuit 121, or receives the threshold current (e.g., the average current, referring to the average current Iavg in FIG. 3A) and the corresponding output current (referring to the output current Is1 in FIG. 3A) from the current detection circuit 121.

The delay circuit 220 is coupled to the compensation circuit 130 and the current comparison circuit 210, and is configured to generate the corresponding control signal according to the compensation signal Vcomp. The delay circuit 220 is further configured to adjust a bias current in the delay circuit according to the error signal (e.g., a corresponding error current Idiff1, or the average current Iavg and the output current Is1 as shown in the subsequent FIG. 1B and FIG. 3A) to adjust the duty cycle of the corresponding control signal.

The present disclosure uses the error signals to confirm the current status of the respective output currents corresponding to different phases (e.g., too large or too small), and then selectively changes the time points at which the levels of the corresponding control signal are changed, such as changing the time point at which the control signal enters the high level, or changing the time point at which the control signal enters the low level. Accordingly, the duty cycle of the control signal can be adjusted to achieve the purpose of maintaining balance among currents corresponding to different phases.

In some embodiments, the multi-phase DC-DC converter 100 achieves the purpose of “controlling the time points at which levels of signals are changed” by controlling phases of signals at control nodes in the delay circuits 220. In other embodiments, the multi-phase DC-DC converter 100 achieves the purpose of “controlling the time points at which levels of signals are changed” by controlling threshold voltages of circuit elements in the delay circuit 220. Each control method of the present disclosure will be explained through the embodiments in FIGS. 3A, 3B, 4A, and 4B.

FIG. 3A is a schematic diagram of a voltage regulator circuit 300 in some embodiments of the present disclosure, which can be applied to the multi-phase DC-DC converter 100 shown in FIG. 1A. The voltage regulator circuit shown in FIG. 3A can be an example of the voltage regulator circuit 200 shown in FIG. 1A. The voltage regulator circuit 300 comprises a current comparison circuit 310 and a delay circuit 320. The current comparison circuit 310 is coupled to the delay circuit 320. The current comparison circuit 310 is coupled to the current detection circuit 121, and is configured to receive the average current Iavg and the output current Is1. The delay circuit 320 is coupled to the compensation circuit 130 and the current comparison circuit 310, and adjusts a phase of a signal (referred to as a node signal S3) at a control node NA in the delay circuit 320 according to the error signal to adjust the duty cycle of the corresponding control signal. The current comparison circuit 310 and the delay circuit 320 may be examples of the current comparison circuit 210 and the delay circuit 220, respectively.

As shown in FIG. 3A, in one embodiment, the current comparison circuit 310 comprises a first current comparator 311. The first current comparator 311 is coupled to the current detection circuit 121. A first terminal (e.g., a negative terminal) of the first current comparator 311 is configured to receive the threshold current (the average current Iavg in this embodiment). A second terminal (e.g., a positive terminal) of the first current comparator 311 is configured to receive the corresponding output current Is1. The first current comparator 311 generates a first error signal S1 according to a difference between the average current Iavg and the output current Is1.

As mentioned above, in one embodiment, the delay circuit 320 comprises a first current source circuit 321 which is configured to provide a first bias current Ib1 according to the power supply Vcc. The first current source circuit 321 is further configured to receive the first error signal S1 generated by the first current comparator 311, and change the intensity of the output first bias current Ib1 according to the first error signal S1. In some embodiments, the first error signal S1 can be a voltage signal, and is configured to change the intensity of the first bias current Ib1.

Similarly, in one embodiment, the current comparison circuit 310 further comprises a second current comparator 312. The second current comparator 312 is coupled to the current detection circuit 121 and an inverter 323. A first terminal (e.g., a negative terminal) of the second current comparator 312 is configured to receive the corresponding output current Is1. A second terminal (e.g., a positive terminal) of the second current comparator 312 is configured to receive the threshold current (the average current Iavg in this embodiment). The second current comparator 312 generates the second error signal S2 according to a difference between the average current Iavg and the output current Is1.

As mentioned above, the delay circuit 320 further comprises a second current source circuit 322 which is configured to provide a second bias current Ib2 according to the power supply Vcc. The second current source circuit 322 is coupled to the second current comparator 312 and the inverter 323. The second current source circuit 322 is configured to receive the second error signal S2 generated by the second current comparator 312, and change the intensity of the output second bias current Ib2 according to the second error signal S2. It is worth mentioning here that both of the first current comparator 311 and the second current comparator 312 are configured to receive the corresponding output current Is1 and the average current Iavg, but the receiving positions (i.e., the positive and negative terminals) are opposite, so the first error signal S1 and the second error signal S2 will have different logic levels. In some other embodiments, the current comparison circuit 310 can be omitted. Under this configuration, the first current source circuit 321 and the second current source circuit 322 can be directly coupled to the current detection circuit 121 to receive the corresponding one of the error currents Idiff1~Idiffn, such as the error current Idiff1 Then, the first current source circuit 321 directly uses the error current Idiff1 as the first error signal S1, and the second current source circuit 322 uses the current inverse to the error current Idiff1 as the second error signal S2. Or, the first current source circuit 321 directly uses the error current Idiff1 as the second error signal S2, and the second current source circuit 322 uses the current inverse to the error current Idiff1 as the first error signal S1.

Specifically, as shown in FIG. 3A, the delay circuit 320 comprises the inverter 323, and further comprises a delay capacitor C31 and a hysteresis comparator 324. An input terminal of the inverter 323 is coupled to the output terminal of the compensation circuit 130, and is configured to receive the compensation signal Vcomp. An output terminal of the the inverter 323 is coupled to the control node NA to output the node signal S3. A first correction terminal of the inverter 323 is coupled to the first current source circuit 321 to receive the first bias current Ib1. A second correction terminal of the inverter 323 is coupled to the second current source circuit 322 to receive the second bias current Ib2. The inverter 323 is configured to control charge or discharge of the delay capacitor C31 according to the first bias current and/or the second bias current control to adjust the phase of the node signal S3 of the control node NA.

The delay capacitor C31 is coupled between the output terminal (e.g., the control node NA) of the inverter 323 and a reference terminal (e.g., ground). When the first error signal S1 is at a high level, the delay capacitor C31 is configured to delay a time point at which the node signal S3 is changed from a high logic level to a low logic level. When the first error signal S1 is at a low level, the delay capacitor C31 is configured to delay a time point at which the node signal S3 is changed from the low logic level to the high logic level.

The hysteresis comparator 324 is coupled to the output terminal of the inverter 323 (that is, the control node NA), and is configured to generate the corresponding control signal Spwm1 according to the node signal S3. In one embodiment, the hysteresis comparator 324 can be implemented by a Schmitt trigger.

FIG. 3B is a voltage characteristic diagram of a hysteresis comparator 324 in some embodiments of the present disclosure. The horizontal axis represents the input voltage (i.e., the node signal S3) received by the hysteresis comparator 324, and the vertical axis represents the output voltage (i.e., the control signal Spwm1) output by the hysteresis comparator 324. The voltage characteristics of the hysteresis comparator 324 show a hysteresis curve. When the input voltage of the hysteresis comparator 324 increases to a first threshold voltage VTH, the output voltage is changed to a low level (e.g., shown in characteristic curve L31). When the input voltage of the hysteresis comparator 324 decreases to a second threshold voltage VTL, the output voltage is changedl changed to a high level (e.g., as shown in characteristic curve L32). When the input voltage of the hysteresis comparator 324 is between the first threshold voltage VTH and the second threshold voltage VTL, the output voltage is not changed. Since people in the art can understand the characteristics and implementation of the hysteresis comparator 324, it will not be described here.

Referring to FIGS. 1A, 2 and 3A~3B, the following describes the operation of the delay circuit 320 that adjusts the bias current in the delay circuit according to the error signal, thereby changing the duty cycle of the corresponding control signal. As shown in FIG. 2, when the power output stage circuit operates in the positive half cycle, that is, when the response voltage Vea is greater than the ramp voltage Vramp, the compensation signal Vcomp is at a high level, and the node signal S3 output by the inverter 323 should change to the low logic level. If the output current Is1 is greater than the average current Iavg at this time, then the first error signal S1 is at a high level, and the second error signal S2 is at a low level. Thereby, the first current source circuit 321 is controlled to increase the first bias current Ib1, and the second current source circuit 322 is controlled to decrease the second bias current Ib2. When the first bias current Ib1 becomes larger and the second bias current Ib2 becomes smaller, the delay capacitor C31 will be additionally charged. Therefore, the time point at which the node signal S3 decreases to the low logic level (to at least the second threshold voltage VTL) will become slower. That is, the time point at which the hysteresis comparator 324 converts the received node signal S3 with the low logic level into the control signal Spwm1 with the high level will be delayed. As shown in the waveform Spwm-B shown in FIG. 2, the time point at which the control signal Spwm1 increases to the high level will be delayed from the original time point P1 to the time point P2. Accordingly, it is equivalent to decreasing the duty cycle of the control signal Spwm1. When the duty cycle of the control signal Spwm1 decreases, the time during which the high-side switch Ta is turned on becomes shorter, thus decreasing the output current Is1, achieving the purpose of maintaining balance among currents corresponding to different phases.

As for the power output stage circuit 110 operating in the positive half cycle, refer to the waveform Spwm-C, if the output current Is1 is less than the average current Iavg, the first bias current Ib1 will decrease and the second bias current Ib2 will increase, and the delay capacitor C31 will be discharged smoothly, so the time at which the node signal S3 is switched to the low logic level (to at least the second threshold voltage VTL) is not affected. That is, the time point at which the control signal Spwm1 is switched to the high level is not affected, so in the positive half cycle, the time point at which the waveform Spwm-C is switched to the high level is the same as the time point at which the waveform Spwm-A is switched to the high level.

Next, as shown in FIG. 2, when the power output stage circuit 110 operates in a negative half cycle, that is, when the response voltage Vea is less than the ramp voltage Vramp, the compensation signal Vcomp is at the low level, and the node signal S3 output by the inverter 323 should be changed to the high logic level. If the output current Is1 is less than the average current Iavg at this time, then the first error signal S1 is at the low level and the second error signal S2 is at the high level, so that the first current source circuit 321 is controlled to decrease the first bias current Ib1 and the second current source circuit 322 is controlled to increase the second bias current Ib2. When the first bias current Ib1 becomes smaller and the second bias current Ib2 becomes larger, the delay capacitor C31 will be additionally discharged. Therefore, the time point at which the level of the node signal S3 increases to the high logic level (to at least the first threshold voltage VTH to make the output voltage of the hysteresis comparator 324 changed, refer to the principle shown in FIG. 3B) will become slower. That is, the time point at which the hysteresis comparator 324 converts the received node signal S3 with the high logic level into the control signal Spwm1 with the low level will be delayed, as shown in the waveform Spwm-C shown in FIG. 2, at this time, the time point at which the control signal Spwm1 decreases to the low level will be delayed from the original time point P3 to the time point P4. Accordingly, it is equivalent to increasing the duty cycle of the control signal Spwm1. When the duty cycle of the control signal Spwm1 increases, the time during which the high-side switch Ta is turned on becomes longer, thus increasing the output current Is1 to achieve the purpose of maintaining balance among currents corresponding to different phases.

As for the power output stage circuit 110 operating in the negative half cycle, if the output current Is1 is greater than the average current Iavg, the first bias current Ib1 will increase and the second bias current Ib2 will decrease, so that the delay capacitor C31 will be charged smoothly. Therefore, the time point at which the node signal S3 is switched to the high logic level (to at least the first threshold voltage VTH) is not affected, so the time point at which the waveform Spwm-B is switched to the low level is the same as the time point at which the waveform Spwm-A is switched to the low level in the negative half cycle.

In the aforementioned embodiments, the voltage regulator circuit 300 comprises the first current comparator 311, the second current comparator 312, the first current source circuit 321 and the second current source circuit 322. The first current comparator 311 and the corresponding first current source circuit 321 are configured to generate the first bias current Ib1 to change a change time of the phase of the node signal S3 at the control node NA. Similarly, the second current comparator 312 and the corresponding second current source circuit 322 are configured to generated the second bias current Ib2 to change the change time of the phase of the node signal S3 at the control node NA. However, in other embodiments, the voltage regulator circuit 300 may have the first bias current Ib1 or the second bias current Ib2, which can change the change time of the phase of the node signal S3 at the control node NA. In other words, in other embodiments, the voltage regulator circuit 300 may only comprise the first current comparator 311 and the corresponding first current source circuit 321, or only comprise the second current comparator 312 and the corresponding second current source circuit 322.

FIG. 4A is a schematic diagram of a voltage regulator circuit 400 in some embodiments of the present disclosure, which can be applied to the multi-phase DC-DC converter 100 shown in FIG. 1A. The voltage regulator circuit shown in FIG. 4A can be an example of the voltage regulator circuit 200 shown in FIG. 1A. The voltage regulator circuit 400 comprises a current comparison circuit 410 and a delay circuit 420. The current comparison circuit 410 is coupled to the current detection circuit 121, and is configured to receive the error signal. The delay circuit 420 is coupled to the compensation circuit 130 and the current comparison circuit 410 to adjust a phase of a node signal S4 at a control node NA in the delay circuit 420 according to the error signal, thereby adjusting the duty cycle of the corresponding control signal Spwm1. The current comparison circuit 410 and the delay circuit 420 may be examples of the current comparison circuit 210 and the delay circuit 220 respectively.

As shown in FIG. 4A, in one embodiment, the current comparison circuit 410 comprises a first current comparator 411 and a second current comparator 412, and the delay circuit 420 comprises a first current source circuit 421 and a second current source circuit 422.

The first current comparator 411 is configured to receive the average current Iavg and the corresponding output current Is1