31, adjusting the measurements and determined value based on the detected temperature from temperature sensor 36, temperature sensor 37, and the previously characterized temperature coefficients for load resistor 33 and sense resistor 35. It should be appreciated that in alternative embodiments, RDSon for DUT 31 may be determined without factoring in temperature. It should also be appreciated that in alternative embodiments, the voltage/current provided by power supply 32 to DUT 31 and/or, the voltage/current provided at the gate of DUT 31 by DMU 34 may vary based on the test being run and the specific DUT 31 being tested.

FIG. 4 is a schematic generally illustrating a test system 40 for testing a semiconductor transistor to measure RDSoff during high voltage while the transistor is turned off, according to an embodiment of the invention. FIG. 4 includes “device under test” 41 (also referred to as a “DUT”) connected to test system 40 that is to have various parameters tested by the test system 40. In the embodiment of FIG. 4, DUT 41 is a gallium nitride GaN/MOSFET transistor. Test system 40 is configured such that DUT 41 may be removed and replaced with other GaNs or MOSFET transistors or DUT 41s that are to be tested. In other words, DUT 41 is removable and replaceable within test system 40 so that test system 40 may test other GaNs or MOSFET transistors, other transistors, or other devices.

As shown, DMU 44 is electrically connected to the gate of DUT 41, and is configured to provide current and/or voltage to DUT 41. Test system 40 is further shown electrically connected to the source of DUT 41, and is configured to provide the reference voltage for gate drive level to DUT 41 via that connection. Test system 40 is further shown electrically connected to the source of DUT 41, and is configured to provide ground to DUT 41 via that connection. Power supply 42 is further shown electrically connected to the drain of DUT 41 through coupling load resistor 43, and is configured to provide current and/or voltage to DUT 41 via that connection.

In this embodiment, prior to testing, DMU 44 is configured to provide a voltage to the gate of DUT 41 such that DUT 41 enters the “off” state. In an alternative embodiment, turning DUT 41 into the off state may also be accomplished by connecting the DUT 41 gate to the DUT 41 source. Test system 40 is also shown having a high voltage power supply 42 for providing power to DUT 41, and a load resistor 43 through which power is supplied to DUT 41 by power supply 42. In the embodiment of FIG. 4, power supply 42 is a high voltage power supply configured to provide at least 1 KV at 20 A. It should be appreciated that in other embodiments, power supply 42 may be configured to provide various voltages, currents, and power levels. In the embodiment of FIG. 4, load resistor 43 is used to limit the current through the transistor when it is on (conducting), and has a resistance value of 100 mΩ and is rated at 100 W. In alternative embodiments, load resistor 43 may have other resistance values, and may be rated for different wattages. As shown, once DUT 41 is in the off state, power supply 42 supplies power to the drain of DUT 41 through load resistor 43. In the embodiment of FIG. 4, power supply 42 is adjusted to provide a voltage according to the specification of the DUT. In its off state, the transistor is specified to ideally allow no current flow. This spec is typically called Drain-to-Source Voltage (Continuous). If the DUT fails this test, we measure a voltage drop across the sense resistor and determine the leakage current using Ohm's Law. In alternative embodiments, power supply 42 may be adjusted to provide other voltages, including voltages that are in excess of the normal operating voltage of DUT 41. FIG. 4 also generally illustrates test system 40 including a sense resistor 45. As shown, the source of DUT 41 is coupled to ground through the sense resistor 45. In the embodiment of FIG. 4, sense resistor 45 has a resistance value of 10 mΩ and is rated at 10 W. As shown, test system 40 also includes a dynamic measurement unit (“DMU”) 44. DMU 44 is configured to provide current and voltage to DUT 41, take fast, high-accuracy measurements of current and voltage associated with DUT 41 (for example, comprising a microvoltmeter or a digitizer capable of quickly and accurately measuring low level voltages), monitor the temperature provided by temperature sensors of test system 40, and store and process these data. DMU 44 is shown electrically connected to sense resistor 45 by two electrical connections, one between each terminal of sense resistor 45 and DMU 44, for the measurement of parameters (voltage and/or current) associated with sense resistor 45.

Test system 40 further includes a temperature sensor 46 and a temperature sensor 47. Temperature sensor 46 is located near load resistor 43, and is electrically connected to DMU 44. Temperature sensor 47 is located near sense resistor 45 and is also electrically connected to DMU 44.

In the embodiment of FIG. 4, prior to beginning a test of DUT 41, the resistance values of load resistor 43 and sense resistor 45 are characterized to record thermal coefficients for the resistance values for each resistor as those resistance values vary with temperature. Those thermal coefficients are stored in memory of the DMU 44 for use during the test of DUT 41 to adjust calculations based on the temperature detected by temperature sensor 46 and temperature sensor 47 of the resistors to which they correspond. More specifically, during testing, DMU 44 monitors the temperature of load resistor 43 and sense resistor 45, and adjusts the stored values of load resistor 43 and sense resistor 45, used to calculate RDSon and RDSoff, to compensate for temperature changes.

While DUT 41 is in the “off” state and power supply 42 is supplying the required voltage, DMU 44 measures the voltage across sense resistor 45, and determines RDSoff for DUT 41, adjusting the measurements and determined value based on the detected temperature from temperature sensor 46, temperature sensor 47, and the previously characterized temperature coefficients for load resistor 43 and sense resistor 45. It should be appreciated that in alternative embodiments, RDSon for DUT 41 may be determined without factoring in temperature. It should also be appreciated that in alternative embodiments, the voltage/current provided by power supply 42 to DUT 41 and/or, the voltage/current provided at the gate of DUT 41 by DMU 44 may vary based on the test being run and the specific DUT 41 being tested. In this embodiment, once RDSoff has been determined, the voltage supplied by power supply 42 is ramped back down to safe operating voltage of DUT 41, typically 0V.

FIG. 5 is a schematic generally illustrating a test system 50 for testing a semiconductor transistor to measure RDSon at normal operating voltage while the transistor is turned on, and in conjunction with recovery from current collapse, according to an embodiment of the invention. FIG. 5 includes “device under test” 51 (also referred to as a “DUT”) connected to tests system 50 that is to have various parameters tested by the test system 50. In the embodiment of FIG. 5, DUT 51 is a gallium nitride GaN/MOSFET transistor. Test system 50 is configured such that DUT 51 may be removed and replaced with other GaNs or MOSFET transistors or DUT 51s that are to be tested. In other words, DUT 51 is removable and replaceable within test system 50 so that test system 50 may test other GaNs or MOSFET transistors, other transistors, or other devices.

Test system 50 is also shown having a power supply 52 for providing power to DUT 51, and a load resistor 53 through which power is supplied to DUT 51 by power supply 52. In the embodiment of FIG. 5, power supply 52 is a high current power supply configured to provide at least 60V at 150 A. It should be appreciated that in other embodiments, power supply 52 may be configured to provide various voltages, currents, and power levels. In the embodiment of FIG. 5, load resistor 53 is used to limit the current through the transistor when it is on (conducting), and has a resistance value of 100 mΩ and is rated at 100 W. In alternative embodiments, load resistor 53 may have other resistance values, and may be rated for different wattages. As shown, power supply 52 supplies power to the drain of DUT 51 through load resistor 53. In the embodiment of FIG. 5, power supply 52 is adjusted to provide a voltage of 2.7V. In alternative embodiments, power supply 52 may be adjusted to provide other voltages. FIG. 5 also generally illustrates test system 50 including a sense resistor 55. As shown, the source of DUT 51 is coupled to ground through the sense resistor 55. In the embodiment of FIG. 5, sense resistor 55 has a resistance value of 10 mΩ and is rated at 10 W. As shown, test system 50 also includes a dynamic measurement unit (“DMU”) 54. DMU 54 is configured to provide current and voltage to DUT 51, take fast, high-accuracy measurements of current and voltage associated with DUT 51 (for example, comprising a microvoltmeter or a digitizer capable of quickly and accurately measuring low level voltages), monitor the temperature provided by temperature sensors of test system 50, and store and process these data. DMU 54 is shown electrically connected to sense resistor 55 by two electrical connections, one between each terminal of sense resistor 55 and DMU 54, for the measurement of parameters (voltage and/or current) associated with sense resistor 55.

Test system 50 further includes a temperature sensor 56 and a temperature sensor 57. Temperature sensor 56 is located near load resistor 53, and is electrically connected to DMU 54. Temperature sensor 57 is located near sense resistor 55 and is also electrically connected to DMU 54.

As shown, DMU 54 is electrically connected to the gate of DUT 51, and is configured to provide current and/or voltage to DUT 51. Test system 50 is further shown electrically connected to the source of DUT 51, and is configured to provide the reference voltage for gate drive level to DUT 51 via that connection. Test system 50 is further shown electrically connected to the source of DUT 51, and is configured to provide ground to DUT 51 via that connection. Power supply 52 is further shown electrically connected to the drain of DUT 51 through coupling load resistor 53, and is configured to provide current and/or voltage to DUT 51 via that connection.

In the embodiment of FIG. 5, prior to beginning a test of DUT 51, the resistance values of load resistor 53 and sense resistor 55 are characterized to record thermal coefficients for the resistance values for each resistor as those resistance values vary with temperature. Those thermal coefficients are stored in memory of the DMU 54 for use during the test of DUT 51 to adjust calculations based on the temperature detected by temperature sensor 56 and temperature sensor 57 of the resistors to which they correspond. More specifically, during testing, DMU 54 monitors the temperature of load resistor 53 and sense resistor 55, and adjusts the stored values of load resistor 53 and sense resistor 55, used to calculate RDSon and RDSoff, to compensate for temperature changes.

Once the power supply 52 voltage has reached the desired level (in this case, 2.7V), DMU 54 provide a voltage to the gate of DUT 51 such that DUT 51 enters the “on” state. While DUT 51 is in the “on” state and power supply 52 is supplying the required voltage, DMU 54 measures sequentially (at successive discrete points in time) measures the voltage across sense resistor 55, and determines RDSon for DUT 51 at those multiple, discrete points in time, adjusting the measurements and determined value based on the detected temperature from temperature sensor 56, temperature sensor 57, and the previously characterized temperature coefficients for load resistor 53 and sense resistor 55. It should be appreciated that in alternative embodiments, RDSon for DUT 51 may be determined without factoring in temperature. It should also be appreciated that in alternative embodiments, the voltage/current provided by power supply 52 to DUT 51 and/or, the voltage/current provided at the gate of DUT 51 by DMU 54 may vary based on the test being run and the specific DUT 51 being tested.

By measuring RDSon at discrete points in time until DUT 51 has recovered, test system 50 is configured to determine the recovery time from current collapse for the DUT 51 based on the RDSon measurements over time. In addition, and in an alternative embodiment, because reducing testing time is important, test system 50 may be configured to only measure RDSon for the first portion of the recovery period (for example, 2, 3, 4 or more measurement points where the measurements are completed before the DUT 51 has completed recovery). Test system 50 is then configured, based on a previously determined model for DUT 51 device performance, to use this subset of RDSon points and fit them to the model to predict, based on the subset of points and the model, what the full recovery time would be. In this embodiment, it is possible to determine the recovery time for DUT 51 without actually testing the DUT 51 for the entire recovery time period, saving valuable testing time. This sampling approach is discussed additionally below with respect to FIG. 6.

FIG. 6 is a graph generally illustrating parameters measured, and a resulting best fit projection of future parameters based on measured parameters and a device model, according to an embodiment of the invention. As discussed with each of the previous embodiments, during testing, the DMU (