1 of the second switch cycle is determined by the magnitudes of the cycle detecting current Isen outputted by the processing circuit 120 at least at two time points in the first switch cycle.

Since the actual inductor current is continuous, based on the magnitudes of the cycle detecting current Isen at least at two time points during the previous switch cycle, the slope of the cycle detecting current Isen outputted during the subsequent switch cycle based on the pseudo current may be close to the slope of the actual inductor current during the second switch cycle, thereby improving the accuracy of inductor current detection.

Furthermore, the at least two time points include at least one time point in the second period p2 when the low-side transistor 12 is turned on. In other words, the slope of the cycle detecting current Isen during the first period p1 of the second switch cycle is determined based on the magnitude of the cycle detecting current Isen at least at one time point during the second period p2 of the first switch cycle when the low-side transistor 12 is turned on.

Since the magnitude of the cycle detecting current Isen during the first switch cycle when the low-side transistor 12 is turned on is a precise value which is actually detected by the first detection circuit 110, based on the magnitude of the cycle detecting current Isen at least at one time point during the first switch cycle when the low-side transistor 12 is turned on, the slope of the cycle detecting current Isen during the second switch cycle may be closer to the slope of the actual inductor current during the second switch cycle, thereby further improving the accuracy of inductor current detection.

In the above-mentioned embodiments, the processing circuit 120 is configured to increase the terminal voltage Vc1 established on the first capacitor C1 using the constant current Isr during the first period p1 in the switch cycle of the DC-DC converter, and vary the terminal voltage Vc1 established on the first capacitor C1 with the low-side detecting current Isen1 using the low-side detecting current Isen1 during the second period p2 in the switch cycle of the DC-DC converter, thereby outputting the cycle detecting current Isen based on the terminal voltage Vc1 established on the first capacitor C1 during the switch cycle of the DC-DC converter. This way, the processing circuit 120 may output the cycle detecting current Isen which increases with a constant slope as the actual inductor current during the turn-on period of the high-side transistor 11, and output the accurate low-side detecting current Isen1 provided by the first detection circuit 110 during the turn-on period of the low-side transistor 12. Also, the magnitude of the constant current Isr during the subsequent switch cycle is determined based on the levels of the terminal voltage Vc1 established on the first capacitor C1 at least at two time points during the previous switch cycle, wherein the least two time points include at least one time point during the second period p2 when the low-side transistor 12 is turned on. This way, the slope of the cycle detecting current Isen during the second switch cycle may be close to the slope of the actual inductor current during the second switch cycle, thereby improving the accuracy of inductor current detection.

In some embodiments, the processing circuit 120 is configured to perform the above-mentioned operation during each switch cycle among multiple sets of switch cycles, thereby further improving the accuracy of inductor current detection. In some other embodiments, the processing circuit 120 is configured to perform the above-mentioned operation during two consecutive switch cycles: the first switch cycle and second switch cycle, thereby further improving the accuracy of inductor current detection.

A first implementation method and a second implementation method of determining the magnitude of the constant current Isr during the second switch cycle based on the levels of the terminal voltage Vc1 established on the first capacitor C1 at least at two time points during the first switch cycle are illustrated.

In the first implementation method, the at least two time points are time points in the second period p2 when the low-side transistor 12 is turned on. In other words, the magnitude of the constant current Isr during the second switch cycle is determined based on the levels of the terminal voltage Vc1 established on the first capacitor C1 at least at two time points during the second period p2 of the first switch cycle when the low-side transistor 12 is turned on in the first implementation method.

For example, based on the levels of the terminal voltage Vc1 established on the first capacitor C1 at least at two time points during the second period p2 of the first switch cycle when the low-side transistor 12 is turned on, the negative slope of the terminal voltage Vc1 during the first switch cycle when the low-side transistor 12 is turned on (i.e., the negative slope of the cycle detecting current Isen during the first switch cycle when the low-side transistor 12 is turned on) may be calculated. Next, based on the negative slope of the terminal voltage Vc1 during the first switch cycle when the low-side transistor 12 is turned on, the expected positive slope of the terminal voltage Vc1 during the first period p1 of the second switch cycle (i.e., the expected positive slope of the cycle detecting current Isen during the first period p1 of the second switch cycle) may be calculated. Therefore, the magnitude of the constant current Isr during the second switch cycle may be determined based on the expected positive slope of the terminal voltage Vc1 during the first period p1 in the second switch cycle. This way, the slope of the cycle detecting current Isen during the second switch cycle may be close to the slope of the actual inductor current during the second switch cycle, thereby improving the accuracy of inductor current detection.

The second implementation method of determining the magnitude of the constant current Isr during the second switch cycle based on the levels of the terminal voltage Vc1 established on the first capacitor C1 at least at two time points during the first switch cycle are illustrated in FIG. 2.

FIG. 2 is a diagram illustrating a signal waveform diagram during the operation of the DC-DC converter according to an embodiment of the present invention. FIG. 2 depicts the signal waveforms of the terminal voltage Vc1 established on the first capacitor C1 and the control signal dUG of the high-side transistor 11. It is to be understood that the waveform of the cycle detecting current Isen outputted by the processing circuit 120 and the waveform of the terminal voltage Vc1 are basically identical. Although not depicted in FIG. 2, it is to be understood the control signal dLG of the low-side transistor 12 is at a high level during the second period p2 of each switch cycle so that the low-side transistor 12 may be turned on during the second period p2.

FIG. 2 schematically depicts that the first period p1 is the turn-on period of the high-side transistor 11 and the second period p2 is the turn-off period of the high-side transistor 11. Schematically, the high-side transistor 11 is turned on when the control signal dUG is at a high level, and the high-side transistor 11 is turned off when the control signal dUG is at a low level.

In the second implementation method, the at least two time points further include a first time point t1 during the first period when the high-side transistor 11 is turned on, and the at least one time point during the second period p2 when the low-side transistor 12 is turned on includes a second time point t2. In other words, the magnitude of the constant current Isr during the second switch cycle is determined based on at least the levels of the terminal voltage Vc1 established on the first capacitor C1 at two time points during the first switch cycle, wherein the above-mentioned two time points are the first time point t1 during the first period p1 when the high-side transistor 11 is turned on and the second time point t2 during the second period p2 when the low-side transistor 12 is turned on.

Under such a circumstance, the processing circuit 120 is further configured to adjust the magnitude of the constant current Isr during the second switch cycle based on a first value V1 of the terminal voltage Vc1 established on the first capacitor C1 at the first time point t1 and a second value V2 of the terminal voltage Vc1 established on the first capacitor C1 at the second time point t2. This way, the processing circuit 120 may automatically adjust the magnitude of the constant current Isr during the second switch cycle based on the comparison result between the first value V1 and the second value V2, so that the positive slope of the cycle detecting current Isen during the second switch cycle may be close to the positive slope of the actual inductor current during the second switch cycle, thereby improving the accuracy of inductor current detection.

In some embodiments, in the situation when the first value V1 is larger than the second value V2, the processing circuit 120 is configured to adjust the magnitude of the constant current Isr during the second switch cycle to be smaller than the magnitude of the constant current Isr during the first switch cycle. Also, in the situation when the first value V1 is smaller than the second value V2, the processing circuit 120 is configured to adjust the magnitude of the constant current Isr during the second switch cycle to be larger than the magnitude of the constant current Isr during the first switch cycle.

For illustrative purpose, the following explanation incorporates FIG. 2. FIG. 2 schematically depicts four consecutive switch cycles. From left to right, these four switch cycles sequentially include a switch cycle CYCLE0, a switch cycle CYCLE1, a switch cycle CYCLE2, and a switch cycle CYCLE3.

During the switch cycle CYCLE0, the first value V1 is smaller than the second value V2, which indicates that the positive slope of the terminal voltage Vc1 (or alternatively, the positive slope of the cycle detecting current Isen) during the first period p1 of the switch cycle CYCLE0 may be smaller than the positive slope of the actual inductor current. Therefore, the magnitude of the constant current Isr is increased during the switch cycle CYCLE1 (i.e., the second switch cycle) subsequent to the switch cycle CYCLE0 (i.e., the first switch cycle) for increasing the positive slope of the cycle detecting current Isen during the switch cycle CYCLE1. This way, the positive slope of the cycle detecting current Isen during the switch cycle CYCLE1 may be closer to the positive slope of the actual inductor current.

During the switch cycle CYCLE1, the first value V1 is still smaller than the second value V2, which indicates that the positive slope of the terminal voltage Vc1 (or alternatively, the positive slope of the cycle detecting current Isen) during the first period p1 in the switch cycle CYCLE1 may still be smaller than the positive slope of the actual inductor current. Therefore, the magnitude of the constant current Isr is further increased during the switch cycle CYCLE2 (i.e., the second switch cycle) subsequent to the switch cycle CYCLE1 (i.e., the first switch cycle) for further increasing the positive slope of the cycle detecting current Isen during the switch cycle CYCLE2. This way, the positive slope of the cycle detecting current Isen during the switch cycle CYCLE2 may be closer to the positive slope of the actual inductor current.

During the switch cycle CYCLE2, the first value V1 is larger than the second value V2, which indicates that the positive slope of the terminal voltage Vc1 (or alternatively, the positive slope of the cycle detecting current Isen) during the first period p1 in the switch cycle CYCLE2 may be larger than the positive slope of the actual inductor current. Therefore, the magnitude of the constant current Isr is reduced during the switch cycle CYCLE3 (i.e., the second switch cycle) subsequent to the switch cycle CYCLE2 (i.e., the first switch cycle) for decreasing the positive slope of the cycle detecting current Isen during the switch cycle CYCLE3. This way, the positive slope of the cycle detecting current Isen during the switch cycle CYCLE3 may be closer to the positive slope of the actual inductor current, thereby further improving the accuracy of inductor current detection.

In the embodiment depicted in FIG. 2, the time length Ta between the first time point t1 and the end time te1 of the first period p1 in the first switch cycle is smaller than or equal to a first predetermined time length. By configuring the time length Ta between the first time point t1 and the end time te1 of the first period p1 in the first switch cycle to be smaller than or equal to the first predetermined time length, the first time point t1 may be closer to the end time of the first period p1. In other words, under such a circumstance, the first value V1 of the terminal voltage Vc1 at the first time point t1 may be closer to the extremum of the terminal voltage Vc1 when the high-side transistor 11 is turned on. This way, by adjusting the constant current Isr based on the first value V1, the positive slope of the cycle detecting current Isen during the second switch cycle may be closer to the positive slope of the actual inductor current, thereby further improving the accuracy of inductor current detection.

In some embodiments, the first predetermined time length may be equal to 1/R of the time length of the first period p1 in the first switch cycle, wherein R may be any value between 10 and 100. For example, R may be equal to 10, which means the first predetermined time length is equal to 1/10 of the time length of the first period p1 in the first switch cycle. In some embodiments, the first predetermined time length may have any value between 5 ns and 30 ns, such as 5 ns, 10 ns or 15 ns. Based on the above-mentioned embodiments, the first time point t1 may be closer to the end time of the first period p1, thereby further improving the accuracy of inductor current detection.

In the embodiment depicted in FIG. 1, the first detection circuit 110 includes an operational amplifier 111. Under such a circumstance, the second time point t2 is after the end time te2 of the setting time of the operational amplifier 111 in the first switch cycle, and the time length Tb between the end time te2 of the setting time and the second time point t2 is smaller than or equal to a second predetermined time length, as depicted in FIG. 2.

It is to be understood that the setting time is the time required by the operational amplifier 111 to provide stable output voltages within a designated error margin after receiving stable input voltages. In other words, the low-side detecting current Isen1 outputted by the first detection circuit 110 after the end time te2 of the setting time of the operational amplifier 111 is more accurate.

By configuring the time length Tb between the end time te2 of the setting time and the second time point t2 to be smaller than or equal to the second predetermined time length, the second time point t2 may be closer to the end time te2 of the setting time of the operational amplifier 111. That is, the second time point t2 may be closer to the time point when the first detection circuit 110 starts to output accurate low-side detecting current Isen1. In other words, under such a circumstance, the second value V2 of the terminal voltage Vc1 at the second time point t2 may be closer to the extremum of the terminal voltage Vc1 when varying with the more accurate low-side detecting current Isen1. This way, by adjusting the constant current Isr based on the second value V2, the positive slope of the cycle detecting current Isen during the second switch cycle may be closer to the positive slope of the actual inductor current, thereby further improving the accuracy of inductor current detection.

In some embodiments, the second predetermined time length may be equal to 1/S of the time length of the second period p2 in the first switch cycle, wherein S may be any value between 10 and 100. For example, S may be equal to 10. In some embodiments, the second predetermined time length may have any value between 5 ns and 30 ns, such as 5 ns, 10 ns or 15 ns. Based on the above-mentioned embodiments, the second time point t2 may be closer to the time point when the first detection circuit 110 starts to output accurate low-side detecting current Isen1, thereby further improving the accuracy of inductor current detection.

In another embodiments, the time length Ta between the first time point t1 and the end time te1 of the first period p1 in the first switch cycle is smaller than or equal to the first predetermined time length, the second time point t2 is after the end time te2 of the setting time of the operational amplifier 111 during the first switch cycle, and the time length Tb between the end time te2 of the setting time and the second time point t2 is smaller than or equal to the second predetermined time length. Under such a circumstance, the first value V1 of the terminal voltage Vc1 at the first time point t1 may be closer to the extremum of the terminal voltage Vc1 when the high-side transistor 11 is turned on, and the second value V2 of the terminal voltage Vc1 at the second time point t2 may be closer to the extremum of the terminal voltage Vc1 when varying with the more accurate low-side detecting current Isen1.

Since the extremum of the actual inductor current when the high-side transistor 11 is turned on is essentially the same as the extremum of the actual inductor current when the low-side transistor 12 is turned on, the first value V1 of the terminal voltage Vc1 at the first time point t1 is expected to be essentially the same as the second value V2 of the terminal voltage Vc1 at the second time point t2. In these embodiments, based on the comparison result between the terminal voltages Vc1 at the first time point t1 and at the second time point t2 (not any random two time points) which are expected to be identical, the magnitude of the constant current Isr during the second switch cycle may be adjusted so that the positive slope of the cycle detecting current Isen during the second switch cycle may be closer to the positive slope of the actual inductor current, thereby further improving the accuracy of inductor current detection.

Some embodiments of the processing circuit 120 in the second implementation method are illustrated in FIG. 3. FIG. 3 is a diagram illustrating an implementation of the processing circuit 120 according to an embodiment of the present invention. As depicted in FIG. 3, the processing circuit 120 includes a current-to-voltage converting circuit 1210 and a first switch S1. The current-to-voltage converting circuit 1210 is configured to convert the low-side detecting current Isen1 outputted by the first detection circuit 110 into a voltage. The switch S1 is coupled between the ungrounded second end of the first capacitor C1 and the current-to-voltage converting circuit 1210. The switch S1 is configured to be turned off during the first period p1 and turned on during the second period p2.

In the embodiment depicted in FIG. 3, the first period p1 is the turn-on period of the high-side transistor 11, the second period p2 is the turn-off period of the high-side transistor 11, and the control signal dUG′ of the first switch S1 and the control signal dUG of the high-side transistor 11 have opposite logic-levels. Based on the current-to-voltage converting circuit 1210 and the first switch S1, the processing circuit 120 is configured to vary the terminal voltage Vc1 established on the first capacitor C1 with the low-side detecting current Isen1 using the low-side detecting current Isen1 during the second period p2.

As depicted in FIG. 3, the processing circuit 120 further includes a current source circuit 1220 and a second switch S2. The current source circuit 1220 is configured to provide the constant current Isr. The current source circuit 1220 may include an adjustable current source capable of providing a current of constant magnitude during the first period p1 of the same switch cycle. The adjustable current source may provide currents of different magnitudes during the first periods p1 of different switch cycles. The switch S2 is coupled between the current source circuit 1220 and the ungrounded second end of the first capacitor C1. The switch S2 is configured to be turned on during the first period p1 and turned off during the second period p2.

As depicted in FIG. 3, the first period p1 is the turn-on period of the high-side transistor 11, the second period p2 is the turn-off period of the high-side transistor 11, and the control signal of the second switch S2 may be the control signal dUG of the high-side transistor 11. Based on the current source circuit 1220 and the second switch S2, the processing circuit 120 is configured to increase the terminal voltage Vc1 established on the first capacitor C1 using the constant current Isr during the first period p1.

As depicted in FIG. 3, the processing circuit 120 further includes a voltage-to-current converting circuit 1230 coupled to the ungrounded second end of the first capacitor C1. The voltage-to-current converting circuit 1230 is configured to convert the terminal voltage Vc1 established on the first capacitor C1 into the cycle detecting current Isen. In the above-mentioned embodiments, the processing circuit 120 is able to increase the terminal voltage Vc1 established on the first capacitor C1 using the constant current Isr during the first period p1 as well as vary the terminal voltage Vc1 established on the first capacitor C1 with the low-side detecting current Isen1 using the low-side detecting current Isen1 during the second period p2, thereby outputting the cycle detecting current Isen based on the terminal voltage Vc1 established on the first capacitor C1.

In the embodiment depicted in FIG. 3, the current-to-voltage converting circuit 1210 may include a resistor R1, an operational amplifier OP1 and a transistor TR1. The first end of the resistor R1 is coupled to the first detection circuit 110 for receiving the low-side detecting current Isen1, and the second end of the resistor R1 is coupled to the ground. The positive input end of the operational amplifier OP1 is coupled to the first end of the resistor R1, the negative input end of the operational amplifier OP1 is coupled to the first end of the transistor TR1, and the output end of the operational amplifier OP1 is coupled to the second end of the transistor TR1. The third end of the transistor TR1 is coupled to a power end. Under such a circumstance, the operational amplifier OP1 and the transistor TR1 in the current-to-voltage converting circuit 1210 may function as a voltage buffering circuit between the resistor R1 and the first capacitor C1. This way, the reliability of the first capacitor C1 when converting the low-side detecting current Isen1 into voltage may be increased, thereby improving the reliability of the current detection circuit.

In the embodiment depicted in FIG. 3, the voltage-to-current converting circuit 1230 may include an operational amplifier OP2, a transistor TR2, a resistor R2, and a current mirror MR. The positive input end of the operational amplifier OP2 is coupled to the ungrounded second end of the first capacitor C1, the negative input end of the operational amplifier OP2 is coupled to the first end of the transistor TR2, and the output end of the operational amplifier OP2 is coupled to the second end of the transistor TR2. The first end of the transistor TR2 is coupled to the ground via the resistor R2, and the third end of the transistor TR2 is coupled to the current mirror MR. in an embodiment, the resistors R1 and R2 have the same resistance. This way, the cycle detecting current Isen outputted by the processing circuit 120 during the turn-on period of the low-side transistor 12 may be the same as the low-side detecting current Isen1 outputted by the first detection circuit 110 during the turn-on period of the low-side transistor 12. The structure of the current mirror MR is well-known to those skilled in the art, and is thus not further elaborated.

In the embodiment depicted in FIG. 3, the processing circuit 120 further includes an adjusting circuit 1240 coupled to the current source circuit 1220. The adjusting circuit 1240 is configured to adjust the magnitude of the constant current Isr during the second switch cycle based on the comparison result between the first value V1 of the terminal voltage Vc1 at the first time point t1 and the second value V2 of the terminal voltage Vc1 at the second time point t2. In other words, in these embodiments, the processing circuit 120 is further configured to adjust the magnitude of the constant current Isr during the second switch cycle using the above-mentioned second implementation method. Details of adjusting the magnitude of the constant current Isr during the second switch cycle are not reiterated herein.

Some embodiments of the adjusting circuit 1240 are illustrated in FIG. 4. FIG. 4 is a diagram illustrating an implementation of the adjusting circuit 1240 according to an embodiment of the present invention. As depicted in FIG. 4, the adjusting circuit 1240 includes a sample and hold circuit 1241, a comparison circuit 1242 and a current adjusting circuit 1243. The sample and hold circuit 1241 is configured to sample the terminal voltage Vc1 established on the first capacitor C1, thereby acquiring the first value V1 of the terminal voltage Vc1 at the first time point t1 and the second value V2 of the terminal voltage Vc1 at the second time point t2. The comparison circuit 1242 is configured to compare the first value V1 and the second value V2 provided by the sample and hold circuit 1241, thereby outputting an adjusting signal dOUT. For example, the adjusting signal dOUT is at a first level when the first value V1 is larger than the second value V2, and the adjusting signal dOUT is at a second level different from the first level when the first value V1 is smaller than the second value V2.

The current adjusting circuit 1243 is configured to adjust the magnitude of the constant current Isr provided by the current source circuit 1220 during the second switch cycle based on the adjusting signal dOUT. For example, when the adjusting signal dOUT is at the first level (i.e., the first value V1 is larger than the second value V2), the current adjusting circuit 1243 is configured to control the current source circuit 1220 to adjust the constant current Isr so that the magnitude of the constant current Isr during the second switch cycle is smaller than the magnitude of the constant current Isr during the first switch cycle. Similarly, when the adjusting signal dOUT is at the second level (i.e., the first value V1 is smaller than the second value V2), the current adjusting circuit 1243 is configured to control the current source circuit 1220 to adjust the constant current Isr so that the magnitude of the constant current Isr during the second switch cycle is larger than the magnitude of the constant current Isr during the first switch cycle. In the above-mentioned embodiments, using the adjusting circuit 1240 with a simple structure, the magnitude of the constant current Isr during the second switch cycle may be adjusted based on the comparison result between the first value V1 and the second value V2.

Some embodiments of the sample and hold circuit 1241 and the current adjusting circuit 1243 are illustrated in FIGS. 5 and 6. FIG. 5 is a diagram illustrating an implementation of the sample and hold circuit 1241 according to an embodiment of the present invention. As depicted in FIG. 5, the sample and hold circuit 1241 includes a voltage buffering circuit 12411 coupled to the second end of the first capacitor C1.

In an embodiment, the voltage buffering circuit 12411 may include an operational amplifier OP3 and a transistor TR3 as depicted in FIG. 5. The positive input end of the operational amplifier OP3 is coupled to the ungrounded second end of the first capacitor C1, the negative input end of the operational amplifier OP3 is coupled to the first end of the transistor TR3, and the output end of the operational amplifier OP3 is coupled to the second end of the transistor TR3. The third end of the transistor TR3 is coupled to a power end.

In the embodiment depicted in FIG. 5, the sample and hold circuit 1241 further includes a third switch S3, a second capacitor C2, a fourth switch S4 and a third capacitor C3. The third switch S3 is coupled between the voltage buffering circuit 12411 and the first input end of the comparison circuit 1242. The first end of the second capacitor C2 is coupled to a first node M1 between the third switch S3 and the first input end of the comparison circuit 1242, and the second end of the second capacitor C2 is coupled to the ground. The fourth switch S4 is coupled between the voltage buffering circuit 12411 and the second input end of the comparison circuit 1242. The first end of the third capacitor C3 is coupled to a second node M2 between the fourth switch S4 and the second input end of the comparison circuit 1242, and the second end of the third capacitor C3 is coupled to the ground. In the above-mentioned embodiments, the sample and hold circuit 1241 may retain the first value V1 using the second capacitor C2 and retain the second value V2 using the third capacitor C3, thereby providing the first value V1 to the first input end of the comparison circuit 1242 and providing the second value V2 to the second input end of the comparison circuit 1242.

In some embodiments, the third switch S3 is configured to switch from a turn-on state to a turn-off state at the first time point t1 and switch from the turn-off state to the turn-on state at the third time point t3, so that the second capacitor C2 may retain the voltage of the first value V1 between the first time point t1 and the third time point t3. The fourth switch S4 is configured to switch from the turn-on state to the turn-off state at the second time point t2 and switch from the turn-off state to the turn-on state at the fourth time point t4, so that the third capacitor C3 may retain the voltage of the second value V2 between the second time point t2 and the third time point t3. The second time point t2 and the third time point t3 are time points in the second period p2 of the first switch cycle, and the third time point t3 is after the second time point t2.

Using the above-mentioned method of controlling the third switch S3 and the fourth switch S4, the sample and hold circuit 1241 may provide the first value V1 to the comparison circuit 1242 between the first time point t1 and the third time point t3, and provide the second value V2 to the comparison circuit 1242 between the second time point t2 and the third time point t3. This way, the comparison circuit 1242 may output the adjusting signal dOUT based on the first value V1 and the second value V2 between the second time point t2 and the third time point t3.

FIG. 6 is a diagram illustrating an implementation of the current adjusting circuit 1243 according to an embodiment of the present invention. As depicted in FIG. 6, the current adjusting circuit 1243 includes a trigger 12431 and an up/down counter 12432. The trigger 12431 is configured to output a trigger signal based on the adjusting signal dOUT and a clock signal dSUM. The pulse of the clock signal dSUM lasts from the fourth time point t4 to the third time point t3, wherein the second time point t2, the third time point t3 and the fourth time point t4 are time points in the second period p2 of the first switch cycle, the third time point t3 is after the second time point t2, and the fourth time point t4 is between the second time point t2 and the third time point t3. For example, the trigger 12431 may be a D-trigger depicted in FIG. 6. The D-trigger includes a D-pin for receiving the adjusting signal dOUT, a CK-pin for receiving the clock signal dSUM and a Q-pin and a Q′-pin for outputting the trigger signal. It is to be understood that the signal outputted via the Q-pin and the signal outputted via the Q′-pin have opposite logic levels.

The up/down counter 12432 is configured to adjust its output digit based on the trigger signal provided by the trigger 12431 so that the current source circuit 1220 may provide the constant current Isr whose magnitude matches the output digit. For example, the output digit of the up/down counter 12432 may be any integer between 0 and N, wherein Nis an integer larger than 1. Under such a circumstance, the magnitude of the constant current Isr outputted by the current source circuit 1220 may be equal to the current output digit of the up/down counter 12432 multiplied by a unit current magnitude.

In some embodiments, the up/down counter 12432 is configured to adjust its output digit based on the trigger signal and the clock signal dSUM. For example, clock signal dSUM may include a-DN pin and an UP-pin for receiving the trigger signal and a CK-pin for receiving the clock signal dSUM. Referring to FIG. 6, the DN-pin may be coupled to the Q-pin, and the UP-pin may be coupled to the Q′-pin. For example, when the first value V1 is smaller than the second value V2, the trigger signal outputted by the trigger 12431 includes a high-level signal outputted via the Q′-pin and a low-level signal outputted via the Q-pin. Under such a circumstance, the output digit of the up/down counter 12432 may be increased, thereby allowing the magnitude of the constant current Isr during the second switch cycle to be larger than the magnitude of the constant current Isr during the first switch cycle.

For another example, when the first value V1 is larger than the second value V2, the trigger signal outputted by the trigger 12431 includes a high-level signal outputted via the Q-pin and a low-level signal outputted via the Q′-pin. Under such a circumstance, the output digit of the up/down counter 12432 may be decreased, thereby allowing the magnitude of the constant current Isr during the second switch cycle to be smaller than the magnitude of the constant current Isr during the first switch cycle. This way, the current adjusting circuit 1243 may adjust the magnitude of the constant current Isr provided by the current source circuit 1220 during the second switch cycle based on the adjusting signal OUT.

In some embodiments, the interval between the second time point t2