310) that is connected to one or more associate SOCs (e.g., associate SOC 340) that behave as bridges to deliver audio, control, and/or other data to one or more endpoint peripherals, such as microphones 352, speakers 354, sensors, or the like. The primary SOC 310 is generally responsible for controlling the interface (e.g., the SoundWire bridge), the associate SOC(s) 340, and the endpoint peripherals 352, 354. However, challenges may arise because the associate SOC(s) 340 typically have a very low power consumption requirement and may not be equipped with a clock generator 328, instead relying on the clock signals 366, 368 transported over the SoundWire bridge, which is a DDR interface that requires a synchronous clock with a high frequency or an analog delay-based NPL design to operate without a clock source. In cases where an analog delay-based NPL design is used, the analog NPL is typically technology-dependent, which affects portability across different device types and results in a very large variation across process, voltage, and temperature (PVT) corners, thus introducing higher silicon costs and greater design complexity. Furthermore, using another faster clock 368 to connect the primary SOC 310 to the associate SOC 340 to avoid using an analog NPL design requires an additional I/O pad 370 on the primary SOC 310 and the associate SOC 340, which increases wiring and poses challenges for foldable electronic devices and other devices with form factors that impose physical wiring constraints. Furthermore, a DDR interface restricts the bandwidth and restricts the physical distance between the primary SOC 310 and the associate SOC 340. Accordingly, some aspects described herein relate to a SoundWire interface that has a single clock line, such that an SDR clock signal can be used to minimize the number of clock sources or I/O pads that are used to connect a primary SOC and an associate SOC, avoid a need for an analog NPL design to operate without a source clock, and/or enable a higher bandwidth and longer distance between the primary SOC and the associate SOC, among other examples.

As indicated above, FIG. 3 is provided as an example. Other examples may differ from what is described with respect to FIG. 3.

FIG. 4 is a diagram illustrating an example 400 associated with simplified clocking and I/O timing using an SDR link for a multi-SOC electronic device, in accordance with the present disclosure. As shown in FIG. 4, a multi-SOC electronic device may include a primary SOC 410 and an associate SOC 440, where the primary SOC 410 includes a sub-system 420 to control one or more peripheral devices connected to the primary SOC 410 and one or more peripheral devices connected to the associate SOC 440. For example, as shown in FIG. 4, the sub-system 420 may include a processor 422 (e.g., an application processor), a codec 424, and one or more interfaces 426 to NPL ports 430 that connect to the one or more peripheral devices (e.g., one or more microphones 432 and one or more speakers 434 in FIG. 4, although the peripheral devices may include sensors or other suitable devices). In general, the sub-system 420 may include a data bus (e.g., a SoundWire bus) to support communication between the processor 422, the codec 424, the interfaces 426, and the NPL ports 430 that connect to the one or more peripheral devices. In some aspects, as described herein, the data bus may be operated in accordance with standard protocols defined for interconnecting certain components of mobile devices, such as the SoundWire interface standards specified by the MIPI Alliance.

As further shown in FIG. 4, the associate SOC 440 may include a codec 444 and one or more interfaces 446 to NPL ports 450 that connect to the one or more peripheral devices (e.g., one or more microphones 452 and one or more speakers 454). In some aspects, to control the peripheral devices connected to the associate SOC 440, the primary SOC 410 may be configured to transport audio, control, and other peripheral data to the associate SOC 440 over an SDR link 460. For example, FIG. 4 illustrates an example where the SDR link 460 between the primary SOC 410 and the associate SOC 440 is a SoundWire bridge or a bridge that implements features associated with the SoundWire standard. For example, in some aspects, the SDR link 460 includes a master bridge 462 connected to an NPL port on the primary SOC 410 and a peripheral bridge 464 connected to an NPL port on the associate SOC 440. As shown in FIG. 4, the peripheral data is transported over the SoundWire bridge from the primary SOC 410 to the associate SOC 440 via a data bus 468 (e.g., according to a data signal, shown as SDR_DATA), and a single clock line that carries an SDR clock signal 466 to time the interface digitally. For example, as shown in FIG. 4, the SDR link 460 includes the single clock line between the NPL ports on the primary SOC 410 and the associate SOC 440 to carry the SDR clock signal 466 (shown as SDR_CLK), which may be generated by a clock source or clock generator 428 of the sub-system 420 of the primary SOC 410. In some aspects, edges of the SDR clock signal 466 may be used to time the interface between the primary SOC 410 and the associate SOC 440.

For example, in order to transport peripheral data to the associate SOC 440 over the SDR link 460 using the SDR clock signal 466, a device that has ownership of the data bus 468 (e.g., the master bridge 462) may drive the peripheral data onto the data bus 468 during one or more drive phases associated with the SDR clock signal 466, and the second SOC 440 may sample the peripheral data from the data bus 468 during one or more bus keeper phases associated with the SDR clock signal 466. For example, in some aspects, the peripheral data may be driven onto the data bus 468 starting at a rising edge or a positive edge of the SDR clock signal 466 (e.g., when the SDR clock signal 466 transitions from low to high), and the peripheral data may be sampled from the data bus 468 starting at a falling edge or a negative edge of the SDR clock signal 466 (e.g., when the SDR clock signal 466 transitions from high to low). In such cases, the drive phases associated with the SDR clock signal 466 may start when the SDR clock signal 466 transitions from low to high and may end when the SDR clock signal 466 transitions from high to low, and the bus keeper phases associated with the SDR clock signal 466 may start when the SDR clock signal 466 transitions from high to low and may end when the SDR clock signal 466 transitions from low to high. Alternatively, the peripheral data may be driven onto the data bus 468 starting at a falling edge or a negative edge of the SDR clock signal 466 (e.g., when the SDR clock signal 466 transitions from high to low), and the peripheral data may be sampled from the data bus 468 starting at a rising edge or a positive edge of the SDR clock signal 466 (e.g., when the SDR clock signal 466 transitions from low to high). In such cases, the drive phases associated with the SDR clock signal 466 may start when the SDR clock signal 466 transitions from high to low and may end when the SDR clock signal 466 transitions from low to high, and the bus keeper phases associated with the SDR clock signal 466 may start when the SDR clock signal 466 transitions from low to high and may end when the SDR clock signal 466 transitions from high to low.

In this way, using the SDR clock signal 466 to time the interface between the primary SOC 410 and the associate SOC 440 may enable a single clock line to be used to transport peripheral data from the primary SOC 410 to the associate SOC 440, which may reduce the number of wires that are used for the SDR link 460 (e.g., the single clock line occupies only one I/O pad on the primary SOC 410 and one I/O pad on the associate SOC 440, in contrast to two I/O pads on the primary SOC 410 and two I/O pads on the associate SOC 440 when two clock signals are used to time a SoundWire DDR interface). Furthermore, by using the digital SDR clock signal 466, the interface between the primary SOC 410 and the associate SOC 440 may be timed without using an analog delay-based NPL design, which may avoid variations across PVT corners, reduce silicon costs, and/or reduce design complexity. Furthermore, using a single SDR clock signal 466 mitigates various timing challenges, which may enable running the SDR clock signal 466 at a higher frequency (e.g., enabling a higher rate or bandwidth), extending the maximum distance between the primary SOC 410 and the associate SOC 440 by simplifying the I/O timing, and/or eliminating a need for a clock generator on the associate SOC 440. Furthermore, the single SDR clock signal 466 may maintain backward compatibility with existing SoundWire protocols.

As indicated above, FIG. 4 is provided as an example. Other examples may differ from what is described with respect to FIG. 4.

FIG. 5 is a diagram illustrating an example 500 associated with simplified clocking and I/O timing using an SDR link for a multi-SOC electronic device, in accordance with the present disclosure. In some aspects, reference number 510 depicts an example clock timing for an SDR clock signal, where a length of the SDR clock signal (e.g., from a first rising edge to a next rising edge, or a first falling edge to a next falling edge) is one bit slot. For example, when transporting peripheral data to an associate SOC over an SDR link using the SDR clock signal, a device that has ownership of a data bus (e.g., a SoundWire bridge) may drive the peripheral data onto the data bus during one or more drive phases associated with the SDR clock signal, and the second SOC may sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.

For example, as shown in FIG. 5, the peripheral data may be driven onto the data bus starting at a launch edge 512, which is shown as a rising edge or a positive edge of the SDR clock signal (e.g., when the SDR clock signal transitions from low to high), and the peripheral data may be sampled from the data bus starting at a capture edge 516, which is shown as a falling edge or a negative edge of the SDR clock signal (e.g., when the SDR clock signal transitions from high to low). Alternatively, in some aspects, the launch edge 512 may be a falling edge or a negative edge of the SDR clock signal (e.g., when the SDR clock signal transitions from high to low), and the capture edge 516 may be a rising edge or a positive edge of the SDR clock signal (e.g., when the SDR clock signal transitions from low to high). In either case, as shown by reference number 514, the peripheral data may need to be placed on the data bus a threshold time, T_setup, prior to the capture edge 516, to ensure that the peripheral data is available to be sampled before the bus keeper phase starts with the capture edge 516. Furthermore, as shown by reference number 518, the peripheral data may be held on the data bus for at least a threshold time, T_hold, after to the capture edge 516, to ensure that the peripheral data is available to be sampled during the bus keeper phase. In this way, using the SDR clock signal allows both the bridge manager and the bridge peripheral(s) to operate on edges of the SDR clock signal, which results in deterministic I/O timing that may increase the maximum distance between the bridge manager and the bridge peripheral(s) and/or increase the maximum clock frequency (e.g., allowing a higher data rate or higher bandwidth).

For example, reference number 520 shows a sequence of alternating drive phases 528 and bus keeper phases 532, where peripheral data may be driven onto the data bus during the drive phases 528 and sampled from the data bus during the bus keeper phases 532. For example, FIG. 5 illustrates an example timing for the SDR clock signal 522 (shown as SDR_CLK) and an SDR data signal 524 (shown as SDR_DATA), where the SDR data signal 524 is used to drive peripheral data onto the data bus during the drive phases 528 and to hold the peripheral data on the data bus during the bus keeper phases 532. For example, in FIG. 5, the drive phases 528 begin with rising or positive edges 526 of the SDR clock signal 522, and the bus keeper phases 532 begin with falling or negative edges 530 of the SDR clock signal 522. Alternatively, in some aspects, the drive phases 528 may begin with falling or negative edges 530 of the SDR clock signal 522, and the bus keeper phases 532 may begin with rising or positive edges 530 of the SDR clock signal 522. Furthermore, as described herein, peripheral data may or may not be driven onto the data bus in any particular drive phase 528 (but peripheral data is driven onto the data bus only during drive phases 528).

As indicated above, FIG. 5 is provided as an example. Other examples may differ from what is described with respect to FIG. 5.

FIG. 6 is a diagram illustrating an example 600 associated with a clock stop and wakeup mechanism and an example 650 associated with a bus reset mechanism using an SDR link for a multi-SOC electronic device, in accordance with the present disclosure. For example, the clock stop and wakeup mechanism and the bus reset mechanism may each operate in accordance with an SDR clock signal 610 and an SDR data signal 615, as described in more detail elsewhere herein.

In some aspects, as described herein, the clock stop and wakeup mechanism shown by example 600 may be backward compatible with a SoundWire DDR mode, where the clock stop mechanism may be initiated when a logical “1” is written to a control register. As further shown in FIG. 6, the clock stop mechanism includes a stopping frame 622, which is a one-frame wind-down period, during which the SDR data signal 615 includes only logical “0”s. As shown by reference number 626, the SDR data signal 615 may be parked at a low signal level after a last bit slot of the stopping frame 622. Furthermore, as shown by reference number 628, the SDR clock signal 610 may be parked at a low signal level after the last bit slot of the stopping frame 622. In some aspects, a wakeup mechanism may then be enabled to resume the SDR clock signal 610 and the SDR data signal 615. For example, as shown by reference number 630, wakeup signaling may be triggered when a peripheral device sets the SDR data signal 615 to a high signal level. In some aspects, the previously sampled value may then be driven onto the data bus, without requiring any special logic.

In some aspects, as described herein, the bus reset mechanism shown by example 650 may also be backward compatible with a SoundWire DDR mode, where the bus reset mechanism may be used to reset registers associated with all SoundWire peripheral devices connected to the data bus responsive to detecting a sequence of logical values 660 on the data bus over a configured number of successive cycles of the SDR clock signal 610. For example, in some aspects, the sequence of logical values 660 may include 4096 successive bit slots in which the SDR data signal 615 includes encoded logical “1”s (e.g., 4096 clock cycles of alternating high/low on the data lane). As shown by reference number 662, registers associated with all peripheral devices connected to the data bus may be reset responsive to detecting the sequence of logical values on the data lane over the configured number of successive cycles of the SDR clock signal 610.

As indicated above, FIG. 6 is provided as an example. Other examples may differ from what is described with respect to FIG. 6.

FIG. 7 is a diagram illustrating an example process 700 performed, for example, at an electronic device or an apparatus of an electronic device, in accordance with the present disclosure. Example process 700 is an example where the apparatus or the electronic device performs operations associated with simplified clocking and I/O timing using an SDR link for multiple SOCs.

As shown in FIG. 7, in some aspects, process 700 may include generating peripheral data and an SDR clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line to carry the SDR clock signal (block 710). For example, the electronic device (e.g., using primary SOC 410, sub-system 420, processor 422, and/or clock source 428, depicted in FIG. 4, CPU(s) 802, depicted in FIG. 8, or the like) may generate peripheral data and an SDR clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line to carry the SDR clock signal, as described above.

As further shown in FIG. 7, in some aspects, process 700 may include transporting the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line (block 720). For example, the electronic device (e.g., using SDR link 460, depicted in FIG. 4, system bus 808, depicted in FIG. 8, or the like) may transport the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line, as described above.

As further shown in FIG. 7, in some aspects, transporting the peripheral data to the second SOC over the SoundWire bridge includes driving, by the first SOC, the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal (block 730). For example, the electronic device (e.g., using primary SOC 410, sub-system 420, SDR link 460, master bridge 462, SDR clock signal 466, and/or data bus 468, depicted in FIG. 4, CPU(s) 802, depicted in FIG. 8, or the like) may drive, by the first SOC, the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, as described above.

As further shown in FIG. 7, in some aspects, transporting the peripheral data to the second SOC over the SoundWire bridge includes sampling, by the second SOC, the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal (block 740). For example, the electronic device (e.g., using associate SOC 440, SDR link 460, peripheral bridge 464, SDR clock signal 466, and/or data bus 468, depicted in FIG. 4, CPU(s) 802, depicted in FIG. 8, or the like) may sample, by the second SOC, the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal, as described above.

Process 700 may include additional aspects, such as any single aspect or any combination of aspects described below and/or in connection with one or more other processes described elsewhere herein.

In a first aspect, the one or more drive phases start at rising edges when the SDR clock signal transitions from low to high, and the one or more bus keeper phases start at falling edges when the SDR clock signal transitions from high to low.

In a second aspect, alone or in combination with the first aspect, the one or more drive phases start at falling edges when the SDR clock signal transitions from high to low, and the one or more bus keeper phases start at rising edges when the SDR clock signal transitions from low to high.

In a third aspect, alone or in combination with one or more of the first and second aspects, the single clock line occupies one I/O pad on the first SOC and one I/O pad on the second SOC.

In a fourth aspect, alone or in combination with one or more of the first through third aspects, process 700 includes writing a value to a register to initiate a clock stop mechanism that parks the SDR clock signal and a data signal at a low level after a stopping frame.

In a fifth aspect, alone or in combination with one or more of the first through fourth aspects, process 700 includes detecting, while the SDR clock signal and a data signal are parked at a low level, wakeup signaling that transitions the data signal to a high level, and restarting the SDR clock signal responsive to detecting the wakeup signaling.

In a sixth aspect, alone or in combination with one or more of the first through fifth aspects, process 700 includes resetting registers associated with all peripheral devices connected to the data bus responsive to detecting a sequence of logical values on the data bus over a configured number of successive cycles of the SDR clock signal.

In a seventh aspect, alone or in combination with one or more of the first through sixth aspects, process 700 includes delivering, by the second SOC, the peripheral data transported over the SoundWire bridge to one or more peripheral devices connected to the second SOC.

Although FIG. 7 shows example blocks of process 700, in some aspects, process 700 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 7. Additionally, or alternatively, two or more of the blocks of process 700 may be performed in parallel.

FIG. 8 is a diagram of an example processor-based system 800 that can support simplified clocking and I/O timing using an SDR link for a multi-SOC electronic device, in accordance with the present disclosure. For example, techniques described herein to provide simplified clocking and I/O timing using an SDR link for a multi-SOC electronic device may be provided in or integrated into any processor-based device, such as a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, and/or augmented reality glasses or a virtual reality headset, among other examples), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, and/or a foldable device.

Accordingly, FIG. 8 illustrates an exemplary processor-based system 800 that can support the techniques described herein to provide simplified clocking and I/O timing using an SDR link for a multi-SOC electronic device. For example, as shown in FIG. 8, the processor-based system 800 may include one or more central processing units (CPUs) 802, where each CPU 802 may include one or more processors 804. The CPU(s) 802 may have cache memory 806 coupled to the processor(s) 804 for rapid access to temporarily stored data. In some aspects, the CPU(s) 802 may be coupled to a system bus 808. For example, in some aspects, the CPU(s) 802 may include a first SOC and a second SOC, and the system bus 808 may include a SoundWire bridge and/or SDR link connecting the first SOC and the second SOC. In some aspects, the CPU(s) 802 may communicate with other devices by exchanging address, control, and data information (e.g., audio, control, or other peripheral data) over the system bus 808. Although not explicitly illustrated in FIG. 8, multiple system buses 808 may be provided, wherein each system bus 808 constitutes a different fabric.

In some aspects, other master and slave devices can be connected to the system bus 808. As shown in FIG. 8, the other master and slave devices can include a memory system 812, one or more input devices 814 (e.g., one or more microphones), one or more output devices 816 (e.g., one or more speakers), one or more network interface devices 818, and/or one or more display controllers 820, among other examples. The input device(s) 814 can include any type of input device, including input keys, switches, and/or voice processors, among other examples. The output device(s) 816 can include any type of output device, including audio, video, and/or other visual indicators, among other examples. In some aspects, the network interface device(s) 818 can be any device configured to allow exchange of data to and from a network 822. The network 822 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a personal area network (PAN), or the Internet. The network interface device(s) 818 can be configured to support any type of communications protocol desired. The memory system 812 can include one or more memory units 824 and a memory controller 810.

The CPU(s) 802 may also be configured to access the display controller(s) 820 over the system bus 808 to control information sent to one or more displays 826. The display controller(s) 820 may send information to the display(s) 826 to be displayed via one or more video processors 828, which may process the information to be displayed into a format suitable for the display(s) 826. The display(s) 826 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, and/or a light emitting diode (LED) display.

In some aspects, the processor-based system 800 may implement one or more techniques or perform one or more operations associated with simplified clocking and I/O timing using an SDR link for a multi-SOC device, as described in more detail elsewhere herein. For example, the CPU(s) 802, the memory system 812, the display controller 820, and/or any other component(s) of FIG. 4 or FIG. 8 may perform or direct operations of, for example, process 700 of FIG. 7 or other processes as described herein (alone or in conjunction with one or more other components). The memory units 824 may store data and program codes for the processor-based system 800. In some examples, the memory units 824 may include a non-transitory computer-readable medium storing a set of instructions (for example, code or program code) for implementing one or more techniques or performing one or more operations associated with simplified clocking and I/O timing using an SDR link for a multi-SOC device. The memory units 824 may include one or more memories, such as a single memory or multiple different memories (of the same type or of different types). The memory units 824 may include one or more memories, such as a single memory or multiple different memories (of the same type or of different types). For example, the set of instructions, when executed (for example, directly, or after compiling, converting, or interpreting) by one or more processors of an electronic device, may cause the electronic device to perform process 700 of FIG. 7 or other processes as described herein. In some examples, executing instructions may include running the instructions, converting the instructions, compiling the instructions, and/or interpreting the instructions, among other examples.

In some aspects, an electronic device includes means for generating peripheral data and an SDR clock signal to transport over a SoundWire bridge having a single clock line; and/or means for transporting the peripheral data over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein the means for transporting the peripheral data over the SoundWire bridge may include means for driving the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal; and/or means for sampling the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. In some aspects, the means for the electronic device to perform operations described herein may include, for example, one or more of primary SOC 410, sub-system 420, processor