126 of the accessed row.

The refresh address control circuit 116 may determine if the accessed row is an aggressor row based on the access count from the MT memory cells 126. If the current row is not an aggressor row, the value of the access count may be changed and then the refresh address control circuit may write the new value of the access count back to the counter memory cells 126 of the accessed row. If the refresh address control circuit 116 determines that the accessed row is an aggressor, then the refresh address control circuit 116 may use the row address XADD of the accessed row to determine one or more victim row addresses and provide them as a refresh address RXADD as part of a targeted refresh operation. When the accessed row is determined to be an aggressor, the access count Xcount associated with that row may be reset (e.g., to a minimum value, such as 0). In some embodiments, the refresh address control circuit 116 may queue up identified aggressor addresses (e.g., in a register) for later use in targeted refresh operations.

The refresh address RXADD may be provided with a timing based on a timing of the refresh signal AREF. The refresh address control circuit 116 may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the targeted refresh address may be issued in (e.g., “steal”) a time slot which would otherwise have been assigned to an auto-refresh address. In some embodiments, certain time slots may be reserved for targeted refresh addresses, and the refresh address control circuit 116 may determine whether to provide a targeted refresh address, not provide an address during that time slot, or provide an auto-refresh address instead during the time slot.

The targeted refresh address may be based on access characteristics over time of the row addresses XADD received from the address decoder 104. For example, the access characteristics may be determined based on the value of the access count Xcount stored in the MT memory cells 126. The refresh address control circuit 116 may use different methods to calculate a targeted refresh address based on a row address XADD identified as an aggressor address based on the access count. For example, the refresh address control circuit 116 may determine if a given row is an aggressor address, and then calculate and provide addresses corresponding to victim addresses of the aggressor address as the targeted refresh address. In some embodiments, more than one victim address may correspond to a given aggressor address. In this case the refresh address control circuit may queue up multiple targeted refresh addresses, and provide them sequentially when it determines that a targeted refresh address should be provided. The refresh address control circuit 116 may provide the targeted refresh address right away, or may queue up the targeted refresh address to be provided at a later time (e.g., in the next time slot available for a targeted refresh).

The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 122. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit 122 so that power supply noise generated by the input/output circuit 122 does not propagate to the other circuit blocks.

FIG. 2 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. The memory array 200 may represent an exemplary portion of a memory array, such as the memory array 118 of FIG. 1. The memory array 200 may be divided into mats (e.g., memory mats, memory array mats, array mats), including mat 203 (e.g., full array mat) and edge mat 205 (so called because it is at an edge of the memory array 200) separated by peripheral regions 207 that include sense amplifiers (SA) and LIO. The memory array 200 includes a plurality of word lines WL (rows) 202 and bit lines (BLE and BLO) (columns) 204. A plurality of memory cells 206 (MC), are located at the intersection of the rows and columns. A portion of the memory cells 206 along a given word line may be set up using a MT architecture, such as in MT region 226 on the left side (from the perspective of the reader) of line 201, while a remainder of the memory cells along the word line use a 1T architecture in region 227 on the right side of line 201. The memory cells 206 of both regions 226 and 227 may be generally similar or identical to each other, except they may be coupled differently as described herein. The memory array 200 includes a number of sense amplifier groups 232a-b and 234a-b, each of which includes a number of sense amplifiers SA0-3. The sense amplifier groups 232 and 234 may be generally similar to each other, except that the sense amplifier groups 234 are coupled to bit lines in the 1T region, and the sense amplifier groups 232 are coupled to bit lines in the MT region 226. The sense amplifier groups 232 and 234 may be coupled to local I/O lines LIO 208 and LIOF 210.

For clarity of illustration, only one edge array mat and only one full array mat are shown in FIG. 2. The memory array 200 may include multiple full array mats, with edge array mats at either end of the array. Further, only a few word lines WL and bit lines BL (and their corresponding memory cells 206) and their corresponding sense amplifiers and LIO are shown in FIG. 2. More word lines WL and bit lines BL (and their corresponding memory cells), sense amplifiers, and LIO may be provided in a memory cell array of the present disclosure.

Each of the memory cells 206 may store information. In some embodiments, the information may be stored as a binary code, and each memory cell 206 in the MT region may store a bit, while a pair of memory cells 206 in the MT region 226 may store a bit, which may be either at a logical high or a logical low level. In the example shown in FIG. 2, the pair of memory cells 206 in the MT region 226 may have a same polarity.

The sense amplifiers of sense amplifier groups 232 and 234 may read or write a value of a bit of information along the bit lines 204 to memory cells 206 at the accessed word line 206. The sense amplifiers of sense amplifier groups 232 and 234 may convert a signal along the bit line to a signal which is ‘readable’ by other elements of the memory device (e.g., by amplifying a voltage). The bit lines may be coupled to an input/output circuit (e.g., input/output circuit 122 of FIG. 1) via a respective column select switch, which may be a column select transistor activated by a column select signal CS. In the example shown in FIG. 2, each CS may access eight bits per word line 202 in region 227 and may access four bits per word line in region 226.

In an example read operation of region 227, when a word line 202 is accessed, the memory cells 206 may provide their charge onto the coupled bit lines 204 which may cause a change in a voltage and/or current along the bit line 204. The sense amplifiers of groups 234 may determine a logical level of the accessed memory cell 206 based on the resulting voltage and/or current along the bit line 204, and may provide a signal corresponding to the logical level through the column select transistor to the input/output circuit.

In an example write operation of region 227, the sense amplifiers SA0-3 of sense amplifier groups 234 may receive a signal indicating a logical level to be written to the accessed memory cells 206 from the input/output circuit. The sense amplifiers SA0-3 of sense amplifier groups 234 may provide a voltage and/or current along the coupled bit line 204 (e.g., along the bit lines with active column select transistors) at a level corresponding to the logical level to be written. The voltage and/or current along the bit line 204 may charge the memory cell 206 at the intersection of the bit line 204 with an accessed word line 202 to a charge level associated with the written logical level. In this manner, by specifying the row which is accessed, and which bit lines to record data from (and/or write data to), specific memory cells 202 may be accessed during one or more operations of the memory device.

Certain memory cells along each of the word lines may be set up as MT memory cells in region 226. In the example shown in FIG. 2, the MT memory cells have a 2T architecture. The 2T memory cells 206 in region 226 may generally be similar to the other, 1T, memory cells of region 227. In some embodiments, the 2T memory cells of region 226 may be physically the same as the other memory cells 206. However, rather than each sense amplifier SA0-3 of sense amplifier groups 232 being coupled to a single memory cell, in the 2T region, each sense amplifier SA0-3 of sense amplifier groups 232 is coupled to multiple memory cells (e.g., a pair of memory cells).

Referring to the full array mat 203 in region 226, bit line BLO<0> is coupled to SA0 of sense amplifier group 232a and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLO<0> is further coupled to LIOF<3> associated with sense amplifier group 232a. Bit line BLO<1> is coupled to SA1 of sense amplifier group 232a and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLO<1> is further coupled to LIOF<1> associated with sense amplifier group 232a. Bit line BLO<2> is coupled to SA2 of sense amplifier group 232a and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLO<2> is further coupled to LIOF<2> associated with sense amplifier group 232a. Bit line BLO<3> is coupled to SA3 of sense amplifier group 232a and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLO<3> is further coupled to LIOF<0> associated with sense amplifier group 232a.

Still referring to the full array mat 203 in the region 226, bit line BLE<0> is coupled to SA0 of sense amplifier group 232b and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLE<0> is further coupled to LIO<2> associated with sense amplifier group 232b. Bit line BLE<1> is coupled to SA1 of sense amplifier group 232b and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLE<1> is further coupled to LIO<0> associated with sense amplifier group 232b. Bit line BLE<2> is coupled to SA2 of sense amplifier group 232b and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLE<2> is further coupled to LIO<3> associated with sense amplifier group 232b. Bit line BLE<3> is coupled to SA3 of sense amplifier group 232b and two memory cells 206 in each of half of the word lines 202 of the full array mat 203. BLE<3> is further coupled to LIO<1> associated with sense amplifier group 232b.

Turning to the edge mat 205, bit line BLE<0> is coupled to SA0 of sense amplifier group 232a and two memory cells 206 in each of the word lines 202 of the edge mat 205. BLE<0> is further coupled to LIO<2> associated with sense amplifier group 232a. Bit line BLE<1> is coupled to SA1 of sense amplifier group 232a and two memory cells 206 in each of the word lines 202 of the edge mat 205. BLE<1> is further coupled to LIO<1> associated with sense amplifier group 232a. Bit line BLE<2> is coupled to SA2 of sense amplifier group 232a and two memory cells 206 in each of the word lines 202 of the edge mat 203. BLE<2> is further coupled to LIO<3> associated with sense amplifier group 232a. Bit line BLE<3> is coupled to SA3 of sense amplifier group 232a and two memory cells 206 in each of the word lines 202 of the edge mat 205. BLE<3> is further coupled to LIO<1> associated with sense amplifier group 232a.

The coupling of the bit lines 204 to the sense amplifiers and LIO lines in full array mat 203 the 1T region 227 is the same as in the MT region 226. However, each bit line 204 extends to couple to one memory cell 206 in all of the word lines 202 of the full array mat 203. In some embodiments, such as the one shown in FIG. 2, certain portions of the 1T region 227 may include certain sub-portions that have a 2T architecture. For example, as shown in FIG. 2, memory cells 206 in the edge mat 205 may have a folded architecture and coupling arrangement to that of region 226. Further details of folded bit line architectures in edge mats are disclosed in U.S. patent application Ser. No. 17/565,187, which is incorporated herein by reference for any purpose.

In some embodiments, such as the one shown in FIG. 2, the bit lines may be “folded” to couple multiple memory cells 206 together in the region 226. Box 214 shows an enlarged view of the region indicated by box 212. As shown, a bit line 204a extends from SA3 of sense amplifier group 232a and couple memory cell 206a and memory cell 206b. The bit line 204a may have a “fold” 216a where instead of continuing straight along the mat 203 (such as the bit lines 204 in region 227), the bit line 204a folds back around to couple memory cell 206a and memory cell 206b. Similarly, bit line 204b extends from SA3 of sense amplifier group 232b and has fold 216b to couple memory cells 206c and 206d. In some embodiments, a pitch double process and use of a spacer at the end of the bit line 204 pattern may be used to form the folds 216a and 216b. In the example shown in FIG. 2, the folds 216a, 216b include a straight line extending perpendicularly between two parallel straight line portions of the bit lines 204a and 204b, respectively. However, in other embodiments, the folds 216a, 216b may have a different shape (e.g., curved “U” shape).

In some embodiments, the bit lines coupling the MT memory cells 206 of region 226 may have the same or approximately the same (e.g., within 10%) length as the bit lines coupling the 1T memory cells 206 of region 227. Compared to the sense amplifier groups 234a and 234b in the 1T memory cell region 227, the sense amplifier groups 232a and 232b of the MT memory cell region 227, each sense amplifier group will have only half a section's word lines 202 coupled to it. Two sense amplifiers (e.g., SA0 and SA1) may be used for access. For example, to access the memory cells 206 along WL<n/2+1> in region 226, sense amplifiers of SA0-3 of sense amplifier group 232b are used (but none from sense amplifier group 232a). In contrast, to access the memory cells 206 along WL<n/2+1> in region 227, SA0-3 of sense amplifier group 234a and 234b are used.

In some embodiments, in order to accommodate the fold of the bit lines 204 in memory mat 203 in the region 226, dummy word lines 218 may be included in the memory mat 203. In some embodiments, one dummy word line 218 may be provided. In some embodiments, two to four dummy word lines 218 may be provided. In some embodiments, edge mat 205 may be less crowded than memory mat 203, and dummy word lines 218 may not be necessary to accommodate the folded bit lines 204.

In some embodiments, the increase in layout area due to dummy word lines in the MT region may be less than 1%. In some embodiments, the increase in layout area due to dummy word lines may be approximately 0.27-0.34%.

In some embodiments, providing same-polarity MT memory cells may provide a reduced write recovery time (tWR) for the MT memory cells compared to 1T cells. In some applications, the tWR may be approximately 53% of the tWR of 1T cells.

While same polarity MT architectures provide reduced tWR and acceptably low layout area increases compared to solely 1T memory cell arrays, in some applications, complementary polarity MT architectures may provide further reductions in tWR and/or layout area increases.

FIG. 3 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. The memory array 300 may represent an exemplary portion of a memory array, such as the memory array 118 of FIG. 1. The memory array 300 may be divided into mats, including mat 303 and edge mat 305 (so called because it is at an edge of the memory array 300) separated by peripheral regions 307 that include sense amplifiers (SA) and LIO. The memory array 300 includes a plurality of word lines WL (rows) 302 and bit lines BL/BLF (columns) 304. A plurality of memory cells 306 (MC), are located at the intersection of the rows and columns. A portion of the memory cells 306 along a given word line may be set up using a MT architecture while a remainder of the memory cells along the word line use a 1T architecture in region another region. The memory cells 306 of both MT and 1T be generally similar or identical to each other, except they may be coupled differently as described herein. The region including the 1T architecture may be similar to the architecture shown in region 227 of FIG. 2. Accordingly, the 1T region and explanation thereof are omitted from FIG. 3.

The memory array 300 includes sense amplifier groups 332a and 332b, each of which includes a number of sense amplifiers SA0-3. The sense amplifier groups 332a and 332b may be coupled to local I/O lines LIO 208 and LIOF 210. The sense amplifiers of sense amplifier groups 332a and 332b may be similar or identical to sense amplifiers and groups located in 1T regions (not shown) of the memory array 300, except they may be coupled to memory cells differently as described herein.

For clarity of illustration, only one edge array mat and only one full array mat are shown in FIG. 3. The memory array 300 may include multiple full array mats, with edge array mats at either end of the array. Further, only a few word lines WL and bit lines BL (and their corresponding memory cells 306) and their corresponding sense amplifiers and LIO are shown in FIG. 3. More word lines WL and bit lines BL/BLF (and their corresponding memory cells), sense amplifiers, and LIO may be provided in a memory cell array of the present disclosure.

Each of the memory cells 306 may store information. In some embodiments, the information may be stored as a binary code, in the embodiment shown in FIG. 3, a pair of memory cells 306 in full array mat 303 may store a bit, which may be either at a logical high or a logical low level and four memory cells 306 in an edge mat 305 may store a bit. In the example shown in FIG. 3, the pair of memory cells 306 in the full array mat 303 may have complementary polarities. In the edge mat 305, each pair of memory cells 306 may have a same polarity, but the two pairs of memory cells 306 may have complementary polarities.

The sense amplifiers of sense amplifier groups 332a and 332b may read or write a value of a bit of information along the bit lines 304 to memory cells 206 at the accessed word line 302. The sense amplifiers of sense amplifier groups 332a and 332b may convert a signal along the bit line to a signal which is ‘readable’ by other elements of the memory device (e.g., by amplifying a voltage). The bit lines may be coupled to an input/output circuit (e.g., input/output circuit 122 of FIG. 1) via a respective column select switch, which may be a column select transistor activated by a column select signal CS. In the example shown in FIG. 3, each CS may access four bits per word line. In the 1T region of the memory array 300 (not shown, see region 227 in FIG. 2), each CS may access eight bits per word line in some embodiments. Thus, the CS in the MT region may access half the number of bits as the CS in the 1T region in some embodiments. The ratio may be different in other embodiments where more memory cells are coupled to the sense amplifiers per sense operation.

In the embodiment shown in FIG. 2, folds in the bit lines were provided with the layout expense of dummy word lines 218 in order to couple the MT memory cells 206 to the sense amplifiers. In contrast, in the embodiment shown in FIG. 3, bit lines BL/BLF and LIO/LIOF are rerouted at the layout expense of dummy bit lines 318 in order to couple the MT memory cells 306 to the sense amplifiers. The routing of the bit lines BL and BLF for the full array mat 303 will be explained with reference to the four pairs of memory cells 306 corresponding to bit<0-3> (a total of eight memory cells 306). Each bit<0-3> is stored by two memory cells 306 having complementary polarities from one another.

A first memory cell 306 of bit<0> may be coupled to bit line 304a, which is routed through an LIO break 330 and coupled to SA0 of sense amplifier group 332b. The routing through the LIO break 330 may be accommodated by the dummy bit lines 318. While two dummy bit lines 318 are used in the example shown in FIG. 3, in other embodiments, more ore fewer dummy bit lines 318 may be used (e.g., 0, 1, 4). A second memory cell 306 of bit<0> may be routed “normally” and coupled to SA0 of sense amplifier group 332b.

A first memory cell 306 of bit<0> may be coupled to bit line 304a, which is routed through an LIO break 330 and coupled to SA0 of sense amplifier group 332b. The routing through the LIO break 330 may be accommodated by the dummy bit lines 318. While two dummy bit lines 318 are used in the example shown in FIG. 3, in other embodiments, more ore fewer dummy bit lines 318 may be used (e.g., 0, 1, 4). A second memory cell 306 of bit<0> may be coupled to bit line 304b which is routed over the LIO and also coupled to SA0 of sense amplifier group 332b.

A first memory cell 306 of bit<2> may be coupled to bit line 304c, which is routed through an LIO break 330 and coupled to SA2 of sense amplifier group 332b. A second memory cell 306 of bit<2> may be coupled to bit line 304d which is routed over the LIO and also coupled to SA2 of sense amplifier group 332b. Thus, in the example shown, the even bits associated with a CS may be associated with the sense amplifiers on a same side of a sense amplifier group.

A first memory cell 306 of bit<1> may be coupled to bit line 304e, which is routed through an LIO break 330 and coupled to SA3 of sense amplifier group 332a. A second memory cell 306 of bit<1> may be coupled to bit line 304f which is routed over the LIO and also coupled to SA3 of sense amplifier group 332a.

A first memory cell 306 of bit<3> may be coupled to bit line 304g, which is routed through an LIO break 330 and coupled to SA1 of sense amplifier group 332a. A second memory cell 306 of bit<3> may be coupled to bit line 304h which is routed over the LIO and also coupled to SA1 of sense amplifier group 332a. Thus, in the example shown, the odd bits associated with a CS may be associated with the sense amplifiers on a same side of a sense amplifier group, similar to the even bits associated with the CS. However, the even bits and odd bits are associated with different sense amplifier groups on opposite sides of the full array mat 303.

Turning to the edge mat 305, the bit lines 304 may be folded, similar to the bit lines 204 in edge mat 205. In this embodiment, the memory cells 306 of the edge mat 305 may have a 4T rather than a 2T structure. That is, four memory cells 306 may be used to store a single bit. Box 301 shows an enlarged view of the memory cells 306 of a word line 302 in the edge mat 305. The curved arrows labeled bit<0> and bit<2> indicate the two pairs of memory cells 306 used to store each bit. The memory cells 306 of edge mat 305 associated with a CS may provide two bits instead of four bits. In some embodiments, the odd bits may be stored in another edge mat (not shown) at the other end of the memory array 300.

Similar to the bits of the full array mat 303, a first pair of memory cells 306 for bit<0> may be coupled to a bit line 304i routed through an LIO break 330 to SA0 of sense amplifier group 332a and a second pair of memory cells 306 for bit<0> may be coupled to a bit line 304j routed over the LIO to couple to SA0 of sense amplifier group 332a. A first pair of memory cells 306 for bit<2> may be coupled to a bit line 304k routed through an LIO break 330 to SA2 of sense amplifier group 332a and a second pair of memory cells 306 for bit<2> may be coupled to a bit line 304m routed over the LIO to couple to SA2 of sense amplifier group 332a.

Returning to the sense amplifiers, SA0 of sense amplifier group 332a is coupled to LIO<0> by BL<0> and to LIOF<0> by BLF<0>, which is a truncated portion of a bit line that in a 1T region, would have extended into the array mat 303. SA2 is coupled to LIO<2> by BL<2> and LIOF<2> by BLF<2>, which is again a truncated portion of a bit line that in a 1T region, would have extended into the array mat 303. SA1 of sense amplifier group 332a is coupled to LIOF<1> by BLF<1> and to LIO<1> by BL<1>, which is a truncated portion of a bit line that in a 1T region, would have extended into the edge mat 305. SA3 is coupled to LIOF<3> by BLF<3> and LIO<3> by BLF<3>, which is again a truncated portion of a bit line that in a 1T region, would have extended into the edge mat 303. The sense amplifiers of sense amplifier group 332b have a corresponding coupling structure between the bit lines 304 and the LIO lines 308, 310. Thus, “original” portions of the bit lines rerouted through the LIO break 330 may be “preserved” for coupling to LIO lines 308, 310.

Comparing the sense amplifier groups 234a and 234b in 1T region 227 shown in FIG. 2, for each sense amplifier SA0-3 of the sense amplifier groups 332a and 332b in the MT region of memory array 300, both BL and BLF are at a same side of the SA compared to the 1T array region where the BL and BLF are at different sides of the SA. Further, each full mat 303 in the MT region only uses half of the sense amplifiers from odd and even SA for the 2T example shown in FIG. 3. In some embodiments, such as the one shown, the original jump over bit lines may be routed to the opposite CS region, but may be truncated before entering a core of a memory array mat.

In some embodiments, two of the four bit lines may be placed on a metal M0 layer of a die and the other two bit lines may be routed off diffusion Li1 layer. For example, the bit lines routed through the LIO breaks 330 may be disposed on the metal M0 layer and the bit lines routed over the LIO/F lines may be routed off diffusion Li1 layer in some embodiments. In some embodiments, the diffusion layer may be adjacent to the metal layer.

The embodiment shown in FIG. 3 provides for one column select CS. However, in some applications, more than one column select in a column plane may be desired.

FIG. 4 is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. The memory array 400 may represent an exemplary portion of a memory array, such as the memory array 118 of FIG. 1. The memory array 400 may be divided into mats, including mat 403 and edge mat 405 (so called because it is at an edge of the memory array 400) separated by peripheral regions 407 that include sense amplifiers (SA) and LIO. The memory array 400 includes a plurality of word lines WL (rows) 402 and bit lines BL/BLF (columns) 404. A plurality of memory cells 406 (MC), are located at the intersection of the rows and columns. A portion of the memory cells 406 along a given word line may be set up using a MT architecture while a remainder of the memory cells along the word line use a 1T architecture in region another region. The memory cells 406 of both MT and 1T be generally similar or identical to each other, except they may be coupled differently as described herein. The region including the 1T architecture may be similar to the architecture shown in region 227 of FIG. 2. Accordingly, the 1T region and explanation thereof are omitted from FIG. 4.

The memory array 400 includes sense amplifier groups 432a-d, each of which includes a number of sense amplifiers SA0-3. The sense amplifier groups 432a-d may be coupled to local I/O lines LIO 408 and LIOF 410. The sense amplifiers of sense amplifier groups 432a-d may be similar or identical to sense amplifiers and groups located in 1T regions (not shown) of the memory array 300, except they may be coupled to memory cells differently as described herein.

For clarity of illustration, only one edge array mat and only one full array mat are shown in FIG. 4. The memory array 400 may include multiple full array mats, with edge array mats at either end of the array. Further, only a few word lines WL and bit lines BL (and their corresponding memory cells 406) and their corresponding sense amplifiers and LIO are shown in FIG. 4. More word lines WL and bit lines BL/BLF (and their corresponding memory cells), sense amplifiers, and LIO may be provided in a memory cell array of the present disclosure.

Region 426 of memory array 400 on one side of the LIO break 430 may be associated with one column select signal and region 429 on the other side of the LIO break 430 may be associated with another column select signal. In some embodiments, only one column select may be associated on a side of an LIO break 430. The layout and operation of region 426 may be substantially the same as the portion of memory array 300 shown in FIG. 3. The operation of region 429 may be substantially the same as the operation of region 426 and the portion of memory array 300 shown in FIG. 3. However, the layout of the region 429 may be a mirror image of the layout of region 426.

In some embodiments, such as the one shown in FIG. 4, compared to memory array 300, additional dummy bit lines 418 may be provided in memory array 400 to accommodate the routing of the bit lines 404 through the LIO break 430. In the example shown, four dummy bit lines 418 are provided. However, in other embodiments, more or fewer dummy bit lines 418 may be provided.

In some embodiments, 16 bits are required to provide adequate storage for the access count Xcount. For the MT arrangement shown in FIGS. 3 and 4, four column selects may be used to access the 16 bits (e.g., one column select accesses eight memory cells and 4 bits per memory cell in full array mats). Various layouts may be used to accommodate MT memory cells and column selects used to store the Xcount. For example, memory cells for two column selects may be located in a column plane associated with error correction code and global column redundancy. In some embodiments, the two column selects associated with the Xcount may use the layout shown in FIG. 4. Memory cells for a third column select associated with the Xcount may be placed in another column plane, and memory cells for a fourth column select associated with the Xcount may be placed in a separate column plane. For example, the other two column planes may be associated with DQ3 and DQ4. In another example, the other two column planes may be associated with DQ1 and DQ2. Other column planes may be used in other examples.

In some embodiments, the increase in layout area due to dummy bit lines may be less than 1%. In some embodiments, the increase in layout area due to dummy bit lines may be approximately 0.23%. In some embodiments, this layout area penalty is less than the layout penalty for dummy word lines.

In some embodiments, providing complementary-polarity MT memory cells may provide a reduced write recovery time (tWR) for the MT memory cells compared to 1T cells. In some applications, the tWR may be approximately 47% of the tWR of 1T cells. In some embodiments, the complementary-polarity MT memory cells may provide a lower tWR than same-polarity MT memory cells.

While folding bit lines as described with reference to FIG. 2 and rerouting bit lines as described with reference to FIGS. 3 and 4 provide minimal layout penalties for incorporating MT architecture into the same array as 1T cells, in some applications, these techniques may increase layout complexity and/or increase the risk of defects. Depending on various factors, such as processing equipment, process type, and/or desired robustness against defects, other techniques may be desirable, even if the layout penalty may be higher in some cases.

FIG. 5A is a schematic diagram of a portion of a memory array according to at least one embodiment of the present disclosure. The memory array 500 may represent an exemplary portion of a memory array, such as the memory array 118 of FIG. 1. While memory array 500 may include one or multiple memory mats including memory cells and word lines as shown in FIG. 1, only a peripheral region 507 of memory array 500 is shown in FIG. 5. Memory array 500 may include multiple peripheral regions that are substantially the same as peripheral region 507 in some embodiments. Furthermore, while only a few bit lines, sense amplifiers, and LIO are shown for clarity, more or fewer lines BL, LIO, and sense amplifiers may be included in memory array 500 in some embodiments.

A portion of the memory cells (not shown) of memory array 500 along a given word line may have a MT architecture, such as in MT region 526 on the right side (from the perspective of the reader) of line 501b. The MT architecture may use memory cell having a same polarity or complementary polarity. A remainder of the memory cells along the word line use a 1T architecture in region 527 on the left side of line 501a. The memory cells of both regions 526 and 527 may be generally similar or identical to each other, except they may be coupled differently as described herein. The memory array 500 includes a number of sense amplifier groups 532 and 534, each of which includes a number of sense amplifiers SA0-3 and SA0-7, respectively. The sense amplifier groups 532 and 534 may be generally similar to each other, except that the sense amplifier group 534 are coupled to bit lines in the 1T region, and the sense amplifier group 532 are coupled to bit lines in the MT region 526. The sense amplifier groups 532 and 534 may be coupled to local I/O lines LIO 508 and LIOF 510.

Column selects 536 and 538 may provide CS signals (e.g., CS<0> and CS<1>) to column select switches 540 and 542, respectively, which may be implemented by transistors, as shown in FIG. 5. The switches 540 and 542 may be controlled by the CS signals to activate corresponding sense amplifiers of the sense amplifier groups 532 and 534. In some embodiments, sense amplifier group 534 may include two sense amplifier groups (e.g., SA0-3 and SA4-7).

Turning to the 1T region 227, a first group of CS switches 540 associated with CS<1> is coupled to the LIO lines <0-3> and bit lines BL<0-7>. Switch 540a is coupled between LIO<0> and BL<0>. Switch 540b is coupled between LIO<1> and BL<1>. Switch 540c is coupled between LIO<2> and BL<2> and switch 540d is coupled between LIO<3> and BL<3>.

A second group of CS switches 540 associated with CS<1> is coupled to the LIOF lines <0-3> and bit lines BLF<4-7>. Switch 540e is coupled between LIOF<1> and BLF<6>. Switch 540f is coupled between LIOF<0> and BLF<7>. Switch 540g is coupled between LIOF<3> and BLF<4>. Switch 540h is coupled between LIOF<2> and BLF<5>.

A first group of CS switches 540 associated with CS<0> is coupled to the LIO lines <0-3> and bit lines BL<4-7>. Switch 540i is coupled between LIO<0> and BL<4>. Switch 540j is coupled between LIO<3> and BL<5>. Switch 540k is coupled between LIO<2> and BL<6> and switch 540m is coupled between LIO<1> and BL<7>.

A second group of CS switches 540 associated with CS<0> is coupled to the LIOF lines <0-3> and bit lines BLF<0-3>. Switch 540n is coupled between LIOF<3> and BLF<2>. Switch 540p is coupled between LIOF<2> and BLF<3>. Switch 540q is coupled between LIOF<1> and BLF<0>. Switch 540r is coupled between LIOF<0> and BLF<1>.

As for the bit lines, BL<0> is coupled to SA7, BL<1> is coupled to SA6, BL<2> is coupled to SA 5, BL<3> is coupled to SA4, BL<4> is coupled to SA3, BL<5> is coupled to SA2, BL<6> is coupled to SA1, and BL<7> is coupled to SA0 of sense amplifier group 534. BLF<7> is coupled to SA7, BLF<6> is coupled to SA6, BLF<5> is coupled SA5, BLF<4> is coupled to SA4, BLF<3> is coupled to SA3, BLF<2> is coupled to SA2, BLF<1> is coupled to SA1, and BLF<0> is coupled to SA0 of sense amplifier group 534. The coupling of the bit lines, sense amplifiers, and column select switches in the 1T region 527 may allow eight bits to be accessed per column select.

Turning to the MT region 526, which in the example shown in FIG. 5 is a 2T architecture, compared to the 1T region 527, LIOF<0> and LIOF<2> have been shifted to be on an opposite side of the sense amplifier group 532 to sense amplifier group 534. In both regions, LIOF<2> is disposed closer to the sense amplifiers. Similarly, LIO<1> and LIO<3> in the MT region 526 are an opposite side of the sense amplifier group 532 compared to sense amplifier group 534 in the 1T region 527, and LIO<3> is disposed closer to the sense amplifiers in both regions. As shown in region 544 between lines 501a and 501b, the LIO lines for LIO<1> and LIO<3> and LIOF<0> and LIOF<2> “twist” to accommodate the altered routing. LIO<1> and LIO<3> extend from an “upper” (from the perspective of the viewer) portion to a “lower” portion of the memory array 500 as well as switch which of the two LIO line is closer to the upper portion of the memory array 500. Similarly, LIOF<0> and LIOF<2> extend from the lower portion of the memory array 500 to the upper portion and switch which of the two LIO lines is closer to the lower portion of the memory array