100 when the associated write data is received.

The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to an internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the row decoder 140, the internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

The power supply terminal may also be supplied with power supply potential VDDQ. The power supply potential VDDQ can be supplied to the IO circuit 160 together with the power supply potential VSS. The power supply potential VDDQ can be the same potential as the power supply potential VDD in an embodiment of the present technology. The power supply potential VDDQ can be a different potential from the power supply potential VDD in another embodiment of the present technology. However, the dedicated power supply potential VDDQ can be used for the IO circuit 160 so that power supply noise generated by the IO circuit 160 does not propagate to the other circuit blocks.

The on-die termination terminal(s) may be supplied with an on-die termination signal ODT. The on-die termination signal ODT can be supplied to the IO circuit 160 to instruct the memory device 100 to enter an on-die termination mode (e.g., to provide one of a predetermined number of impedance levels at one or more of the other terminals of the memory device 100).

The clock terminals and data clock terminals may be supplied with external clock signals and complementary external clock signals. The external clock signals CK, CKF, WCK, and WCKF can be supplied to a clock input circuit 120. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and transition between the opposite clock levels at the same time. For example, when a clock signal is at a low clock level, a complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Moreover, when the clock signal transitions from the low clock level to the high clock level, the complementary clock signal transitions from the high clock level to the low clock level, and when the clock signal transitions from the high clock level to the low clock level, the complementary clock signal transitions from the low clock level to the high clock level.

Input buffers included in the clock input circuit 120 can receive the external clock signals. For example, when enabled by a CKE signal from the command decoder 115, an input buffer can receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 can receive the external clock signals to generate internal clock signals ICLK. The internal clock signals ICLK can be supplied to an internal clock circuit 130. The internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the received internal clock signals ICLK and a clock enable signal CKE from the command decoder 115. For example, the internal clock circuit 130 can include a clock path (not shown in FIG. 1) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. The internal clock circuit 130 can further provide input/output (IO) clock signals. The IO clock signals can be supplied to the IO circuit 160 and can be used as a timing signal for determining an output timing of read data and the input timing of write data. The IO clock signals can be provided at multiple clock frequencies so that data can be output from and input to the memory device 100 at different data rates. A higher clock frequency may be desirable when high memory speed is desired. A lower clock frequency may be desirable when lower power consumption is desired. The internal clock signals ICLK can also be supplied to a timing generator 135, and thus various internal clock signals can be generated.

The memory device 100 may additionally employ a plurality of external terminals coupled to a sideband bus. That is, the memory device may include a clock terminal to receive a sideband bus clock signal, SCL. The memory device may include an upstream data terminal to couple to an upstream (e.g., closer to the bus controller) bus data signal, SDA. And the memory device may include a downstream data terminal to couple to a downstream bus data signal, SDA_ALT. During operations, the memory device 100 may receive or transmit the signals SDA and SDA_ALT. For example, the memory device 100 may attempt to broadcast data over the sideband bus and therefore attempt to transmit over SDA and/or SDA_ALT. As a further example, the memory device 100 may not be broadcasting and instead receives sideband bus data (e.g., from a host device or another memory device) over SDA and/or SDA_ALT. As described herein, the memory device 100 may be configured to selectively couple the SDA terminal to the SDA_ALT terminal.

The memory device 100 additionally includes an I3C interface 175, which is configured to interface with the sideband bus. The I3C interface 175 may be coupled to the sideband bus signals SCL, SDA, and/or SDA_ALT and includes logic to implement all or portions of a communication protocol used by the sideband bus (e.g., I3C, M3C, or similar). That is, the I3C interface 175 may be configured to receive and decode commands transmitted over the sideband bus (e.g., from a host device or other component operating as a bus controller), perform operations based on the commands, transmit data over the sideband bus in response to the commands, etc. For example, the I3C interface 175 may be configured to receive and decode a command, broadcast by a host device, to enter a DAA mode (e.g., an ENTDAA command). In response, the I3C interface 175 can determine whether an address has already been assigned to the memory device 100 (for example, following a previous command from a host device to enter a DAA mode). If the memory device 100 has not yet been assigned an address, the I3C interface 175 can transmit device information (e.g., a provisioned ID, BCR, and/or DCR) over the sideband bus during an arbitration round. If the I3C interface 175 determines that it won the arbitration round, it can be configured to receive a dynamic address over the sideband bus and acknowledge receipt. The I3C interface 175 can also be configured to maintain the assigned dynamic address and indication that the memory device has been assigned an address (e.g., in one or more registers).

The I3C interface 175 additionally includes a DAA circuit 180, which is configured to facilitate topology-aware DAA of the memory device 100. As illustrated in FIG. 1, the DAA circuit 180 may be configured to couple the upstream data terminal of the memory device 100 to the downstream data terminal of the memory device, thereby coupling the corresponding sideband bus data signals (e.g., SDA and SDA_ALT). In embodiments, the DAA circuit 180 is configured to initially (e.g., after power on or reset of the memory device 100) uncouple the upstream data terminal from the downstream data terminal. The DAA circuit 180 may be configured to then couple the terminals once the memory device 100 has been assigned an address (e.g., as part of a DAA process). For example, the DAA circuit 180 can be configured to couple the upstream data terminal to the downstream data terminal based on a valid bit (e.g., maintained by the DAA circuit in a register) indicating the memory device 100 has been assigned an address. In other words, the DAA circuit 180 can facilitate selectively coupling downstream components (e.g., other memory devices) to the data line of a sideband bus once the memory device 100 has been assigned a dynamic address and will no longer contend with the other memory devices during a DAA process.

FIG. 2 is a simplified block diagram schematically illustrating a sideband bus interface 200, with a topology-based DAA circuit 205, in accordance with an embodiment of the present technology. The sideband bus interface 200 may be part of a memory device (e.g., a DRAM die, a DRAM device, etc.). The sideband bus interface 200 may be an example of or include aspects of the I3C interface 175 described with reference to FIG. 1. The topology-based DAA circuit 205 may be an example of or include aspects of the DAA circuit 180 described with reference to FIG. 1.

The sideband bus interface 200 may be used to enable communication between the memory device and sideband bus, such as an I3C bus or an M3C bus. The sideband bus interface 200 may couple to wires of the sideband bus, such as SCL 210 and SDA 215, through one or more external terminals and/or pads. SCL 210 may operate as the clock of the sideband bus, and SDA 215 may operate as the data line of the sideband bus. As described herein, SDA 215 may be coupled to a bus controller (e.g., a host device, memory controller, or other component therein) that controls the operation of the sideband bus. In some embodiments, SDA 215 (of the sideband bus interface 200) is directly coupled to the bus controller (e.g., there are no intervening devices on the sideband bus). In some embodiments, the coupling between SDA 215 (of the sideband bus interface 200) and the bus controller passes through one or more other devices on the sideband bus (e.g., memory devices), such as in a daisy chain. Any intervening devices between the memory device of the sideband bus interface 200 and the bus controller may be referred to as upstream devices.

The sideband bus interface 200 includes I3C logic 220, which implements at least a portion of the communication protocol used by the sideband bus (e.g., I3C, M3C, or similar). The I3C logic 220 may be configured to detect and decode commands transmitted by the bus controller over SDA 215, perform operations based on the commands (e.g., performing bus functions, performing functions on the memory device, etc.), and transmit data over SDA 215. For example, upon detecting a command to enter a DAA mode (e.g., an ENTDAA command), the I3C logic 220 may be configured to attempt to transmit information associated with the memory device (e.g., provisioned ID, BCR, and DCR) over SDA 215 during an arbitration round if the memory device has not already been assigned an address. If the I3C logic 220 determines that it won the arbitration round (e.g., it transmitted the lowest-valued provisioned ID, BCR, and DCR among the memory devices participating in the arbitration round), it can be configured to receive a dynamic address (assigned by the bus controller) from SDA 215 and save the dynamic address to a dynamic address register 225. The I3C logic 220 can also set a DA valid flag 230 (e.g., in a register) to indicate that an address has been assigned to the memory device. During subsequent arbitration rounds of the DAA mode, the I3C logic 220 may be configured not to participate (e.g., not to transmit device information and detect a win condition) based on the state of the DA valid flag 230.

The sideband bus interface 200 may also couple to an additional sideband bus wire SDA_ALT 235 through an external terminal and/or pad. SDA_ALT 235 may provide the data line of the sideband bus to downstream devices (e.g., memory devices farther from the bus controller). That is, as described herein, SDA_ALT 235 may connect to the SDA external terminal and/or pad of a downstream device. During operation of the sideband bus interface 200, and the memory device of which it is a part, SDA 215 and SDA_ALT 235 may be selectively coupled or uncoupled. When coupled, a logical connection is formed between SDA 215 and SDA_ALT 235 so that a value on SDA propagates to SDA_ALT (e.g., a value broadcast by the memory device of sideband bus interface 200, an upstream memory device, and/or the bus controller propagates to a downstream memory device), and a value on SDA_ALT propagates to SDA (e.g., a value broadcast by a downstream memory device propagates to the memory device of the sideband bus interface, upstream memory devices, and/or the bus controller). When uncoupled, values do not propagate between SDA 215 (e.g., associated with a bus controller, upstream memory devices, and/or the memory device of sideband bus interface 200) and SDA_ALT 235 (e.g., associated with downstream memory devices).

Coupling between SDA 215 and SDA_ALT 235, at the sideband bus interface 200, may be controlled by the topology-based DAA circuit 205. The topology-based DAA circuit 205 may include a transmission gate 240, configurable to connect SDA 215 to SDA_ALT 235. For example, the transmission gate 240 may connect SDA 215 to SDA_ALT 235 once the memory device of sideband bus interface 200 has been dynamically assigned an address. In some embodiments, the transmission gate 240 is controlled by DA valid flag 230. In embodiments, DA valid flag 230 may initially (e.g., after power on and/or reset of the memory device) indicate that the memory device has not been dynamically assigned an address. For example, DA valid flag 230 may be provided by a register that resets to a logical value of 0. Once DA valid flag 230 is set after the memory device has been assigned an address (e.g., following a portion of a DAA process, as described herein), transmission gate 240 is activated to connect SDA 215 and SDA_ALT 235. For example, as illustrated in FIG. 2, transmission gate 240 may be controlled by DA valid flag 230 and its inverse.

The topology-based DAA circuit 205 may also be configured to drive a known static value on SDA_ALT 235 (e.g., the sideband bus data wire of downstream memory devices), when SDA_ALT and SDA 215 are not coupled, to prevent SDA_ALT from floating (e.g., having an unknown value). For example, as illustrated in FIG. 2, the topology-based DAA circuit 205 may connect SDA_ALT 235 to VDD 245 through a weak pull-up resistor 250. The resistance of weak pull-up resistor 250 may be such that when transmission gate 240 enables the connection between SDA 215 and SDA_ALT 235, logical 0 values (e.g., VSS) may propagate between SDA and SDA_ALT despite the connection to VDD 245 (e.g., SDA_ALT does not remain stuck at VDD).

FIG. 3 is a simplified block diagram schematically illustrating a daisy chain 300 between memory devices with topology-based DAA circuits, forming a sideband bus, in accordance with an embodiment of the present technology. The daisy chain 300 may be formed by one or more memory devices 305, each of which may have logic to perform topology-based DAA. For example, each of the memory devices 305 may be a memory device 100 described in reference to FIG. 1 and/or a topology-based DAA circuit 205 described in reference to FIG. 2.

As illustrated in FIG. 3, the daisy chain 300 can include memory device 305-1, memory device 305-2, etc., up to memory device 305-n (e.g., any number of memory devices). The memory devices 305 may be part of a memory module (e.g., a DIMM) or other arrangement in a memory system (e.g., on multiple DIMMs). Based on their topology on the daisy chain 300, the memory devices 305 may have a different priority for being assigned an address during a DAA process. For example, in the embodiment illustrated in FIG. 3, memory device 305-1 is the highest priority memory device (e.g., the first of the memory devices 305 to be assigned an address during a DAA process), and memory device 305-n is the lowest priority memory device (e.g., the last of the memory devices to be assigned an address during a DAA process). As described herein, memory device 305-1 may have the highest priority due to it being the closest to a bus controller 310 (e.g., a memory controller, host device, or other component of a memory system) on a sideband bus 315.

The sideband bus 315 includes an SCL wire 320, which can be used to provide the clock line for the sideband bus. The SCL wire 320 is common to all memory devices 305. That is, as illustrated in FIG. 3, the same SCL wire 320 (e.g., driven by the bus controller 310) connects to the SCL terminals of all memory devices 305 (e.g., memory device 305-1, memory device 305-2, etc., up to memory device 305-n).

The sideband bus 315 additionally includes one or more SDA segments, which collectively form the data line of the sideband bus. Each SDA segment serially connects a memory device (e.g., one of memory devices 305-1 through 305-n) to another memory device or connects the bus controller 310 to a first memory device (e.g., the highest priority memory device). SDA segments connecting two memory devices 305 may connect to an upstream data line terminal of one of the memory devices (e.g., an SDA pad) and to a downstream data line terminal of the other memory device (e.g., an SDA_ALT pad). Further, the SDA segment connected to the highest priority memory device may connect to its upstream data line terminal (e.g., the SDA pad). For example, as illustrated in FIG. 3, bus controller 310 and memory device 305-1 are connected by SDA segment 325-1; the SDA segment connects to the SDA pad of the memory device. Further, SDA segment 325-1 connects to the SDA_ALT pad of memory device 305-1 and the SDA pad of memory device 305-2 to connect those two memory devices. Still further, SDA segment 325-3 connects to the SDA_ALT pad of memory device 305-1 and to the SDA pad of the next lowest priority memory device on the sideband bus 315 (not shown). Similarly, memory device 305-n (illustrating the lowest priority memory device on the sideband bus 315) connects to SDA segment 325-n via the memory device's SDA pad; the SDA segment also connects to the SDA_ALT pad of the next highest priority memory device (not shown). As illustrated in FIG. 3, the SDA_ALT pad of each memory device 305 may additionally be coupled to VDD through a pull-up resistor.

As described herein, each SDA segment may be selectively coupled to or uncoupled from the next SDA segment in the daisy chain 300 based on the operation of the memory devices 305 (e.g., the topology-based DAA circuits therein). For example, when the memory devices 305 are in an initial state (e.g., after power on or reset), the topology-based DAA circuits of each memory device may uncouple their SDA pad from their SDA_ALT pad. A memory device may be configured to leave its SDA pad uncoupled from its SDA_ALT pad until the memory device has been assigned an address as part of a DAA process. As a result, during an initial period (e.g., prior to the completion of a first phase of a DAA process), only memory device 305-1 is configured to receive data signals broadcast by bus controller 310 (since SDA segment 325-1 is connected to its SDA pad); all other memory devices are uncoupled from the upstream SDA segments and do not receive data broadcast by the bus controller. After an address is assigned to memory device 305-1 (e.g., during a first phase of a DAA process), the topology-based DAA circuit of the memory device couples its SDA and SDA_ALT pads, thereby coupling SDA segment 325-2 to SDA segment 325-1. As a result, memory device 305-2 becomes coupled to the data portion of sideband bus 315 and is able to receive data broadcast by bus controller 310. After the memory device 305-2 is assigned an address during a next phase of the DAA process, it couples its SDA and SDA_ALT pads, thereby coupling SDA segment 325-2 and SDA segment 325-3 and coupling the next memory device to the data portion of sideband bus 315. The process continues until the lowest memory device (e.g., memory device 305-n) is coupled to the data portion of sideband bus 315, after which it may be assigned an address via the DAA process. By coupling the memory devices 305 to the data portion of sideband bus 315 in a serial fashion, after which an address may be assigned to the most recently coupled memory device, addresses may be assigned to the memory device in a predictable fashion (e.g., based on their proximity to bus controller 310 along the daisy chain 300).

In some embodiments, additional devices other than memory devices 305 may also be coupled to the sideband bus 315 to communicate with the bus controller 310. For example, one or more temperature sensors, power management integrated circuits (PMICs), and/or other devices can share the sideband bus 315 with the memory devices 305 (e.g., are part of the same group). In some embodiments, one or more other devices (e.g., temperature sensors and/or PMICs) are coupled to a separate sideband bus, not shown, that also couples to the bus controller 310 (e.g., the devices are part of a group separate from the memory devices 305).

FIG. 4 is a flow diagram illustrating a process 400 for assigning topology-based dynamic addresses in accordance with an embodiment of the present technology. Aspects of the process 400 can be performed, for example, by a component of a memory system operating as a controller of a sideband bus (e.g., a bus controller), such as a host device, memory controller, or combination thereof. The bus controller can perform the process 400 in compliance with I3C, M3C, or other specification of a sideband bus. Although the process 400 describes transmitting and receiving values, in embodiments, each value and each portion of a value are transmitted serially over one or more clock cycles. For example, one data bit may be transmitted or received over the sideband bus per clock cycle. In some embodiments, a value transmitted by one device is received by multiple other devices on the sideband bus (e.g., the value is broadcast).

The process 400 begins at block 405, where a bus controller transmits a start or repeated start indication over the sideband bus. For example, the bus controller may transmit the start indication the first time performing block 405 and may transmit the repeated start indication when subsequently performing block 405.

At block 410, the bus controller transmits a global broadcast address and a write indication. The global broadcast address may be transmitted so that other devices on the sideband bus, such as memory devices (e.g., targets), see a command code to be subsequently transmitted. The write indication may indicate that the transmitter (e.g., bus controller) is writing a message to the targets. In some embodiments, the global broadcast address is a 7-bit value, such as 7′h7E. In some embodiments, the write indication is transmitted as an RnW bit set to the value 1′b0.

At block 415, the bus controller receives an acknowledgement (e.g., ACK) from the targets. In some embodiments, targets (e.g., the memory devices on the sideband bus) acknowledge by driving a data line of the sideband bus (e.g., SDA) low. In some embodiments, targets on the bus will send an acknowledgement regardless of whether the target has been assigned a dynamic address.

At block 420, the bus controller transmits a command to instruct targets to enter a DAA procedure. In some embodiments, the command is an ENTDAA command as defined by the I3C specification. In some embodiments, the command is similar to the I3C ENTDAA command (e.g., an “enter dynamic address assignment” command as defined by the M3C specification).

At block 425, the bus controller transmits a repeated start indication, the global broadcast address, and a read indication. In some embodiments, the read indication is transmitted as an RnW bit set to the value of 1′b1. In some embodiments, every target on the sideband bus that supports DAA and does not yet have an assigned dynamic address is configured to acknowledge the transmitted broadcast address.

At decision block 430, the bus controller determines whether it receives at least one acknowledgement from the targets on the sideband bus (e.g., memory devices). In some embodiments, at most one target will acknowledge the broadcast address transmitted at block 425. For example, as described herein, in some embodiments, only one memory device coupled to the data portion of the sideband bus will not yet have an assigned dynamic address and therefore will acknowledge (where upstream memory devices already have been assigned a dynamic address and therefore do not acknowledge, and downstream memory devices have not yet been coupled to the data portion of the sideband bus and therefore do not receive the transmitted information). If the bus controller determines that at least one target acknowledges the broadcast address, then processing continues to block 435. If the bus controller determines that no targets acknowledged the broadcast address (e.g., a negative acknowledgement, or NACK), then the process ends.

At block 435, the bus controller receives device information over the sideband bus. The device information can include a provisioned ID, BCR, and/or DCR. In some embodiments, the device information is received during an arbitration round. In some embodiments, only a single memory device participates in the arbitration round (e.g., the memory device most recently coupled to the data portion of the sideband bus).

At block 440, the bus controller assigns a dynamic address to the memory device associated with the received device information (e.g., the winning memory device of the arbitration round). In some embodiments, the assigned dynamic address follows a predictable pattern with respect to a previously assigned dynamic address (e.g., from the previous arbitration round). For example, the bus controller, memory controller, and/or firmware of the memory system may be configured to assign addresses according to a specified pattern. In some embodiments, the assigned dynamic address may be the next sequential (greater or lower) address after the previously assigned dynamic address. For example, addresses may be in a monotonically increasing or decreasing manner (e.g., in increments or decrements of 1, 2, 3, etc.) with each next memory device starting from the first memory device (e.g., the memory device closest on the bus to the bus controller). In some embodiments, addresses are assigned such that the memory devices in the middle of the bus (e.g., between the bus controller and the last memory device in a daisy chain) have the lower-valued addresses. In embodiments, other address assignments may be used that assign lower-valued addresses (e.g., higher priority addresses) to memory devices depending on the topology, such that those devices are given higher priority. The bus controller may additionally maintain an association between the newly assigned dynamic address and the device information (and, therefore, the corresponding memory device). Since the dynamic addresses are assigned to the memory devices in a predictable manner (e.g., the address incrementing with each memory device that is farther on the sideband bus from the bus controller), the maintained association facilitates targeting known memory devices based on their assigned address. For example, a bus controller can target the nearest memory device using the lowest-valued assigned address, the further memory device used the highest-valued assigned address, etc.

At block 445, the bus controller transmits the assigned dynamic address to the winning memory device. At block 450, the bus controller receives an acknowledgement or a negative acknowledgement from the winning device, therefore concluding a phase or round of DAA. In some embodiments, if the bus controller receives a negative acknowledgement (e.g., indicating that the winning device did not successfully receive the transmitted dynamic address), then the address that had been assigned is freed to be reassigned during a subsequent arbitration round.

The process 400 then returns to block 405 to transmit a repeated start prior to transmitting the global broadcast address and write indication (at block 410), instructing memory devices to enter a DAA procedure (at block 420) and determining whether another round of arbitration and address assignment is needed (at decision block 430) (e.g., for another phase of DAA). It will be noted that in contrast to other DAA processes that do not involve repeated transmissions of the command to enter a DAA procedure, the illustrated embodiment of process 400 transmits the enter DAA command after each phase of DAA. For example, the bus controller retransmits the enter DAA command with each new phase because memory devices downstream of the one assigned an address during the previous phase were not coupled to the data portion of the sideband bus during that previous phase.

FIG. 5 is a flow diagram illustrating a process 500 for being assigned a topology-based dynamic address in accordance with an embodiment of the present technology. Aspects of the process 500 can be performed, for example, by a target device on a sideband bus, such as a memory device and/or a topology-based DAA circuit that is part of the device. For example, the process 500 can be performed by the memory device 100 illustrated in FIG. 1 (in some embodiments including the I3C interface 175 and/or DAA circuit 180), sideband bus interface 200 illustrated in FIG. 2, and/or one of the memory devices 305 illustrated in FIG. 3. The target device can perform the process 500 in compliance with I3C, M3C, or other specification of a sideband bus. Although the process 500 describes transmitting and receiving values, in embodiments, each value and each portion of a value are transmitted serially over one or more clock cycles. For example, one data bit may be transmitted or received over the sideband bus per clock cycle. In some embodiments, a value transmitted by one device is received by multiple other devices on the sideband bus (e.g., the value is broadcast).

The process 500 begins at block 505, where a target device receives a command to enter a DAA procedure. In some embodiments, the received command is an ENTDAA command as defined by the I3C specification. In some embodiments, the received command is similar to the I3C ENTDAA command (e.g., an “enter dynamic address assignment” command as defined by the M3C specification).

At block 510, the target device receives a repeated start indication, a global broadcast address, and a read indication. In some embodiments, the read indication is received as an RnW bit set to the value of 1′b1. In some embodiments, the global broadcast address is a 7-bit value, such as 7′h7E.

At decision block 515, the target device determines whether it has an assigned address. In some embodiments, the determination is made based on a dynamic address register and/or valid register maintained by the target device (e.g., does the register indicate a valid address). As described herein, the target device may have been assigned a dynamic address during a DAA process. If the target device determines that it has an assigned address, processing continues to block 520. If the target device determines that it does not have an assigned address, processing continues to block 525.

If at decision block 515, the target device determined that it has an assigned address, then at block 520, the target device transmits a negative acknowledgement. In some embodiments, the target device indicates a negative acknowledgement by driving the data portion of the sideband bus high or by not driving a value on the data portion of the sideband bus. The process 500 then ends.

If at decision block 515, the target device determined that it has not been assigned an address, then at block 525, the target device transmits an acknowledgement. In some embodiments, the target device indicates an acknowledgement by driving the data portion of the sideband bus low.

At block 530, the target device transmits device information associated with it. The device information can include a provisioned ID, BCR, and/or DCR.

At decision block 535, the target device determines whether it won arbitration during transmission of the device information (at block 530). In some embodiments, the target device determines whether it won arbitration based on whether it successfully transmitted the device information over the sideband bus. For example, the sideband bus may be configured (e.g., by operation of the bus controller) to have a default logic high value (e.g., 1). The default logic high value may be overridden if a target device attempts to transmit a logic low value (e.g., 0) over the sideband bus. The target devices and sideband bus may be configured so that if one target device attempts to transmit a logic high value and another target device attempts to transmit a logic low value, the target device transferring the logic low value wins (e.g., the sideband bus goes low). A target device wins arbitration if it transmitted its device information without being overridden by another target device during transmission (e.g., the target device transmitted its device information without an occurrence of it attempting to transmit a logic high value when at the same time another target device attempted, and succeeded in, transferring a logic low value). In some embodiments, the target device with the lowest-valued device information wins arbitration. In some embodiments, no other devices attempt to transmit their device information (e.g., based on the operation of topology-based DAA circuits), and the target device will win arbitration. If the target device determines that it won arbitration, processing continues to block 540. If the target device determines that it did not win arbitration, the process 500 ends.

At block 540, the target device receives a dynamic address over the sideband bus (e.g., from the bus controller). In some embodiments, the received dynamic address is a 7-bit value assigned by the bus controller.

At block 545, the target device saves the received dynamic address. For example, the target device may save the received dynamic address in a dynamic address register. The target device may also set a flag (e.g., in a register) indicating it has a valid dynamic address. As described herein, following the saving of the assigned dynamic address, the target device may couple an upstream data terminal (e.g., SDA) with a downstream data terminal (e.g., SDA_ALT) of the target device.

At block 550, the target device transmits an acknowledgement indication. The process 500 then ends.

FIG. 6 is a timing diagram illustrating a topology-based DAA sequence 600 in accordance with an embodiment of the present technology. The topology-based DAA sequence 600 involves bus communications 605 over a sideband bus, such as an I3C bus, M3C bus, or other. As illustrated in FIG. 6, the bus communications 605 may include communications from a bus controller (e.g., a memory controller, host device, and/or other component of a memory system) as well as from one or more target devices (e.g., memory devices). In particular, the topology-based DAA sequence 600 may involve repeated broadcasts 610 of an enter DAA command by the bus controller.

As illustrated in FIG. 6, during an initial phase of the topology-based DAA sequence 600, a Die0 SDA 615 may be active. In the embodiment illustrated in FIG. 6, Die0 may be the highest priority of multiple memory dies on the sideband bus (e.g., the one closest to the bus controller on the sideband bus data chain), and its SDA terminal may be directly coupled to the SDA terminal of the bus controller. That is, Die0 may be capable of receiving data from, and transmitting data to, the bus controller over the sideband bus SDA line first (e.g., before other memory dies). As a result, Die0 completes DAA phase 620 in response to the first enter DAA command broadcast by the bus controller.

Following the completion of DAA phase 620 by Die0, Die1 SDA 625 goes active. As described herein, Die0 may couple its SDA terminal to its SDA_ALT terminal, therefore activating its SDA_ALT terminal (e.g., coupling its SDA_ALT to the sideband bus SDA line and the bus controller), after it has been dynamically assigned an address. Further, Die0 SDA_ALT may be coupled to Die1 SDA 625, such that the activation of Die0 SDA_ALT further activates Die1 SDA. As a result, when the bus controller broadcasts the second enter DAA command, Die1 completes DAA phase 630.

Following the completion of DAA phase 630 by Die1, Die2 SDA 635 goes active (e.g., by way of Die1 coupling its SDA and SDA_ALT terminals). The topology-based DAA sequence 600 continues, with dies completing DAA phases (e.g., being assigned an address) and activating the SDA line of the next lowest priority memory die. Eventually, the memory die with the second lowest priority, DieN−1, is assigned a dynamic address and activates DieN SDA