114 is made conductive by the application of a low potential or level, for example, the ground, to the conductor of this gate 114.

When gates 114 are in the off state, this prevents the transfer, to regions 114, of the useful charges photogenerated and accumulated in the portion of the substrate 100 of pixel Pix. As an example, when substrate 100 is P-type doped and the useful charges are holes, each gate 114 is made non-conductive by the application of a high potential or level, for example, power supply potential Vdd, to the conductor of gate 114. As an example, during the acquisition of a depth map, the gates 114 of pixel Pix are sequentially switched to the on state one after the other, preferably for an identical time period for each gate 114, with or without an overlapping of their on-states, so that the photogenerated useful charges are alternately transferred to each of regions 112. A sequence corresponding to the successive switching of each of the gates 114 of pixel Pix is, preferably, repeated a large number of times during an integration period corresponding to the acquisition of a depth map by the sensor.

As an example, when the sensor acquires a color or black-and-white image, gates 114 are maintained non-conductive during the integration period corresponding to this acquisition, gate 110 being also maintained non-conductive, and during the period of reading out from pixel Pix corresponding to this acquisition, gate 110 then being switched to the on-state to transfer useful charges from substrate 100 to region 108.

Although this is not shown in FIGS. 1 and 2, the sensor comprises a control circuit configured to control gates 110 and 114 as described hereabove.

According to an embodiment, the gate trench for each gate 114 penetrates into substrate 100 deeper than the gate trench for gate 110. This enables to favor, when a gate 114 is set to the on-state and gate 110 is in the off-state, the transfer of the photogenerated useful charges which are located under the assembly of gate 110 and of region 108, to the region 112 associated with this gate 114.

According to an embodiment, although this is not illustrated in FIGS. 1 and 2, each region 112 is coupled, for example connected, to an electrode of a corresponding capacitive element forming, for example, a memory cell. In such an embodiment, during the acquisition of a depth map, the sensor can operate in a global shutter mode, each pixel then operating in the voltage domain. In this example where the photogenerated useful charges are holes, the other electrode of the capacitive element is coupled, for example, connected, to a high potential or level, for example, potential Vdd. In another example, not illustrated, where the photogenerated useful charges are electrons (N-type doped substrate 100), the other electrode of the capacitive element is coupled, for example, connected, to a low potential or level, for example, ground potential GND.

According to an embodiment, for each region 114, the capacitive element which is associated therewith is of metal-insulator-metal (MIM) type. As an example, for each region 114, the capacitive element which is associated therewith is implemented in an interconnection structure resting on surface 102 of substrate 100. This interconnection structure is, for example, that provided for substrate 100 and is configured to connect together and to the outside elements formed from substrate 100. In the case where substrate 100 is assembled with another semiconductor substrate, for example, by molecular bonding of the interconnection structure of substrate 100 to the interconnection structure of this other substrate, the capacitive element may be implemented in one or the other of these interconnection structures.

According to an embodiment, in each pixel Pix, the portion of substrate 100 where charges are photogenerated when the sensor receives light and the vertical insulation structures 106 which surround this portion of substrate 100 are configured so that this portion of substrate 100 corresponds to or implements a pinned photodiode. According to an embodiment, during the acquisition of a color or black-and-white image, the sensor may operate in rolling shutter mode, each pixel then operating, for example, in the charge domain.

In an alternative embodiment, region 108 is coupled, for example, connected, to an electrode of a capacitive element, for example, of MIM type, similarly to what has been previously described for each of regions 112, so that, during the acquisition of a color or black-and-white image, the sensor can operate in global shutter mode, each pixel Pix then operating, for example, in the voltage domain.

Preferably, the sensor of FIGS. 1 and 2 is configured to receive light, for example visible light and/or infrared light, on the side of its surface 104. The sensor is thus of the type commonly referred to in the art as being back side illuminated.

Although this is not shown in FIGS. 1 and 2, as an example, each pixel comprises a doped well of the second conductivity type, for example, type N, arranged on the side of surface 102 of the substrate. As an example, one or a plurality of transistors of the pixel are arranged inside and on top of this well of the pixel, for example, transistors of circuits for reading out from the pixel. As an example, in the case where substrate 100 is assembled to another semiconductor substrate (three-dimensional integration), transistors of the readout circuits and/or of the control circuit and/or of a circuit for processing the data read from the pixels may be formed from this other substrate, that is, be arranged inside and on top of this other substrate. According to another example, when substrate 100 is not assembled to another semiconductor substrate (monolithic integration), all the transistors of the sensor circuits, for example, of pixel readout circuits and/or of the pixel control circuit and/or of the circuit for processing the read data, are implemented from substrate 100.

Preferably, in each pixel Pix, a heavily-doped layer of the second conductivity type, for example, of type N in this example where the photogenerated useful charges are holes, is formed at the surface 102 of substrate 100, this layer being for example only interrupted by structure 106, gates 110 and 144, and regions 108 and 112.

In the embodiment of FIGS. 1 and 2, each gate 114 is arranged between gate 110 and insulation structure 106. In other words, each gate 114 is separated from structure 106 by a portion of substrate 100. Thus, each pixel Pix of the pixel array of the sensor has its own transfer gates 114 that it does not share with its neighboring pixels.

FIGS. 3, 4, and 5 illustrate an alternative embodiment of the sensor of FIGS. 1 and 2, wherein each pixel Pix of the array shares its gates 114 with its neighboring pixels, for example, by sharing each of its gates with a different neighboring pixel so that each gate 114 is shared by two neighboring pixels Pix only.

FIG. 3 is a simplified top view of the sensor according to this alternative embodiment, FIG. 4 corresponding to a simplified cross-section view of the sensor of FIG. 3, taken along a cross-section plane AA of FIG. 3, and FIG. 5 corresponding to a simplified cross-section view of the sensor of FIG. 3, taken along a cross-section plane BB of FIG. 3.

Only the differences between the sensor of FIGS. 1 and 2 and that of FIGS. 3 to 5 are here highlighted, and, unless otherwise indicated, all that has been described in relation with FIGS. 1 and 2 applies to the sensor of FIGS. 3 to 5.

In the alternative embodiment of FIGS. 3 to 5, similarly to what has been described as an example in relation with FIGS. 1 and 2, each pixel Pix shares portions of its insulation structure 106 with the pixels Pix surrounding it. Further, in this variant, each gate 114 of each pixel Pix is aligned with, and insulated from, vertical insulation structure 106, and thus can be seen to form a portion of vertical insulation structure 106. In other words, each gate 114 replaces a portion of structure 106. Still in other words, each gate 114 penetrates, from the surface 102 of substrate 100, into structure 106. Preferably, as can be seen in FIG. 3, for each gate 114, the vertical walls of gate 114 which are in respective contact with two neighboring pixels Pix sharing this gate 114, are aligned with the vertical walls of structure 106 which are in respective contact with these two neighboring pixels Pix.

As an example, each gate 114 shared by two neighboring pixels Pix forms a portion of the portion of insulation structure 106 which is shared by these two neighboring pixels.

As an example, FIG. 5 illustrates in further detail a gate 114. Gate 114 comprises a gate conductor 1141 insulated from structure 106 and from substrate 100 by a gate insulator layer 1142.

The provision of a vertical gate 114 forming part of vertical insulation structure 106 between two neighboring pixels, so that this gate 114 is shared between these two neighboring pixels, is for example described in further detail in United States Patent Application Publication No. 2021/0020675 (corresponding to French Patent 3098988), incorporated herein by reference. See, for example, FIGS. 6 to 13. In particular, FIGS. 8 to 13 describe examples of methods of manufacturing such a transfer gate.

The provision of gates 114 as being incorporated in insulation structure 106 enables to avoid the presence of a portion of substrate 100 located between each gate 114 and insulation structure 106, which enables to decrease the dimensions of each pixel Pix with respect to the case of FIGS. 1 and 2.

As an example of dimensions, in the sensor described in relation with FIGS. 1 to 5: the thickness of substrate 100, taken between surfaces 102 and 104, is in the range from 8 to 4 μm, for example substantially equal to 6 μm, for example equal to 6 μm; for each gate 110, the distance between two opposite portions of gate 110, for example, between two parallel sides of gate 110 of square ring shape in top view, is in the range from 200 nm to 400 nm, for example, substantially equal to 300 nm, for example equal to 300 nm; each gate 114 is arranged at a distance from the corresponding portion of gate 110 which is in the range from 300 to 500 nm, for example, substantially equal to 400 nm, for example, equal to 400 nm; each gate 110 penetrates into substrate 100 down to a depth in the range from 0.6 μm to 1 μm, for example substantially equal to 0.8 μm, for example equal to 0.8 μm; and each gate 114 penetrates into substrate 100 down to a depth in the range from 1 μm to 1.5 μm, for example, substantially equal to 1.2 μm, for example, equal to 1.2 μm.

FIG. 6 partially shows a circuit of a pixel Pix of the sensor of FIGS. 1 to 5 according to an embodiment.

In particular, in this embodiment, pixel Pix comprises two assemblies of a gate 114 and of a region 112, the gate 114 and the region 112 of a first one of the two assemblies bearing respective references TGMEM1 and SN1 in FIG. 6, and the gate 114 and the region 112 of the second one of the assemblies bearing respective references TGMEM2 and SN2 in FIG. 6. It will be within the abilities of those skilled in the art to adapt the description made hereafter in relation with FIG. 6 to the case of a pixel Pix comprising more than two assemblies of a gate 114 and of a region 112.

In this embodiment, during the acquisition of a depth map, the sensor is configured to operate in global shutter mode. As an example, pixel Pix then comprises a capacitive element C1 connected between node SN1 and a node of application of a high potential or level, for example, potential Vdd, in this example where the useful charges are holes, and a capacitor C2 connected between node SN2 and a node of application of the same high potential or level Vdd.

In FIG. 6, region 108 and gate 110 are respectively designated with references SN0 and TG0. Further, in this embodiment, the sensor is configured to operate in rolling shutter mode on acquisition of a color or black-and-white image. More particularly, in the example of FIG. 6, node SN0 is shown as the electrode of a diode D1. In this example where the useful charges are holes, node SN0 corresponds to the anode of diode D1 and the cathode of diode D1 is connected to a node of application of a high potential or level, for example, potential Vdd. It will be within the abilities of those skilled in the art to adapt the above description to the case where the sensor is configured to operate in global shutter mode during the acquisition of a color or black-and-white image, for example, by connecting a memory cell, for example, in the form of a capacitive element, to node SN0.

In FIG. 6, the portion of the substrate 100 of pixel Pix where charges are photogenerated, that is, for example, a pinned photodiode, is represented by a photodiode PD. In this example, where the photogenerated useful charges are holes, the cathode of photodiode PD is connected to a node of application of a high potential, for example, power supply potential Vdd, and the anode 600 of photodiode PD is coupled to each of nodes SN0, SN1, and SN2 by respective gates TG0, TGMEM1, and TGMEM2.

In FIG. 6, transfer gates TG0, TGMEM1, and TGMEM2 are each shown in the form of a MOS transistor. In this example where the photogenerated useful charges are holes, transistors TG0, TGMEM1, and TGMEM2 have a P channel. As an example, transistor TG0 has a conduction terminal connected to photodiode PD, for example, to the anode 600 of photodiode PD, and another conduction terminal connected to node SN0. As an example, transistor TGMEM1 has a conduction terminal connected to photodiode PD, for example, the anode 600 of photodiode PD, and another conduction terminal connected to node SN1. As an example, transistor TGMEM2 has a conduction terminal connected to photodiode PD, for example, the anode 600 of photodiode PD, and another conduction terminal connected to node SN2. Transistors TG0, TGMEM1, and TGMEM2 receive on their control terminals the respective control signals sig0, sig1, and sig2. The conduction terminals of each of transistors TG0, TGMEM1, and TGMEM2 corresponds, in practice, to the gate conductor of each of the transfer gates, respectively TG0, TGMEM1, and TGMEM2.

As an example, the sensor comprises a control circuit CTRL configured to control gates TG0, TGMEM1, and TGMEM2, that is, to deliver signals sig0, sig1, and sig2 to each pixel Pix of the sensor, and, for example, to also deliver other control signals to these pixels Pix. Preferably, circuit CTRL is common to all the pixels Pix of the sensor.

According to an embodiment, each node SN0, SN1, SN2 is associated, for example, coupled or connected, to a corresponding readout circuit shown in FIG. 6 in the form of a block, respectively RD0, RD1, RD2. As an example, although this is not detailed in FIG. 6, each circuit RD0, RD1, and RD2 is implemented from MOS transistors, for example, from at least one MOS transistor assembled as a source follower and from at least one transistor for selecting the pixel Pix. As an example, each circuit RD0, RD1, and RD2 receives control signals (not illustrated) delivered by control circuit CTRL. The implementation of circuits RD0, RD1, and RD2 is within the abilities of those skilled in the art, many pixel readout circuits being described in the literature, these circuits being adapted to reading out from pixels operating in the voltage domain, or to reading out from pixels operating in the charge domain, and to reading out from pixels implementing image (color or black-and-white) or depth map acquisitions in global shutter mode or in rolling shutter mode.

Preferably, according to an embodiment, the sensor pixels Pix, particularly readout circuits RD0, RD1, and RD2 and control circuit CTRL, are configured so that: during the acquisition of an image (color or black-and-white) by the pixels, the sensor operates in rolling shutter mode, and during the acquisition of a depth map by the pixels, the sensor operates in global shutter mode.

Such an embodiment enables to avoid the provision of an intermediate (charge or voltage) memory area coupled to node SN0.

Such an embodiment further enables to implement the acquisition of a depth map by illuminating the scene to be captured only during an integration time period, common or simultaneous for all the sensor pixels. The illumination of a scene to be captured for the acquisition of a depth map generally being implemented by a laser delivering an amplitude-modulated infrared light, this enables to decrease the time of use of the laser, and thus the resulting electric power consumption.

Operations in global shutter mode or in rolling shutter mode are well known by those skilled in the art and will not be detailed herein. Further, it will be within the abilities of those skilled in the art to adapt the sensor to the case where the acquisition of a color of black-and-white image is implemented according to a global shutter mode, for example by providing a (charge or voltage) memory area coupled to node SN0 and/or to the case where the acquisition of a depth map is implemented according to a rolling shutter mode.

According to an embodiment, pixel Pix comprises a transistor RST configured to initialize the potential of node SN0, for example at a low initialization potential or level in the case where the photogenerated useful charges are holes, for example, at ground GND. Transistor RST may form part of readout circuit RD0.

Transistor RST is, for example, a MOS transistor. Transistor RST has a conduction terminal coupled, preferably connected, to node SN0, and another conduction terminal coupled, preferably connected, to a node at the initialization potential, that is, ground GND in this example. The control terminal of transistor RST receives a control signal reset. As an example, signal reset is delivered by circuit CTRL.

FIG. 7 illustrates, in timing diagrams, an example of an implementation mode of a color or black-and-white image acquisition in the sensor of FIGS. 1 to 5.

In this example, each pixel Pix of the sensor is of the type illustrated in relation with FIG. 6, that is, during the acquisition of a color or black-and-white image by the sensor, each pixel Pix operates in the charge domain and the sensor operates in rolling shutter mode. In other words, the operation of the pixel Pix described herein is preferably common and simultaneous in all the pixels Pix of the row to which this pixel belongs.

It will be within the abilities of those skilled in the art to adapt the description made hereafter in relation with FIG. 7 to the case where, during the acquisition of a color or black-and-white image by the sensor, each pixel Pix operates in the voltage domain and/or the sensor operates in global shutter mode.

In this example, the photogenerated useful charges are holes.

At a time t0, pixel Pix is in a light integration phase INT, that is, for example, useful charges are photogenerated by light reaching the pixel, and these useful charges are accumulated in the pixel photodiode PD. For this purpose, gates TG0, TGMEM1, and TGMEM2 are in the off-state and receive, for example, respective signals sig0, sig1, and sig2 in the high state or level.

Although this is not illustrated in FIG. 7, before time t0, integration phase INT starts at the end of a phase R of initialization of photodiode PD during which photodiode PD is emptied of the photogenerated charges that it contains.

At a time t1 subsequent to time t0, pixel Pix is selected. As an example, pixel Pix is selected by switching a selection signal delivered to circuit RD0 by circuit CTRL, for example, to electrically couple a node of circuit RD0 to a pixel readout line, for example, common to all the pixels of a same column. As an example, the node of circuit RD0 is coupled to the readout line by a selection MOS transistor set to the on-state by the switching of the selection signal.