Accordingly, when a read operation is performed on the memory cell MC in the reset state RESET, a current having the same direction as the direction when the state of the memory cell MC transitions to the set state SET may be provided to the memory cell MC. Therefore, the voltage level of the threshold voltage Vth of the memory cell MC in the reset state RESET may be lowered (e.g., change in the direction of an arrow D shown in FIG. 5).

The semiconductor device according to an embodiment of the present disclosure may determine the state of the memory cell MC by providing the second bias voltage V_2 (read voltage) to the memory cell MC for a set time after the start of a read operation.

Furthermore, after the start of a read operation, when the state of the memory cell MC is determined, that is, when the second bias voltage V_2 (read voltage) that is provided to the memory cell MC is discontinued, the semiconductor device according to an embodiment of the present disclosure may generate undershoot on a current path including the memory cell MC. While the undershoot is performed, the memory cell MC may be provided with an undershot current having a direction that is opposite the direction of a current provided after the start of the read operation, that is, the undershot current having a direction the same as when the state of the memory cell MC transitions to the reset state RESET. Accordingly, the voltage level of the threshold voltage Vth of the memory cell MC in the reset state RESET, which was lowered after the start of the read operation, may rise again (e.g., change in the direction of an arrow U in FIG. 5).

An operation of each of the components of the semiconductor device according to an embodiment of the present disclosure may be more specifically described as follows with reference to FIG. 1.

First, a set write operation for changing the state of the memory cell MC into the set state may be described as follows.

The memory cell MC may be selected. For example, at least one memory cell MC from among a plurality of memory cells may be selected. In this case, the memory cell MC may be selected by the first and second selection switches 610 and 620. The memory cell MC that has been selected may be a memory cell that is connected to the first and second selection switches 610 and 620 that have been turned on. That is, the memory cell MC that has been selected may be a memory cell that is electrically connected between the first selection switch 610 that has been turned on by the bit line selection signal BL_s and the second selection switch 620 that has been turned on by the word line selection signal WL_s.

The write enable signal Write Enable may be a signal that is enabled after the start of a write operation, such as a reset write operation and a set write operation. Accordingly, the first connection switch 630 may be turned on.

As a result, the first bias voltage generation circuit 100 may be electrically connected to the memory cell MC through the first selection switch 610 that has been turned on.

After the start of a set write operation, the first bias voltage generation circuit 100 may provide the first bias voltage V_1 to the memory cell MC through the first selection switch 610 that has been turned on. At this time, the third bias voltage V_3 has a voltage value that less than the voltage value of the first bias voltage V_1.

Accordingly, after the start of the set write operation, a current path having a first direction in which a current flows from the first bias voltage generation circuit 100 to the first selection switch 610, the memory cell MC, the second selection switch 620, and the first connection switch 630 may be formed. The state of the memory cell MC may transition to the set state SET as the current path having the first direction is formed.

Next, a reset write operation for changing the state of the memory cell MC into the reset state may be described as follows.

The memory cell MC may be selected. For example, at least one memory cell MC from among a plurality of memory cells may be selected. In this case, the memory cell MC may be selected by the first and second selection switches 610 and 620. The memory cell MC that has been selected may be a memory cell that is connected to the first and second selection switches 610 and 620 that have been turned on. That is, the memory cell MC that has been selected may be a memory cell that is electrically connected between the first selection switch 610 that has been turned on by the bit line selection signal BL_s and the second selection switch 620 that has been turned on by the word line selection signal WL_s.

The write enable signal Write Enable may be a signal that is enabled after the start of a write operation, such as a reset write operation and a set write operation. Accordingly, the first connection switch 630 may be turned on.

As a result, the third bias voltage generation circuit 300 may be electrically connected to the memory cell MC by the first connection switch 630 that has been turned on and the second selection switch 620 that has been turned on.

After the start of the reset write operation, the third bias voltage generation circuit 300 may transmit the third bias voltage V_3 to the memory cell MC through the first connection switch 630 and the second selection switch 620 that have been turned on. At this time, the first bias voltage V_1 has a voltage value that less than the voltage value of the third bias voltage V_3.

Accordingly, after the start of the reset write operation, a current path having a second direction in which a current flows from the third bias voltage generation circuit 300 to the first connection switch 630, the second selection switch 620, the memory cell MC, and the first selection switch 610 may be formed.

As described above, the semiconductor device according to an embodiment of the present disclosure may be configured to form a current path having a different direction in the memory cell MC in order to change the state of the memory cell MC into the set state or the reset state.

Finally, a read operation of determining whether the state of the memory cell MC is the reset state or the set state may be described as follows.

The memory cell MC may be selected. For example, at least one memory cell MC from among a plurality of memory cells may be selected. In this case, the memory cell MC may be selected by the first and second selection switches 610 and 620. The memory cell MC that has been selected may be a memory cell that is connected to the first and second selection switches 610 and 620 that have been turned on. That is, the memory cell MC that has been selected may be a memory cell that is electrically connected between the first selection switch 610 that has been turned on by the bit line selection signal BL_s and the second selection switch 620 that has been turned on by the word line selection signal WL_s.

The second bias voltage generation circuit 200 may be electrically connected to the memory cell MC by the first selection switch 610 that has been turned on. The second bias voltage generation circuit 200 may provide the second bias voltage V_2 to the memory cell MC through the first selection switch 610 after the start of a read operation.

The read enable signal Read Enable may be a signal that is enabled after the start of a read operation. Accordingly, the second connection switch 640 may be turned on.

Accordingly, after the start of the read operation, a current path in which a current flows from the second bias voltage generation circuit 200 to the first selection switch 610, the memory cell MC, the second selection switch 620, the second connection switch 640, the read disturbance reduction circuit 500, and the sense amplifier 400 may be formed. In this case, the current path that is formed after the start of the read operation may be a current path having the same direction as the direction after the start of a set write operation because the current path is a current path in which the current flows into the first selection switch 610 and the memory cell MC and the second selection switch 620 on the basis of the memory cell MC. That is, the direction of the current path that is formed after the start of the read operation may be the first direction that is the same as the direction after the start of the set write operation.

As described above, in the read operation, all of the first selection switch 610, the second selection switch 620, and the second connection switch 640 may be turned on, and thus a current that flows through the memory cell MC may be transmitted to the sense amplifier 400 via the read disturbance reduction circuit 500 due to the second bias voltage V_2 that is provided by the second bias voltage generation circuit 200.

The sense amplifier 400 may determine the state of the memory cell MC by sensing the amount of current in the current path formed due to the second bias voltage V_2 that has been provided by the second bias voltage generation circuit 200 for a set time or the voltage level of a voltage that is formed due to the current, and may output the output signal D_out, that is, the results of the determination.

After the second bias voltage V_2 is provided to the memory cell MC for the set time, that is, after the sense amplifier 400 determines the state of the memory cell MC, the second bias voltage generation circuit 200 may stop the providing of the second bias voltage V_2. When the second bias voltage V_2 that is provided by the second bias voltage generation circuit 200 is discontinued, undershoot may be performed on a current path that is connected to the memory cell MC, the read disturbance reduction circuit 500, and the sense amplifier 400. In this case, the undershoot may form a current having a direction opposite the first direction, that is, a current that flows through the memory cell MC in the second direction. Such a current may be called an undershot current.

After the start of the read operation, the direction of the current that flows through the memory cell MC may be the same as the direction of a current for changing the state of the memory cell MC into the set state. Accordingly, as the read operation is repeated, the threshold voltage of the memory cell MC in the reset state may be at risk of being changed into the set state, that is, a state in which the voltage level of the threshold voltage is low.

As described above, the semiconductor device according to an embodiment of the present disclosure may include the read disturbance reduction circuit 500 in order to prevent a phenomenon in which the voltage level of the threshold voltage of the memory cell MC in the reset state is lowered after the start of a read operation. When a determination of the state of the memory cell MC after the start of a read operation is completed, the read disturbance reduction circuit 500 may form a current that flows through the memory cell MC in a direction opposite a direction in which the current flows through the memory cell MC after the start of the read operation. Accordingly, the voltage level of the threshold voltage of the memory cell MC, which has been lowered due to the read operation, may be restored.

FIG. 6 is a diagram for describing a construction of a semiconductor device according to another embodiment of the present disclosure.

Referring to FIG. 6, the semiconductor device according to another embodiment of the present disclosure may include a first bias voltage generation circuit 100-1, a second bias voltage generation circuit 200-1, a third bias voltage generation circuit 300-1, a sense amplifier 400-1, a read disturbance reduction circuit 500-1, a first selection switch 610-1, a second selection switch 620-1, a first connection switch 630-1, and a second connection switch 640-1.

The first bias voltage generation circuit 100-1 may provide a first bias voltage V_1 to a memory cell MC for a set time after the start of a write operation. For example, the first bias voltage generation circuit 100-1 may provide the first bias voltage V_1 to the memory cell MC through the first selection switch 610-1 that is turned on for a set time after the start of a write operation. In this case, the first bias voltage V_1 may be a voltage for changing the state of the memory cell into a first state (e.g., a set state).

The second bias voltage generation circuit 200-1 may provide a second bias voltage V_2 to the memory cell MC for a set time after the start of a read operation. For example, the second bias voltage generation circuit 200-1 may provide the second bias voltage V_2 to the memory cell MC through the first selection switch 610-1 that is turned on for a set time after the start of a read operation. In this case, the second bias voltage V_2 may be a voltage having a voltage level at which the state of the memory cell may be determined.

The third bias voltage generation circuit 300-1 may provide a third bias voltage V_3 to the memory cell MC for a set time after the start of a write operation. For example, the third bias voltage generation circuit 300-1 may provide the third bias voltage V_3 to the memory cell MC through the second selection switch 620-1 and the first connection switch 630-1 that are turned on for a set time after the start of a write operation. In this case, the third bias voltage V_3 may be a voltage for changing the state of the memory cell into a second state (e.g., a reset state).

The sense amplifier 400-1 may determine the state of the memory cell MC by sensing a voltage that is formed due to the amount of a current that flows through the memory cell MC after the start of a read operation. For example, the sense amplifier 400-1 may determine whether the state of the memory cell MC is the set state or the reset state by comparing a reference voltage Vref to a voltage that is formed due to a current that flows through the memory cell MC that has been selected by the first and second selection switches 610-1 and 620-1. In this case, when the state of the memory cell MC is the set state, the sense amplifier 400-1 may output an output signal D_out having a low level. Furthermore, when the state of the memory cell MC is the reset state, the sense amplifier