1, M2 simultaneously for a brief moment when the binary signal d_nto a DAC cell 20 changes. It is, therefore, the task of the switch drivers 10 to ensure that the switch control signals, i.e. the binary signals d_n, overlap in time during their on-state. This overlap is, as mentioned, commonly referred to as high/low cross point (depending on whether PMOS or NMOS switches are used), make-before-break operation, etc. The concept of the two switches being on at the same time may, in this disclosure, be referred to as on-state overlap time.

Returning to the block diagram of FIG. 1a, there are numerous published circuits implementing the functionality for driving the switches of a current-steering DAC cell 20. Common to the prior art is that their operation and components can all be mapped to the block diagram shown in FIG. 1a. The operation of the driver 10 starts with a latch element 12 which propagates the bit data D in synchrony with a global reference clock CLK. An output signal of the latch 12 contains the bit data D mixed with the reference clock CLK into one signal. This means that the single output of the latch 12 carries both timing and state information.

In an on-state overlap time generation block 14, the mixed clock and data signal is split in two differential signals (with complementary data). Importantly, however, the edges of these differential signals are intentionally skewed with respect to each other. An edge that will turn on one of the switches M1, M2 in the DAC cell 20 is propagated with a sufficiently short delay. An edge that will turn the other one of the switches M1, M2 off is intentionally delayed more than the edge turning on said one of the switches M1, M2. This ensures that the DAC cell switches M1, M2 are briefly turned on at the same time and that there is a reduced risk of abrupt changes in the impedance of node C as would have been the case if both switches M1, M2 were off at the same time. By delaying a turning off of a switch M1, M2, there will always be a path for the reference current I_R. The resulting signals from the on-state overlap time generation block 14 are provided to a buffer 16. The output of the buffer 16 are the binary signals d_n, d_n used to drive the switches M1 and M2 of FIG. 1b.

In the solutions of FIGS. 1a and 1b, all blocks comprising switch drivers 10, apart from the clock generation and distribution, are local to each DAC cell 20. In other words, after the global reference clock CLK, no devices or signals are shared between paths for the binary signals d_n, d_n+1, d_n+2, . . . , d_n+m. In addition to this, the data is latched very early in the timing chain—already by the latch element 12.

As is clear to a person skilled in the art, after being given the time to fully digest the teachings of this disclosure, in a particular transistor implementation of a switch driver, not all blocks in FIG. 1a will be easy, or even possible, to cleanly separate and to assign devices to the function of one block only. For example, it is common that the data latching 12 and differential signal generation with on-state overlap 14 is done simultaneously, or that no additional buffer 16 is used. Regardless of this, the circuits remain local to the DAC cells 20, and the order of operations remains the same, i.e. clock and data are latched early in the chain, before generation of on-state overlap and before any differential signal generation.

In summary, all signals downstream of the latch 12 contain timing information on both their rising and falling edges. That is, there are no separate paths carrying the timing information for the turn on and turn off events of a given switch M1, M2. Instead, the events are propagated through the same nodes by the same signals. Notice that this is not the same between the two switches M1, M2. A signal path for one switch M1 will have to be different from a signal path of the other switch M2, at least the path from the differential signal generation with on-state overlap 14 and onwards to the switches M1, M2. It should be noted that, the differential signal generation with on-state overlap 14 is a quite complex circuit with many devices, nodes and comparably long signal paths.

Just like in digital circuits, one reason for the occurrence of glitches in analog circuits may be due to a signal path fanning out to separate paths and later in the signal chain, fans back in to one signal again. The separate paths of the signal are generally subjected to different circuitry, routing lengths etc. causing a delay that is inconsistent for the signal paths. This is what happens with the reference clock CLK in a DAC—it is mixed with the data to produce the driving signals for each DAC cell (fan-out), propagates through driver buffers and the DAC cells, finally the outputs of the DAC cells 20 are summed to generate the output signal (fan-in). This path, from the common clock to the DAC output is referred here as timing path.

In order to guarantee glitch-free operation, all blocks between the clock fan-out and an output summation node connecting the different DAC cells 20 preferably present identical propagation delays, regardless of bit weight, data history, analog output state, and random fluctuations of the, otherwise identical, device properties comprising each individual path. In practice, however, several factors contribute to different propagation delays for each individual branch. This timing mismatch is referred to as timing skew. A characteristic of the timing skew is that it is static for a given signal, operating conditions, and circuit sample. That is, it depends on process, voltage, temperature, corner, signal history, and device matching. The latter, matching, means that the delay distribution between the timing paths in a DAC are statistical in nature. However, since it does not depend directly on time, it is different from timing jitter which is understood as being random in time. Timing skew generates distortion at the output while timing jitter generates noise.

Glitches at the DAC output represent signals which are not originally present in the input data sequence. However, they are strongly dependent on the specific transitions of the input data. Therefore, the linearity performance of the DAC heavily depends on ensuring very low power levels of the glitch signals and, by extension, on accurate timing path matching, i.e. low timing skew.

One challenge of the solution presented in FIG. 1a is related to achieving low timing skew between the DAC cells 20 while maintaining low-power operation and small chip area. The challenge stems from the functional requirement to simultaneously latch the data and drive the DAC cell switches M1, M2 with overlapping signals. These are two related in time, but functionally separate timing features.

As mentioned, the complex circuitry of the on-state overlap generation 14 results in long signal paths for the timing critical events. Since only one edge of a switch control signal d_n, d_n (the one turning it off) has to be delayed, it is gated by a delayed version of the other (“turn on”) edge. This gating introduces at least one extra stage as well as at least one extra node in the signal chain and requires extra devices to be connected to the other signal nodes. This is the functionality of the on-state overlap time block 14 in FIG. 1a. As was already established, the timing skew performance deteriorates as more devices and nodes are added in the timing signal path. Therefore, the long timing path created by the gating of the “turn off” edge is detrimental to the timing skew performance, and hence to, linearity and overall power consumption as well.

The on-state overlap time is added after mixing clock and data (after latching 12). Therefore, on-state overlap generation must be done locally to the DAC cell 20, hence, it is subject to timing skew. This may be viewed from another point of view regarding the order of operations in FIG. 1a. The generation of on-state overlap time is an inherently complex operation as it has to involve the clock together with a current and a next data state. In the prior art, on-state overlap generation is placed in the critical timing path, that is after data is latched, this limits the ultimate performance of the driver.

Additionally, in differential implementations, two signal paths are used to propagate four events, requiring the power and area to grow exponentially with the target performance. This is related to a maximum speed of the logic transitions at internal nodes of the driver 10 and the DAC cell 20. As was previously mentioned, in order to achieve low timing skew, it is important to maintain fast signal transitions between logic levels. For a given load at the output of a logic gate, the only way to speed up a transition in a given direction is to increase the driving strength (size up) the corresponding pull-up/down network. However, this has the added effect that the total output load is increased and the transition speed in the opposite direction is reduced, requiring even further upsizing. This leads to a recursive cycle of transistor up scaling. From the description of FIGS. 1a and 1b, since both logic transitions for substantially all nodes after the latch 12 carry timing information, the required power and area grows exponentially with the targeted performance.

Further to this, the input of the DAC cell 20, i.e. the latch 12 takes two control signals for its two switches M1, M2, and both the rising and the falling edge of these control signals are timing critical. The solutions presented in FIGS. 1a and 1b, employ two paths to propagate the information for the control signals d_n, d_n of the two switches M1, M2. In other words, they propagate the “turn on” as well as the “turn off” events on the same path—four events for two switches M1, M2 propagated on two paths. Therefore, the area and power required for a given performance will grow exponentially.

The present disclosure presents a new architecture for the switch driver of an IDAC unit cell, i.e. a current steering DAC cell, and timing path based on a new latching element that is synchronizing (to the clock) and propagating, to its output, only one logic transition—rising or falling. This latch enables the rearranging of the operations in the local data-path cell 10 of FIG. 1a and present a different architecture. This new latch is configured to synchronize only one of the input data logic transitions to the edges of the clock. Further to this, the latch allows the use of four separate timing critical paths—one per critical timing event, where each path may be optimized for one transition direction only. The change in architecture of the switch driver makes it possible to move the on-state overlap time generation before the data latching operation is performed, thus reducing the length and complexity of the timing critical paths. In addition to this, the on-state overlap time is generated globally for all DAC cells 20. This eliminates its timing skew contribution when compared to local on-state overlap time generation. Furthermore, it allows the on-state-overlap time to be trimmed globally for the entire DAC.

It should be mentioned that although the present disclosure focuses on on-state overlap, there may very well be embodiment wherein an off-state overlap is desired and the solutions presented herein are just as applicable for applications in need of a controlled off-state overlap.

The functional description of the latch will be explained in the following starting with the schematic block diagram of FIG. 2. FIG. 2 illustrates one embodiment of a single ended driver circuit 100. The driver circuit 100 is suitable for providing control signal d_n, d_n to the DAC cell 20. The driver circuit 100 comprises one positive single-edge latch 200 and one negative single-edge latch 300. The positive single-edge latch 200 is configured to provide a positive edge latched data signal S⁺ by latching a positive edge of a data signal D synchronized by a first clock signal CLK₁. That is, the positive edge latched data signal S⁺ is only actively driven when the data signal D is high and the first clock signal CLK₁is high, i.e. only the rising edge of the data signal D is synchronized and propagated to the positive edge latched data signal S⁺. Similarly, the negative single-edge latch 300 is configured to provide a negative edge latched data signal S⁻ by latching a negative edge of the data signal D synchronized by a second clock signal CLK₂. That is, the negative edge latched data signal S⁻ is only actively driven when the data signal D is low and the second clock signal CLK₂is low. The outputs of the positive single-edge latch 200 and the negative single-edge latch 300, i.e. the positive edge latched data signal S⁺ and the negative edge latched data signal S⁻, are combined to provide a drive signal S. The drive signal S may be fed through a buffer circuitry to provide the control signal d_n, d_nto the DAC cell 20 or fed directly to DAC cell 20 depending on e.g. design constraints. The drive signal S will have a positive edge synchronized by the first clock signal CLK₁and a negative edge synchronized by the second clock signal CLK₂.

The single ended driver circuit 100 enables the control of latching of a positive edge of the data signal D independently of the latching of the negative edge of the data signal D. The on-state overlap, or off-state overlap for that matter, is controlled by a phase difference, or a delay, between the first clock signal CLK₁and the second clock signal CLK₂. One of the clock signals CLK₁, CLK₂may be delayed with regards to the other clock signal CLK₁, CLK₂by a delay period T_D, see FIG. 5. This delay period T_Dmay, in some embodiments, be controlled through one or more software controllable registers. The control, or tenability, of the delay period T_Dallows for a more aggressive and finely tuned design. That is to say, the delay period T_Dmay be easily tuned and optimized, per unit, batch, series, product and/or platform in order to allow efficient and fast DAC operation.

As the delay period T_Dmay be generated globally and shared between some or all DAC cells 20, it is possible to feedback an output performance of a DAC 600 (see FIGS. 10a-b) and tune the delay period T_D, and thereby the on-state overlap time to optimize DAC performance.

In the following, it is assumed that the DAC cell 20 and any other circuitry is implemented such that switches turn on when the voltage level at their control port, i.e. their gate, is high. In other words, the embodiments presented are given with transistors of NMOS type. Anyone skilled in the art appreciates that all circuits presented herein may be transformed to their dual, and all reasoning will be the same for the case when circuitries are provided with switches of PMOS type.

With reference to FIG. 3, the inner workings of the positive single-edge latch 200 according to one embodiment will be given. The positive single-edge latch 200 is, as previously stated, configured to provide the positive edge latched data signal S⁺ of the data signal D. The positive single-edge latch 200 comprises a high side drive transistor 240, a first high side transistor switch 210, a first low side transistor switch 220 and a second low side transistor switch 230. The first high side transistor 210, the first low side transistor switch 220 and the second low side transistor switch 230 are connected in series between negative feed V⁻ and a positive feed V⁺. The series connection is such that the low side transistor switches 220, 230 are arranged downstream from the first high side transistor switch 210. The first high side transistor switch 210 and the second low side transistor switch 230 are configured to be controlled by the data signal D and the first low side transistor switch 220 is configured to be controlled by the first clock signal CLK₁. The high side drive transistor 240 is controlled by an output signal D⁺ provided between the first high side transistor switch 210 and the series connection of the low side transistor switches 220, 230. The high side drive transistor 240 is preferably configured to provide the positive edge latched data signal S⁺ at an open drain of the high side drive transistor 240.

In the positive single-edge latch 200 of FIG. 3, when the data signal D is low, the output signal D⁺ between the first high side transistor switch 210 and the series connection of the low side transistor switches 220, 230 will always be high regardless of the state of the first clock signal CLK₁. In other words, as soon as the data signal D goes low, the output signal D⁺ will go high and stay high at least for the duration of the data signal D being low. When the data signal D is high, the output signal D⁺ will depend on the state of the first clock signal CLK₁. If the data signal D goes high at a point in time when first clock signal CLK₁is also high, the output signal D⁺ will be driven low by the series connection of the low side transistor switches 220, 230. However, if the first clock signal CLK₁is low when the data signal D goes high, the output signal D⁺ will remain at a high state subject to e.g. gate source leakage currents of the high side drive transistor 240. However, when the first clock signal CLK₁changes to a high state, the output signal D⁺ will be driven low and the gate of the high side drive transistor 240 will be discharged. As the positive edge latched data signal S⁺ is provided at an open drain of the high side drive transistor 240, it will be the inverse of the output signal D⁺ and, the positive single-edge latch 200 of FIG. 3 will, in this embodiment, only be able to drive the positive edge latched data signal S⁺ high and this will be in response to the data signal D and the first clock signal CLK₁being high at the same time.

In FIG. 4, a negative single-edge latch 300 according to one embodiment is illustrated. The working of the negative single-edge latch 300 are similar to those of the positive single-edge latch 200 of FIG. 3, but the negative single-edge latch 300 is configured to provide the negative edge latched data signal S⁻ of the data signal D. The negative single-edge latch 300 comprises a low side drive transistor 340, a first high side transistor switch 310, a second high side transistor switch 320 and a first low side transistor switch 330. The first high side transistor 310, the second high side transistor switch 320 and the first low side transistor switch 330 are connected in series between negative feed V⁻ and a positive feed V⁺. The series connection is such that the high side transistor switches 310, 320 are arranged upstream from the first low side transistor switch 330. The first high side transistor switch 310 and the first low side transistor switch 330 are configured to be controlled by the data signal D and the second high side transistor switch 320 is configured to be controlled by the second clock signal CLK₂. The low side drive transistor 340 is controlled by an output signal D⁻ provided between the series connection of the high side transistor switches 310, 320 and the first low side transistor switch 330. The low side drive transistor 340 is preferably configured to provide the positive edge latched data signal S⁺ at an open drain of the low side drive transistor 340.

In the negative single-edge latch 300 of FIG. 4, when the data signal D is high, the output signal D⁻ between the first low side transistor switch 330 and the series connection of the high side transistor switches 310, 320 will always be low regardless of the state of the second clock signal CLK₂. In other words, as soon as the data signal D goes high, the output signal D⁻ will go low and stay low at least for the duration of the data signal D being high. When the data signal D is low, the output signal D⁻ will depend on the state of the second clock signal CLK₂. If the data signal D goes low at a point in time when second clock signal CLK₂is also low, the output signal D⁻ will be driven high by the series connection of the high side transistor switches 310, 320. However, if the second clock signal CLK₂is high when the data signal D goes low, the output signal D⁻ will remain at a low state. However, when the second clock signal CLK₂changes to a low state, the output signal D⁻ will be driven high and the gate of the low side drive transistor 340 will be charged. As the negative edge latched data signal S⁻ is provided at an open drain of the low side drive transistor 340, it will be the inverse of the output signal D⁻ and the negative single-edge latch 300 of FIG. 4 will only be able to drive the negative edge latched data signal S⁻ low and this will be in response to the data signal D and the second clock signal CLK₂being low at the same time.

The connection of the transistor switches 210, 220, 230 of the positive single-edge latch 200 of FIG. 3 is illustrated with the first low side transistor switch 220 sandwiched between the second low side transistor switch 230 and the first high side transistor switch 210. Similarly, the connection of the transistor switches 310, 320, 330 of the negative single-edge latch 300 of FIG. 4 is illustrated with the second high side transistor switch 320 sandwiched between the first low side transistor switch 330 and the first high side transistor switch 310. This means that the output signals D⁻, D⁺ are connected to the transistor switch 220, 320 being controlled by the clock signal CLK₁, CLK₂. Compared to an opposite arrangement (not shown), wherein the first low side transistor switch 220 and the second low side transistor switch or the first high side transistor switch 310 and the second high side transistor switch 320 change positions, a coupling from the data signal D to the positive respective negative edge latched data signal S⁺, S⁻ is reduced. But it should be emphasized that embodiments of the present disclosure are applicable regardless of the order of the first low side transistor switch 220 and the second low side transistor switch 230 or the first high side transistor switch 310 and the second high side transistor switch 320.

From the description given of the positive single-edge latch 200 and the negative single-edge latch 300 it is clear that the positive single-edge latch 200 is configured to provide the positive edge latched data signal S⁻ synchronized to the first clock CLK₁, and the negative single-edge latch 300 is configured to provide the negative edge latched data signal S⁻ synchronized with the second clock CLK₂. As was illustrated in FIG. 2, the positive edge latched data signal S⁺ is combined with the negative edge latched data signal S⁻. Because both latched data signals S⁺, S⁻ are provided at an open drain, the signals S⁺, S⁻ may be connected directly to one another in order to provide the drive signal S. As the positive single-edge latch 200 is latched when the first clock signal CLK₁goes high and the negative single-edge latch 300 is latched when the second clock signal CLK₂goes low, the second clock signal CLK₂is preferably an inverse of the first clock signal CLK₁with the addition of the delay period T_D. The frequencies of the first clock signal CLK₁and the second clock signal CLK₂are preferably substantially equal.

FIG. 5 illustrates a timing diagram of the signals of the single ended driver circuit 100 as depicted in FIG. 2. The timing diagram illustrates the data signal S, the first clock signal CLK1, the second clock signal CLK2, the drive signal S and the output signals D⁺, D⁻ controlling the drive transistors 240, 340 of the single-edge latches 200, 300. These signals are all presented on a common time-based x-axis. In FIG. 5, the second clock signal CLK₂is inverted with regards to the first clock signal CLK₁and delayed by the delay period T_D. It is preferable to keep the data signal D stable when the first clock signal CLK₁is high in order to synchronize the drive signal S to the first clock signal CLK₁. In the timing scenario of FIG. 5b, the drive signal S rising edge is synchronized to the first clock signal CLK₁, and its falling edge is synchronized to the second clock signal CLK₂

At the start of the timing diagram, the data signal D is low and the output signal D⁺ of the positive single-edge latch 200 is actively driven high. In this state, the output signal D⁺ of the positive single-edge latch 200 will remain high regardless of the state of the first clock signal CLK₁. Consequently, the positive edge latched data signal S⁺ will be open, that is high impedance. The positive edge latched data signal S⁺ will stay in its high impedance state at least as long as the data signal D is low. However, the second clock signal CLK₂is high which implies that the output signal D⁻ of the negative single-edge latch 300 is floating at a high state (due to a historic previous state not shown where the second clock signal CLK₂was low and the gate of the low side drive transistor 340 was charged). This means that the output signal D⁻ of the negative single-edge latch 300 is actively driven high and the drive signal S is driven to a low state by the low side drive transistor 340 of the negative single-edge latch 300.

At a first point in time A, the drive signal S is driven low in response to the output signal D⁻ of the negative single-edge latch 300 going high. Which happens at a same time, ignoring delay between switches, as the second clock signal CLK₂going low when the data signal D is low. At a second point in time B, the data signal D goes high, but this transmission is not reflected in the drive signal S until the first clock signal CLK₁goes high causing the output signal D⁺ of the positive single-edge latch 200 to go low, see a third point in time C. At a fourth point in time A, the data signal D goes low which causes the output signal D⁺ of the positive single-edge latch 200 to go high asynchronously with respect to any of the clock signals CLK₁, CLK₂. But the change in data signal D at the fourth point in time A is not propagated to the drive signal S until the output signal D⁻ of the negative single-edge latch 300 goes high at fifth point in time E. The output signal D⁻ of the negative single-edge latch 300 goes high responsive to the second clock signal CLK₂going high when the data signal D is low. That is, at time instant E the output signal D⁻, and the drive signal S are synchronized to the second clock signal CLK₂.

As seen in the embodiment of FIG. 5 the positive edge of the data signal D is transitioned to the drive signal S synchronized to the first clock signal CLK₁, and the negative edge of the data signal D is transitioned to the drive signal S synchronized to the second clock signal CLK₂. As understood from the description given, the drive signal S may be described as a PWM signal having a duty cycle that is controllable by the delay period T_D. If the delay period T_Dis zero, the duty cycle would be 50% and if the delay period T_Dis half a period time of the clock signals CLK₁, CLK₂, the duty cycle would be 75% and so on.

As the delay period T_D, and thereby the amount of on-state overlap is not limited by requirements for timing matching, complexity of the local DAC-circuits etc., as is the case of the prior art, it may be selected freely. This allows for the delay period T_Dto be chosen to match e.g. requirements for keeping an operation point of a DAC cell stable.

The configuration with the drive transistors 240, 340 of the single-edge latches 200, 300 provides an inherently strong output stage that effectively eliminates a need for additional drive circuitry. Prior art solutions generally require additional circuitry, such as inverter-based buffers, to provide this in order to achieve the low timing skew that is required for high performance DACs 600. This is inherent through the drive transistors 240, 340 of the single-edge latches 200, 300 which further reduces complexity and cost compared to the prior art.

In FIG. 6, a differential driver circuit 500 is illustrated. The differential driver circuit 500 comprises a first single ended driver circuit 100 and a second single ended driver circuit 100, each according to any suitable embodiment of this disclosure. A positive drive signal S^Pis provided by the first single ended driver circuit 100 by connecting a positive edge latched data signal S^+Pof a first positive single-edge latch of the first single ended driver circuit 100 to a negative edge latched data signal S^−Pof a first negative single-edge latch 300 of the first single ended driver circuit 100. Similarly, a negative drive signal S^Nis provided by connecting a positive edge latched data signal S^+Nof a second positive single-edge latch 200 of the second single ended driver circuit 100 to a negative edge latched data signal S^−Nof a second negative single-edge latch 300 of the second single ended driver circuit 100. The data signal D provided to the second positive single-edge latch 200 and the second negative single-edge latch 300 is an inverse of the data signal D provided to the second positive single-edge latch 200 and the second negative single-edge latch 300. The drive signals S^N, S^Pare for operatively connection to a DAC cell 20.

From FIG. 6 it has been shown that the single ended driver circuit 100 of the present disclosure is usable also for forming a differential driver circuit 500. Differential circuitry are in many cases the preferred circuitry for high speed DACs 600. The differential DAC has added benefits compared to the single ended DAC as it is less sensitive to electromagnetic interference, since the differential drive signals S^N, S^Pare transmitted on balanced lines. The risk of crosstalk is reduced and perhaps even more important, it may be used for high speed transmission lines with good quality much due to the reduced noise and radiation. Consequently, common mode rejection as well as improved power supply rejection can be achieved by the differential DAC.

Returning to the general idea of the present disclosure. With the global generation of the on-state overlap and the possibility to share it with one, some or all DAC cells 20, the number of nodes in the timing critical path is greatly reduced which in turn reduces the current consumption of the circuitry as fewer gates needs to be switched. In the prior art, one clock signal is distributed to an array of switch drivers of a DAC and locally delayed to create the on-state overlap. In the present solution, two clocks CLK₁, CLK₂are distributed to the array of switch drivers of the DAC 600. One clock controls turn on events and the other clock controls turn off events, such that, in differential operation, when these clocks are mixed with the data signal D, four separate signals are provided (four timing paths), each carrying one timing event. In addition, the delay period T_Dmay be generated globally for all timing paths and the resulting delay period T_Dmay be distributed similarly to a main clock. Therefore, its timing skew contribution can be significantly reduced. Furthermore, since it is outside of the sensitive timing path, the circuit can be made substantially more advanced and still allows for lower random timing jitter.

The solution of the present disclosure provides each timing event on a separate path. This gives a higher degree of freedom in designing each timing path and consequently a more fine-tuned design.

The present solutions offers a break-before-make operation which allows for higher switching speeds, lower timing skew and reduced power consumption. In the context of CMOS circuits, break-before-make comprises of setting a node to high impedance state, just before changing its logic level. Consider the positive edge latched data signal S^+Pin FIG. 6 and the timing diagram of FIG. 5. When the data signal D is a logic high, see second and third time points B, C in FIG. 5b, the low side drive transistor 340 of the first negative single-edge latch 300 of the first single ended driver circuit 100 is off, regardless of the second clock signal CLK₂. I.e. the negative edge latched data signal S^−Pis high impedance. The high side drive transistor 240 of the first positive single-edge latch 200 of the first single ended driver circuit 100 is turned on synchronously to the first clock signal CLK₁. This drives the positive edge latched data signal S^+Pand the positive drive signal S^Phigh. When the data signal D goes low, see the fourth time point Δ in FIG. 5b, the high side drive transistor 240 of the first positive single-edge latch 200 of the first single ended driver circuit 100 is turned off, leaving the positive edge latched data signal S^+Pin a high impedance state. The negative edge latched data signal S^−Pis still at a high impedance state which means that the positive drive signal S^Pis floating until the second clock signal CLK₂goes low. Importantly, since the positive drive signal S^Pis floating, no short circuit current flows through the drive transistors 240, 340 and all of the drive current, i.e. current at the output signals D⁺, D⁻, is available to change the output state, increasing speed and reducing power consumption.

The break-before-make operation is also utilized in earlier stages of the single ended driver circuit 100. When the first clock signal CLK₁is low, the output signals D⁺, D⁻ are either floating or not going to transition. Similarly, when the first clock signal CLK₁goes high, the data signal D is preferably stable and the output signals D⁺, D⁻ are either driven at their current state or are left floating, they are not going into transition.

The break-before-make operation allows the transitions to happen much faster than they could in a conventional CMOS gate. There are a few reasons for this. A first reason is that no shoot-through current flows between the supplies which result in the full driving strength of the devices being utilized to charge/discharge the driven nodes. In addition to this, the number of transistor gates connected to input nodes of break-before-make gates is typically half of that of an equivalent conventional gate, i.e. half of the load is present to the stage driving them. Additionally, since only one transition at a given input of a break-before-make gate can trigger a transition at the output, the preceding (driving) gate can be optimized to generate fast transitions only in that direction, thus avoiding effects of self-loading.