According to at least one embodiment of the AD conversion method, an output is provided which is given by the difference between an output determined from the method carried out for the further analog signal and an output determined from the method carried out for the analog signal. The outputs can each comprise a digital signal. This means, the method is carried out for the analog signal and as an output a digital signal is provided. Afterwards, the method is carried out for the further analog signal and as an output a digital signal is provided. The signal to be determined is then the difference between the two digital signals. This means, in this provided output the reset level is subtracted from the actual analog signal. In this way, the delay cancels out in the subtraction as the delay is the same for the analog signal and the further analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description of figures may further illustrate and explain exemplary embodiments. Components that are functionally identical or have an identical effect are denoted by identical references. Identical or effectively identical components might be described only with respect to the figures where they occur first. Their description is not necessarily repeated in successive figures.

FIG. 1 shows an exemplary embodiment of the ADC circuit.

With FIGS. 2, 3A and 3B show exemplary embodiments of an AD conversion method.

DETAILED DESCRIPTION

FIG. 1 shows an exemplary embodiment of an ADC circuit 20. The ADC circuit 20 comprises a comparator 21 with a first input 22 for receiving an analog signal AS and a second input 23 for receiving a ramp signal RS. The analog signal AS can be provided to the first input 22 via a capacitor 31 connected to the first input 22 or the analog signal AS can be provided to the first input 22 in another way. The capacitor 31 is optional. The ramp signal RS is provided to the second input 23 via a ramp generator 30 connected to the second input 23.

The comparator 21 comprises a first output 24 and a second output 25. The second output 25 is connected to the first output 24. The first output 24 is configured to provide a first output signal FO and the second output 25 is configured to provide a second output signal SO. The first output signal FO toggles once the ramp signal RS has reached the level of the analog signal AS at a stopping time ST. The second output signal SO toggles at a delayed stopping time DS which is delayed by a delay in comparison to the stopping time ST. The comparator 21 further comprises a delay element 32. The delay element 32 is configured to delay the second output signal SO so that the second output signal SO toggles at the delayed stopping time DS. The second output 25 is arranged at an output of the delay element 32 or is connected to an output of the delay element 32. The delay element 32 can comprise an inverter. It is also possible that the delay element 32 is a separate component and not comprised by the comparator 21.

The ADC circuit 20 further comprises a first counter 26 that is connected to the first output 24 and a second counter 27 that is connected to the second output 25. Furthermore, the second counter 27 is connected to the first output 24 and the second counter 27 is connected to the first counter 26. However, the connection between the second counter 27 and the first output 24 is optional.

The ADC circuit 20 further comprises a first clock 28 that is connected to the first counter 26 and a second clock 29 that is connected to the second counter 27. The first clock 28 is configured to provide a first clock signal FC to the first counter 26 and the second clock 29 is configured to provide a second clock signal SC to the second counter 27. The first counter 26 is configured to count with the frequency of the first clock signal FC and the second counter 27 is configured to count with the frequency of the second clock signal SC. The frequency of the first clock signal FC is lower than the frequency of the second clock signal SC. The frequency of the second clock signal SC is n times the frequency of the first clock signal FC, wherein n is a natural number.

The second counter 27 is configured to be activated once the first clock signal FC has changed its state after the stopping time ST. The first counter 26 is configured to be activated at the time when the ramp signal RS is provided to the second input 23 of the comparator 21. The delay amounts to one period of the first clock signal FC.

With FIG. 2 an exemplary embodiment of the AD conversion method is described. FIG. 2 shows a diagram where the time is plotted on the x-axis and different signals are plotted above each other on the y-axis. According to the AD conversion method at first a first point in time t1 an analog signal AS is provided to the first input 22 of the comparator 21. The analog signal AS is shown in the bottom line of the diagram. At the same time a ramp signal RS is provided to the second input 23 of the comparator 21. Furthermore, the ramp signal RS is set to a starting value.

At a second point in time t2 the ramp signal RS is provided to the second input 23 of the comparator 21. From the second point in time t2 on the ramp signal RS linearly decreases. Thus, at the second point in time t2 the comparison of the analog signal AS to the ramp signal RS by the comparator 21 is started. The second point in time t2 is referred to as a first starting time FS. At the first starting time FS the first counter 26 is activated. This means, at the first starting time FS the first counter 26 starts to count with the frequency of the first clock signal FC. At the first starting time FS the first counter 26 starts to provide a first counting signal CF which is shown in the top line in the diagram. In the example in FIG. 2 the first counting signal CF shows two clock cycles of the first clock signal FC.

At a third point in time t3 a first output signal FO toggles. This is the point in time when the ramp signal RS has reached the level of the analog signal AS. The third point in time t3 is referred to as the stopping time ST. The first output signal FO is provided by the first output 24 of the comparator 21. The first counter 26 is connected to the first output 24. The first counter 26 stops counting when the clock cycle that was started before the stopping time ST and ended after the stopping time ST ended. This means, the first counter 26 is deactivated with the end of the clock cycle of the first clock signal FC that was started before the stopping time ST. In the example in FIG. 2 the first counter 26 is deactivated shortly after the stopping time ST.

The second counter 27 is activated at a fourth point in time t4. The fourth point in time t4 is referred to as the second starting time SE. The second starting time SE is reached when the ramp signal RS has reached the level of the analog signal AS at the stopping time ST and the first clock signal FC has changed its state after the stopping time ST. This means, the second counter