However, it is to be understood that the first signal distribution circuit and/or the second signal distribution circuit may comprise any other suitable components that are configured to perform the functionalities described above.

DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 schematically shows an example of a test and/or measurement system according to an embodiment of the present disclosure in a first operational mode;

FIG. 2 schematically shows the test and/or measurement system of FIG. 1 in a second operational mode;

FIG. 3 shows an example of a signal distribution circuit of the test and/or measurement system according to an embodiment of the present disclosure;

FIG. 4 shows another example of a signal distribution circuit of the test and/or measurement system according to an embodiment of the present disclosure;

FIG. 5 shows yet another example of a signal distribution circuit of the test and/or measurement system according an embodiment of the present disclosure;

FIG. 6 shows a still another example of a signal distribution circuit of the test and/or measurement system according an embodiment of the present disclosure;

FIG. 7 shows a diagram illustrating a synchronization performed by the test and/or measurement system according to an embodiment of the present disclosure;

FIG. 8 shows another example of a test and/or measurement system according to an embodiment of the present disclosure; and

FIG. 9 shows yet another example of a test and/or measurement system according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

FIG. 1 schematically shows an example of a test and/or measurement system 10 in accordance with an embodiment of the present disclosure. As shown in FIG. 1, the system 10 comprises a first measurement circuit 12 and a second measurement circuit 14. In general, the test and/or measurement system 10 is configured to perform measurements on a device under test or on several devices under test by the measurement circuits 12, 14.

In an embodiment, the first measurement circuit 12 and the second measurement circuit 14 may be physically distinct circuits that are provided on physically distinct circuit boards and/or in physically distinct devices each having a housing. For example, the test and/or measurement system 10 may comprise a first test and/or measurement instrument having a housing, wherein the first test and/or measurement instrument comprises the first measurement circuit 12. In this example, the test and/or measurement system 10 may further comprise a second test and/or measurement instrument having a further housing, wherein the second test and/or measurement instrument comprises the second measurement circuit 14.

In the embodiment of FIG. 1, the first measurement circuit 12 comprises an LO circuit 16 that is configured to generate an LO signal. For example, the LO circuit 16 may be or comprise a voltage-controlled oscillator (VCO). In an embodiment, the LO circuit 16 is configured to generate the LO signal based on a clock signal that is equal to or derived from a first reference clock signal.

In the example embodiment shown in FIG. 1, the first measurement circuit 12 comprises a first reference clock signal generator circuit 18 that is configured to generate the first reference clock signal. For example, a frequency of the first reference clock signal may be between 10 MHz and 10 GHz. However, it is to be understood that any other suitable frequencies may be used depending on the application.

The LO circuit 16 is coupled to the first reference clock signal generator circuit 18 by a clock coupling circuit 20 that is configured to derive the clock signal for the LO circuit 16 based on the first reference clock signal, e.g. by frequency division or frequency multiplication. The clock coupling circuit 20 may comprise or be a phase-locked loop.

In the embodiment of FIG. 1, the first measurement circuit 12 further comprises a first signal distribution circuit 22, a first ADC 24, and a first LO port 26. In general, the first signal distribution circuit 22 is configured to forward the LO signal generated by the LO circuit 16 to the first LO port 26. Further, in an adjustment mode of the test and/or measurement system 10, the first signal distribution circuit is configured to forward the LO signal to the first ADC 24.

In the adjustment mode, the first ADC 24 is configured to digitize the LO signal received, thereby obtaining a first digitized LO signal. For example, the first ADC 24 may be configured to digitize the LO signal based on a sampling clock that is derived from the first reference clock signal by a clock coupling circuit 28. The clock coupling circuit 28 may comprise or be a phase-locked loop.

In an embodiment, the first measurement circuit 12 may further comprise a first signal adjustment circuit 30 that may be interconnected between the first signal distribution circuit 22 and the first ADC 24. In general, the first signal adjustment circuit 30 may be configured to amplify, filter, and/or attenuate a signal received from the first signal distribution circuit 22, and to forward the correspondingly processed signal to the first ADC 24. In the adjustment mode described above, the signal received and processed by the first signal adjustment circuit 30 is the LO signal.

In an embodiment, the first measurement circuit 12 further comprises a first frequency converting circuit 32, and a first RF port 34 that is connected to the first frequency converting circuit 32. In general, the first RF port 34 is configured to receive a first measurement signal and to forward the first measurement signal to the first frequency converting circuit 32.

In an embodiment, the first RF port 34 may be connected to a first RF antenna 36 that receives the first measurement signal from a device under test. Alternatively, the first RF port 34 may be connected to the device under test via a cable. In an embodiment, the first measurement signal may be an RF signal or a baseband signal.

If the first measurement signal received is an RF signal, the first frequency converting circuit 32 is configured to down-convert the first measurement signal in frequency, namely to an intermediate frequency. In this case, the down-converted first measurement signal is forwarded to the first signal distribution circuit 22.

In an embodiment, the first frequency converting circuit 32 may receive the LO signal via the first signal distribution circuit 22, and may mix the first measurement signal with the received LO signal, thereby down-converting the first measurement signal.

Of course, the first frequency converting circuit 32 may comprise at least one filter in order to remove unwanted signal components from the first measurement signal mixed with the LO signal.

If the first measurement signal received is a baseband signal, the first frequency converting circuit 32 may be bypassed. In this case, the first measurement signal may be forwarded to the first signal distribution circuit 22.

As is indicated by the dotted lines, the measurement path comprising the first frequency converting circuit 32 and the first RF port 34 may be inactive in the adjustment mode of the test and/or measurement system 10 illustrated in FIG. 1. Accordingly, in the adjustment mode, the first signal distribution circuit 22 may not forward the first measurement signal to the first ADC 24.

The second measurement circuit 14 and the first measurement circuit 12 may be identically constructed, but configured differently, as will be explained hereinafter.

In the embodiment shown in FIG. 1, the second measurement circuit 14 comprises a second signal distribution circuit 38, a second ADC 40, and a second LO port 42. The second LO port 42 is connected to the first LO port 26 so as to receive the LO signal from the first LO port 26. For example, the second LO port 42 may be connected to the first LO port 26 by a cable. In the adjustment mode, the second signal distribution circuit 38 is configured to forward the LO signal received by the second LO port 42 to the second ADC 40.

In an embodiment, a second signal adjustment circuit 44 may be provided between the second signal distribution circuit 38 and the second ADC 40, wherein the second signal adjustment circuit 44 may be configured to amplify, filter, and/or attenuate a signal received from the second signal distribution circuit 44, and to forward the correspondingly processed signal to the second ADC 40.

In the adjustment mode, the second ADC 40 is configured to digitize the LO signal received, thereby obtaining a second digitized LO signal. For example, the second ADC 40 may be configured to digitize the LO signal based on a sampling clock that is derived from a second reference clock signal by a clock coupling circuit 46. In an embodiment, the clock coupling circuit 46 may comprise or be a phase-locked loop.

In the example embodiment shown in FIG. 1, the second measurement circuit 14 comprises a second reference clock signal generator circuit 48 that is configured to generate the second reference clock signal. The second reference clock signal generator circuit 48 may be synchronized to the first reference clock signal generator circuit 18. For example, the first reference clock signal may be forwarded to the second measurement circuit 14 via a coupling and/or switching circuit 50 of the first measurement circuit 14, a first clock port 52 of the first measurement circuit 14, and a second clock port 54 of the second measurement circuit 14.

In an embodiment, the second measurement circuit 14 may comprise a clock coupling circuit 56 that is connected to the second clock port 54 so as to receive the first reference clock signal. The second reference clock signal generator circuit 48 may be synchronized to the first reference clock signal generator circuit 18 by the clock coupling circuit 56. In an embodiment, the clock coupling circuit 56 may comprise or be a phase-locked loop.

As is illustrated by the dashed lines in FIG. 1, the second measurement circuit 14 may comprise a local oscillator circuit 58, which however may be inactive as the second measurement circuit 14 receives the LO signal from the first measurement circuit 14.

In an embodiment, the second measurement circuit 14 further comprises a second frequency converting circuit 60, and a second RF port 62 that is connected to the second frequency converting circuit 60. In general, the second RF port 62 is configured to receive a second measurement signal and to forward the second measurement signal to the second frequency converting circuit 60.

In an embodiment, the second RF port 62 may be connected to a second RF antenna 64 that receives the second measurement signal from a device under test or the device under test described above. Alternatively, the second RF port 62 may be connected to the device under test via a cable. In an embodiment, the second measurement signal may be an RF signal or a baseband signal.

In an embodiment, the second measurement signal may correspond to the same measurement signal as the first measurement signal or to a different measurement signal than the first measurement signal.

If the second measurement signal received is an RF signal, the second frequency converting circuit 60 is configured to down-convert the second measurement signal in frequency, namely to an intermediate frequency. In this case, the down-converted second measurement signal is forwarded to the second signal distribution circuit 38.

In an embodiment, the second frequency converting circuit 60 may receive the LO signal from the second LO port 42 via the second signal distribution circuit 38, and may mix the second measurement signal with the received LO signal, thereby down-converting the second measurement signal.

Of course, the second frequency converting circuit 60 may comprise at least one filter in order to remove unwanted signal components from the second measurement signal mixed with the LO signal.

If the second measurement signal received is a baseband signal, the second frequency converting circuit 60 may be bypassed. In this case, the second measurement signal may be forwarded to the second signal distribution circuit 38.

As is indicated by the dotted lines, the measurement path comprising the second frequency converting circuit 60 and the second RF port 62 may be inactive in the adjustment mode of the test and/or measurement system 10 illustrated in FIG. 1. Accordingly, in the adjustment mode, the second signal distribution circuit 38 may not forward the second measurement signal to the second ADC 40.

In an embodiment, the test and/or measurement system 10 further comprises a processing circuit 66 that is connected to both the first ADC 24 and the second ADC 40. Accordingly, in the adjustment mode, the processing circuit 66 receives the first digitized LO signal from the first ADC 24 and the second digitized LO signal from the second ADC 40.

In the example embodiment shown in FIG. 1, the processing circuit 66 comprises a first digital signal processing sub-circuit 68 that is integrated into the first measurement circuit 12, and a second digital signal processing sub-circuit 70 that is integrated into the second measurement circuit 14. In an embodiment, the first digital signal processing sub-circuit 68 and the second digital signal processing sub-circuit 70 are connected by a data-transmitting connection, such that the signal processing sub-circuits 68, 70 form a single logical unit.

Alternatively, the processing circuit 66 may be completely integrated into the first measurement circuit 12. Alternatively, the processing circuit 66 may be completely integrated into the second measurement circuit 14. Alternatively, the processing circuit 66 may be provided separately from the first measurement circuit 12 and the second measurement circuit 14. In an embodiment, the processing circuit 66 may be established separately from the first measurement circuit 12 and separately from the second measurement circuit 14, for example on a physically distinct circuit board and/or in a separate housing.

FIG. 2 shows the test and/or measurement system 10 described above, however not in the adjustment mode but in a measurement mode. Hereinafter, only the differences compared to the adjustment mode described hereinafter are explained.

The test and/or measurement system 10 has a first measurement mode, which is associated with the measurement signals being RF signals. In the first measurement mode, the first signal distribution circuit 22 is configured to forward the LO signal to both the first LO port 26 and the first frequency converting circuit 32, while the second distribution circuit 38 is configured to forward the LO signal from the second LO port 42 to the second frequency converting circuit 60.

In the first measurement mode, the first signal distribution circuit 22 is configured to forward the down-converted first measurement signal from the first frequency converting circuit 32 to the first ADC 24. Further, the second signal distribution circuit 38 is configured to forward the down-converted second measurement signal from the second frequency converting circuit 60 to the second ADC 40.

In the first measurement mode, the first ADC 24 is configured to digitize the down-converted first measurement signal, thereby obtaining a first digitized measurement signal. The second ADC 40 is configured to digitize the down-converted second measurement signal, thereby obtaining a second digitized measurement signal. The digitized measurement signals are forwarded to the processing circuit 66, respectively.

The test and/or measurement system 10 further has a second measurement mode, which is associated with the measurement signals being baseband signals. In the second measurement mode, the first signal distribution circuit 22 is configured to forward the first measurement signal being a baseband signal to the first ADC 24, and the second signal distribution circuit 38 is configured to forward the second measurement signal being a baseband signal to the second ADC 40.

The first frequency converting circuit 32 and the second frequency converting circuit 60 may be bypassed, such that a signal path between the first RF port 34 and the first ADC 24 is free of frequency converting circuits, and such that a signal path between the second RF port 62 and the second ADC 40 is free of frequency converting circuits.

FIG. 3 shows an example embodiment of the first signal distribution circuit 22 that is associated with the first measurement mode and the adjustment mode described above. It is to be understood that the second signal distribution circuit 38 may be established similarly to the first signal distribution circuit 22, but may be configured differently as described above.

In an embodiment of FIG. 3, the first signal distribution circuit 22 comprises a power divider 72 that is configured to split the LO signal into a first signal path 74 and into a second signal path 76. For example, the power divider 72 may be a Wilkinson power divider.

The first signal path 74 is connected to the first LO port 26, such that the LO signal is forwarded from the power divider 72 to the first LO port 26. The second signal path 76 comprises a first switching circuit 78 and a second switching circuit 80.

In the adjustment mode, the switching circuits 78, 80 are switched such that the LO signal is forwarded to the first ADC 24, namely via the first signal adjustment circuit 30.

In the first measurement mode, the first switching circuit 78 is switched such that the LO signal is forwarded to the first frequency converting circuit 32. The second switching circuit 80 is switched such that the down-converted first measurement signal is forwarded to the first ADC 24.

FIG. 4 shows another example embodiment of the first signal distribution circuit 22 that is associated with the second measurement mode and the adjustment mode described above. Hereinafter, only the differences compared to the first variant of the first signal distribution circuit 22 described above are explained.

As is illustrated in FIG. 4, the first frequency converting circuit 32 may be omitted or bypassed, such that the first switching circuit 78 described above can be omitted or set to the switching position that connects the second switching circuit 80 to the power divider 72. In the adjustment mode, the second switching circuit 80 is switched such that the LO signal is forwarded to the first ADC 24. In the second measurement mode, the second switching circuit 80 is switched such that the first measurement signal being a baseband signal is forwarded to the first ADC 24.

FIG. 5 shows another example embodiment of the first signal distribution circuit 22 that is associated with the first measurement mode and the adjustment mode described above. Compared to the example described above with respect to FIG. 3, the first switching circuit 78 is replaced by a first directional coupler 82, which is configured to forward the LO signal to both the second switching circuit 80 and to the first frequency converting circuit 32.

FIG. 6 shows another example embodiment of the first signal distribution circuit 22 that is associated with the second measurement mode and the adjustment mode described above. Compared to the example described above with respect to FIG. 4, the power divider 72 is replaced by a second directional coupler 84, which is configured to forward the LO signal to both the second switching circuit 80 and to the first LO port 26.

It is to be understood that further variations and/or combinations of the example embodiments of the first signal distribution circuit 22 described above are possible, and are within the scope of the claimed subject matter.

As already described above, in the adjustment mode, the processing circuit 66 receives the first digitized LO signal and the second digitized LO signal. Optionally, the LO signal generated by the LO circuit 16 in the adjustment mode may be a baseband signal in order to bypass an LO suppression that may be provided by the signal adjustment circuits 30, 44.

In general, the processing circuit 66 is configured to determine a phase drift between the first digitized LO signal and the second digitized LO signal based on the first digitized LO signal and the second digitized LO signal received in the adjustment mode, namely in order to correct phase drift occurring in the test and/or measurement system 10, and/or in order to synchronize the first measurement circuit 12 with the second measurement circuit 14.

For example, the processing circuit 66 may be configured to determine the phase drift by applying a correlation operation to the first digitized LO signal and the second digitized LO signal. In an embodiment, the correlation operation may comprise determining a cross-correlation between the digitized LO signals. In another embodiment, the correlation operation may comprise a fit function that is applied to the digitized LO signals. In another embodiment, the correlation operation may comprise a multiplication of the first digitized LO signal and the second digitized LO signal, for example a convolution of the first digitized LO signal with the second digitized LO signal.

In an embodiment, the test and/or measurement system 10 is configured to adapt a frequency of the LO signal generated by the LO circuit 16 and/or a phase of the LO signal generated by the LO circuit 16 at least once during the adjustment mode, such that at least two different LO signals having different frequencies and/or phases are generated.

In an embodiment, the processing circuit 66 may be configured to control the LO circuit 16 to generate the at least two different LO signals having different frequencies and/or phases. An example of this procedure is illustrated in FIG. 7. The LO circuit 16 first generates an LO signal 86 having a first auxiliary frequency faux, 1, which is digitized by both the first ADC 24 and the second ADC 40, thereby obtaining the corresponding first digitized LO signal 88 and the corresponding second digitized LO signal 90.

It is noted that, of course, the first digitized LO signals 88 and the corresponding second digitized LO signal 90 are actually time-displaced with respect to each other, but this time-displacement is not shown in FIG. 7 for illustration purposes.

After a certain time period, the LO circuit 16 generates an LO signal 92 having a second auxiliary frequency faux, 2, which is digitized by both the first ADC 24 and the second ADC 40, thereby obtaining the corresponding first digitized LO signal 94 and the corresponding second digitized LO signal 96.

In an embodiment, the processing circuit 66 digitally extrapolates the digitized LO signals 88, 90. The processing circuit 66 may then determine a first reference time at which both first digitized LO signals 88, 94 have a zero-crossing simultaneously. Further, the processing circuit 66 may determine a second reference time at which both second digitized LO signals 90, 94 have a zero-crossing simultaneously.

By choosing appropriate auxiliary frequencies faux, 1 and faux, 2, the phase drift between the digitized LO signals can be determined with large accuracy. It is noted that the values faux, 1=6200 MHz and faux, 1=7400 MHz shown in FIG. 7 are purely examples.

For example, the different auxiliary frequencies may be chosen to be a base frequency fbase multiplied with different prime numbers. This ensures that all ambiguities are resolved and that there is only a single simultaneous zero-crossing within several clock cycles of the reference clock signal (“SYSSYNC” in FIG. 7).

Determining the first reference time and the second reference time allows to precisely match corresponding samples of the first ADC 24 and of the second ADC 40, as the sample of the first ADC 24 at the first reference time has to correspond to the sample of the second ADC 40 at the second reference time. Thus, the measurement circuits 12, 14 can be synchronized in a particularly precise manner.

In an embodiment, the phase drift between the digitized LO signals obtained in the adjustment mode can be used to correct phase drifts between the digitized measurement signals in the first measurement mode and/or in the second measurement mode.

As is further illustrated in FIG. 8, the synchronization and/or phase drift correction procedure described above can be extended to an arbitrary number of measurement circuits.

In the example embodiment shown in FIG. 8, the test and/or measurement system 10 further comprises a third measurement circuit 98, which may be established identically to the first measurement circuit 12 and/or the second measurement circuit 14. The third measurement circuit 98 comprises a third LO port 100 that is configured to receive the LO signal.

In the embodiment shown in FIG. 8, the LO signal is distributed to the second LO port 42 and to the third LO port 100 by a star connection.

In the embodiment shown in FIG. 9, the measurement circuits 12, 14, 98 are connected in series, i.e. in a “daisy chain” manner.

In an embodiment, the second measurement circuit 14 may comprise an LO through port 102, which is connected to the second LO port 42 and the third LO port 100. Thus, the LO signal is forwarded from the first LO port 26 to the third LO port 100 via the second LO port 42 and the LO through port 102.

The synchronization and/or phase drift correction procedure described above can be applied to the measurement circuits 12, 14, 98 in a pairwise manner or to all measurement circuits 12, 14, 98 simultaneously.

Certain embodiments disclosed herein include systems, apparatus, modules, units, devices, components, etc., that utilize circuitry (e.g., one or more circuits) in order to implement standards, protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph. It will be further appreciated that the terms “circuitry,” “circuit,” “one or more circuits,” etc., can be used synonymously herein.