14 and the first bonding terminals 151, as shown in FIG. 4, the bonding terminals 15 may be arranged in at least one row along the first direction X. In the same row, the first bonding terminals 15 and the second bonding terminals 152 may be alternately distributed. In contrast to a plurality of first bonding terminals 151 concentrated on one side, when the first bonding terminals 151 and the second bonding terminals 152 are alternately distributed, one first bonding terminal 151 may be close to one corresponding touch lead 14 to be connected to with the first bonding terminal 151, making it easier to connect the first bonding terminal 151 and the corresponding touch lead 14.

When the total number of the bonding terminals required for the data lines 12 is relatively large, the number of the second bonding terminals 152 may be relatively large. Correspondingly, in the same row, multiple second bonding terminals 151 may be disposed between two adjacent first bonding terminals 151.

As shown in FIG. 2, the touch leads 14 close to the bonding area BA may be generally evenly distributed along the first direction X. As an example, in one same row, the first bonding terminals 151 may be also evenly distributed in the first direction X. That is, the distance between any two adjacent first bonding terminals 151 may be equal in n the first direction X. For example, along the first direction X, every first bonding terminal 151 may be provided at an interval of 4 mm.

When the sizes of the second bonding terminals 152 are the same, the number of the second bonding terminals 152 arranged between every two adjacent first bonding terminals 151 may be the same.

Further, the first gating circuits 161 connected to the first bonding terminals 151 may be disposed close to the first bonding terminals 151. When the first bonding terminals 151 are evenly distributed in the first direction, the first gating circuits 161 may be also uniformly distributed in the first direction X.

For example, in one embodiment, as shown in FIG. 3, one first gating circuit 161 may include a first transistor T1 and a second transistor T2. The first transistor T1 may be connected between one corresponding first data line 121 and one corresponding first bonding terminal 151. The second transistor T2 may be connected between one corresponding touch lead 14 and the corresponding first bonding terminal 151. The gate of the first transistor T1 may be connected to a corresponding first control line MUX1, and the gate of the second transistor T2 may be connected to a corresponding second control line MUX2.

The working process of the display panel may include a display phase and a touch detection phase. In the display phase, the first transistor T1 may be turned on and the second transistor T2 may be turned off. In the touch detection phase, the second transistor T2 may be turned on and the first transistor T1 may be turned off.

One second bonding terminal 152 may be connected to one corresponding second data line 122, and the second bonding terminals 152 may not need to be connected to the touch leads 14. For ease of explanation, the path through which the data signal is transmitted to the first data line 121 through the first bonding terminal 151 and the first transistor T1 is called the first path, and the path through which the data signal is transmitted through the second bonding terminal 152 to the second data line 122 is called the second path. Compared with the second path, the first path may additionally include the first transistor T1, and the impedance of the transistor T1 may be larger than the impedance of the wiring. Therefore, during the display stage of the display panel, the impedance on the first path may be higher than the impedance on the second path, thus affecting the display effect.

The impedance difference between the above-mentioned first path and the second path may be reduced through various implementation methods.

In an implementation manner to reduce the impedance difference between the first path and the second path, the impedance of the first bonding terminal 151 may be set to be smaller than the impedance of the second bonding terminal 152. Since the impedance of the first bonding terminal 151 is small, the overall impedance of the first path may tend to be consistent with the overall impedance of the second path even when the data signal is transmitted through the first bonding terminal 151 to the first data line 121 through the first transistor T1. Therefore, the impedance difference between the first path and the second path may be reduced, improving the display effect.

As an example, in one embodiment, an area of an orthogonal projection of the first bonding terminal 151 on the substrate of the display panel may be larger than an area of an orthogonal projection of the second bonding terminal 152 on the substrate of the display panel. That is, the first bonding terminal 151 may be designed to be larger, and the second bonding terminal 152 may be designed to be smaller. When the first bonding terminal and the second bonding terminal are made of same materials, the impedance of one bonding terminal may be smaller when the area of the bonding terminal is larger. For example, in the first direction X, the width of the first bonding terminal 151 may be larger than the width of the second bonding terminal 152, and the length of the first bonding terminal 151 may be equal to the length of the second bonding terminal 152 in the second direction Y.

In another implementation manner to reduce the impedance difference between the first path and the second path, the width-to-length ratio of the channel of the first transistor T1 may be increased to reduce the impedance of the first transistor T1, thereby reducing the impedance difference between the first path and the second path. The width-to-length ratio of the channel is the ratio of the channel width of a transistor to its conducting length.

For example, as shown in FIG. 5, one pixel 11 may include a pixel circuit 111 and a light-emitting element 112. The pixel circuit 111 is connected to the light-emitting element 112 to drive the light-emitting element 112 to emit light.

The pixel circuit 111 may include driving transistors and switching transistors. The driving transistors may be used to generate a driving current. Driven by the driving current, the light-emitting element 112 may emit light. FIG. 5 exemplarily shows a pixel circuit with a “7T1C” structure where “T” represents a transistor and “C” represents a capacitor. The “7T1C” structure may include 7 transistors and 1 capacitor. In FIG. 5, transistors M2 to M7 may be all used as switching transistors, and transistor M1 may be used as the driving transistor.

To improve the driving capability of the driving transistor, the width-to-length ratio of the channel of the driving transistor may be usually larger than the width-to-length ratio of the channel of the switching transistor in the pixel circuit. When the width-to-length ratio of the channel of a transistor is larger, the area occupied by the transistor may be larger.

In some embodiments, the width-to-length ratio of the channel of the first transistor T1 may be larger than the width-to-length ratio of the channel of the switching transistor in the pixel circuit, thereby increasing the width-to-length ratio of the channel of the first transistor T1.

In some other embodiments, the width-to-length ratio of the channel of the first transistor T1 may be less than or equal to the width-to-length ratio of the channel of the driving transistor in the pixel circuit. Therefore, the width-to-length ratio of the channel of the first transistor T1 may be increased to a certain extent while the area occupied by the first transistor T1 may be taken into account, thereby facilitating the realization of a narrow frame.

In another implementation manner of reducing the impedance difference between the first path and the second path, the overall impedance of the connection line used to connect the devices on the first path may be reduced.

For example, in one embodiment, as shown in FIG. 6, the first bonding terminal 151 may be connected to the first data line 121 through a first connection line 171, and the second bonding terminal 152 may be connected to the second data line 122 through a second connection line 172. The first connection line 171 may include two sections. One section of the first connection line 171 may be connected between the first bonding terminal 151 and the first transistor T1, and another section may be connected between the first transistor T1 and the first data line 121.

For example, when the wiring length of the first connection line 171 and the wiring length of the second connection line 172 are substantially equal, the impedance per unit length of the first connection line 171 may be smaller than the impedance per unit length of the second connection line 172. Therefore, the overall impedance of the first connection line 171 may be reduced to reduce the impedance difference between the first path and the second path.

For another example, when the impedance per unit length of the first connection line 171 is substantially equal to the impedance per unit length of the second connection line 172, the length of the first connection line 171 may be designed to be smaller than the length of the second connection line 172. Therefore, the overall impedance of the first connection line 171 may also be reduced.

In one embodiment, the wiring width of the first connection line 171 may be larger than the wiring width of the second connection line 172, thereby reducing the impedance per unit length of the first connection line 171.

In another embodiment, the first connection line 171 and the second connection line 172 may be made of a same material.

With the development of display technology, the display panel is developing towards a direction of higher and higher resolutions. Therefore, a larger number of data lines 12 are required. If one bonding terminal 15 is only used for one data line 12, the total number of the required bonding terminals 15 may be very large, which will undoubtedly increase the difficulty of the bonding process. Moreover, the bonding terminals 15 and the pins of the driving chips are usually connected in a one-to-one correspondence, which will also increase the number of pins of the driving chips and increase the cost of the driving chips.

In some embodiments, as shown in FIG. 7, the display panel may further include second gating circuits 162. One second gating circuit 162 may include a first gating unit 1621 and a second gating unit 1622. The first gating unit 1621 may be connected between multiple first data lines 121 and one corresponding first gating circuit 161, and the second gating unit 1622 may be connected between multiple corresponding second data lines 122 and one corresponding second bonding terminal 152. Therefore, one first bonding terminal 151 may be shared by multiple first data lines 121, and one second bonding terminal 152 may be shared by multiple second data lines 122. The total number of the bonding terminals may be reduced, thereby reducing the difficulty of the bonding process and also helping to reduce the cost of the driving chips.

The second gating circuits 162 may be disposed in the non-display area NA.

In one second gating circuit 162, the input terminal of the first gating unit 1621 may be connected to the first transistor T1, and multiple output terminals of the first gating unit 1621 may be respectively connected to the multiple first data lines 121. As an example, the first gating unit 1621 may include a transistor T5 and a transistor T6. A first terminal of the transistor T5 and a first terminal of the transistor T6 may both be connected to the first transistor T1. A second terminal of the transistor T5 may be connected to one corresponding first data line 121, and a second terminal of the transistor T6 may be connected to another corresponding first data line 121.

In the second gating circuit 162, the input terminal of the second gating unit 1622 may be connected to the second bonding terminal 152, and the multiple output terminals of the second gating unit 1622 may be respectively connected to the multiple second data lines 122. As an example, the second gating unit 1622 may include a transistor T7 and a transistor T8. A first terminal of the transistor T7 and a first terminal of the transistor T8 may be both connected to the second bonding terminal 152. A second terminal of the transistor T7 may be connected to one of the corresponding second data lines 122, and a second terminal of the transistor T8 may be connected to another one of the corresponding second data lines 122.

For example, in one embodiment, the gate of the transistor T5 and the gate of the transistor T7 may be both connected to the control line MUX, and the gate of the transistor T6 and the gate of the transistor T8 may be both connected to the control line MUX6.

The working process of the display panel may include the display phase and the touch detection phase. In the display phase, the first transistor T1 may be turned on, the second transistor T2 may be turned off, and the transistors T5 and T6 may be turned on in a time-sharing manner, and the transistors T7 and T8 may be turned on in a time-sharing manner. For example, the transistor T5 and the transistor T7 may be turned on first, then the transistor T5 and the transistor T7 may be turned off, and the transistor T6 and the transistor T8 may be turned on. In the touch detection stage, the second transistor T2 may be turned on, the first transistor T1 may be turned off, and the transistors T5, T6, T7, and T8 may be turned off.

The present disclosure also provides a driving chip. The driving chip may be a TDDI chip, and may be used to control the display function and the touch function of the display panel.

In one embodiment as shown in FIG. 8, the driving chip 200 may include a plurality of output pins 21. The plurality of output pins 21 may include first output pins 211. The first output pins 211 may be used for transmission of data signals and touch signals in a time-sharing manner.

Exemplarily, in one embodiment, the plurality of output pins 21 of the driving chip 200 may be connected with the plurality of bonding terminals 15 of the display panel 100 in the above embodiments in a one-to-one correspondence. The first output pins 211 may be connected to the first bonding terminal 151.

In the driving chip provided by the embodiments of the present disclosure, the first output pins 211 may be used to transmit the data signals and the touch signals in a time-sharing manner. Therefore, the first output pins 211 may be multiplexed by the data signals and touch signals in a time-sharing manner. Compared with the situation where the data signals and touch signals use different output pins, the present disclosure may multiplex some output pins without increasing the total number of output pins, thereby avoiding an increase in the difficulty of the bonding process and helping to ensure product yield.

In some embodiments, as shown in FIG. 8, the driving chip 200 may also include a plurality of display driving circuits 22, a plurality of touch driving circuits 23 and third gating circuits 24.

The plurality of display driving circuits 22 may be used to process the data signals, and one display driving circuit 22 may include a first display driving circuit 221. An output terminal of the first display driving circuit 221 may be connected to one corresponding first output pin 211 through one corresponding third gating circuit 24.

The plurality of touch drive circuits 23 may be used to process the touch signals. For example, part of the touch drive circuits 23 may be used to transmit the touch drive signals, and another part of the touch drive circuits 23 may be used to receive the touch sensing signals. An output end of one touch driving circuit 23 may be also connected to one corresponding first output pin 211 through one corresponding third gating circuit 24.

One third gating circuit 24 may be used to connect one corresponding first display driving circuit 221 and one corresponding touch driving circuit 23 to one corresponding first output pin 211 in a time-sharing manner.

In other embodiments, as shown in FIG. 9, gating circuits may not be provided in the connection paths between the first output pins 211 and the display driving circuits 22 and the touch driving circuits 23. When one first display driving circuit 221 transmits the data signal to one corresponding first output pin 211, one corresponding touch driving circuit 23 is in the non-working state. When the touch signal is transmitted between one touch driving circuit 23 and one corresponding first output pin 211, one corresponding first display driving circuit 221 may be in the non-working state. Therefore, even without gating circuits, the first output pins 211 may be able to transmit the data signal and the touch signal in a time-sharing manner, avoiding crosstalk between the data signal and the touch signal.

When one driving circuit is in the non-working state, the output terminal of the driving circuit may not output a signal to one corresponding first output pin 211 or the output terminal of the driving circuit may not receive a signal from the corresponding first output pin 211.

The total number of the bonding terminals required for the data lines 12 may be larger than the total number of the bonding terminals required for the touch leads 14, such that the total number of the output pins required for the data lines 12 may be larger than the total number of the output pins required for the touch leads 14.

In some embodiments, as shown in FIG. 8 or FIG. 9, some of the plurality of display driving circuits 22 may be second display driving circuits 222, and some of the plurality of output pins 21 may be second output pins 212. One second output pin 212 may be connected to one corresponding second display driving circuit 222, and the second output pins 212 may be not connected to the touch driving circuits 23. The second output pin 212 may be used for transmitting the data signals and does not transmit the touch signals.

For example, in one embodiment, the total number of the bonding terminals required for all data lines 12 may be N1, and the total number of bonding terminals required for all touch leads may be N2. Therefore, the total number of the output pins may be N1, and N2 output pins of the output pins may be multiplexed by the data signals and the touch signals. Further, N1-N2 output pins may only transmit the data signals and may be no longer multiplexed.

To facilitate the connection between the output pins of the driving chip and the corresponding bonding terminals, as shown in FIG. 8 or FIG. 9, multiple output pins 21 may be arranged in at least one row along the first direction X. The multiple first output pins 211 and the multiple second output pins 212 may be alternately distributed.

In one embodiment, for example, the multiple first output pins 211 may be distributed evenly in the first direction Y.

In one embodiment, as an example, in one same row, the multiple first output pins 211 may be also evenly distributed in the first direction X. That is, the distance between any two adjacent first output pins 211 may be equal in the first direction X. For example, along the first direction X, every first output pin 211 may be provided at an interval of 4 mm.

When the sizes of the second output pins 212 are the same, the number of the second output pins 212 arranged between every two adjacent first output pins 211 may be the same.

Further, the third gating circuits 24 connected to the first output pins 211 may be disposed close to the first output pins 211. When the first output pins 211 are evenly distributed in the first direction, the third gating circuits 24 may be also uniformly distributed in the first direction X.

For example, in one embodiment, as shown in FIG. 8, one third gating circuit 24 may include a third transistor T3 and a fourth transistor T4.

The first terminal of the third transistor T3 and the first terminal of the fourth transistor T4 may both be connected to one corresponding first output pin 21. The second terminal of the third transistor T3 may be connected to one corresponding first display driving circuit 221, and the second terminal of the fourth transistor T4 may be connected to one corresponding touch driving circuit 23. The gate of the third transistor T3 may be connected to a corresponding third control line MUX