It is known that output characteristics of an amplification circuit change due to the influence of the load mismatch or the reflected signal. In particular, it is known that output characteristics of an amplification circuit change depending on whether the impedance as viewed from the output terminal of the amplification circuit toward the load is inductive or capacitive.

FIG. 4B and FIG. 4C are schematic graphs showing change in output characteristics of the amplification circuits of Comparative Example 1 caused by the load mismatch. FIG. 4B is a schematic diagram illustrating input/output characteristics of the amplification circuits when the load 80 is inductive. When the load 80 is inductive, the gain of the amplification circuits tends to increase as compared with the case where the load 80 is a resistive load.

FIG. 4C is a schematic diagram illustrating the input/output characteristics of the amplification circuits when the load 80 is capacitive. When the load 80 is capacitive, the gain of the amplification circuits tends to decrease as compared with the case where the load 80 is a resistive load. As described above, the direction of change in the gain of the amplification circuit (i.e., whether it increases or decreases) is known to be reversed depending on whether the load 80 is inductive or capacitive.

When the gain of the amplification circuit or the output power of the amplification circuit changes due to the change of the load 80 in this manner, it is inconvenient that power of an intended value cannot be supplied to the load 80.

FIG. 5 is a block diagram showing a configuration of an amplifying apparatus of Comparative Example 2 in which an isolator is provided between the load 80 and the combiner in order to avoid the above-described inconvenience. In the amplifying apparatus of Comparative Example 2, even if the load 80 changes and the load mismatch occurs, the reflected signal is absorbed by the isolator, so the reflected signal does not reach the output terminal of each amplification circuit. Thus, the above-described inconvenience does not occur.

However, as described above, the high-power isolator is large in physical size and is expensive. Further, the high-power isolator has a limit on its maximum output, which may affect the output characteristics of the amplification circuits.

Thus, in the amplifying apparatus 60 of the present embodiment, the input-side transmission lines 64A, 64B, 64C and the output-side transmission lines 65B, 65C, 65D are provided, and this configuration enables suppression of the influence of the load change without providing a high-power isolator. Hereinafter, the operation and effects of this configuration will be described by referring to FIG. 6A to FIG. 7D.

FIG. 6A to FIG. 6D are schematic diagrams illustrating the operation and effects of the amplifying apparatus 60 when the load 80 is capacitive. Of the configuration of the amplifying apparatus 60 according to the embodiment shown in FIG. 3, FIG. 6A extracts and shows only the parallel element circuit composed of the first amplification circuit 62A and the third amplification circuit 62C.

A parallel element circuit is a circuit that is composed of: two amplification circuits provided in parallel; and an impedance conversion circuit provided between a load and an output end of at least one of the two amplification circuits. An impedance conversion circuit is a circuit configured such that a polarity of reactance as viewed from an output terminal of one of two amplification circuits toward a load becomes opposite to a polarity of reactance as viewed from an output terminal of the other of two amplification circuits toward the load.

As shown in FIG. 6A, when the load 80 is capacitive, the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80 is substantially the same as the impedance of the load 80 and is capacitive.

FIG. 6B is a schematic diagram illustrating the input/output characteristics of the first amplification circuit 62A. When the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80 is capacitive, the gain of the first amplification circuit 62A tends to decrease as compared with the case where the load 80 is resistive.

The second λ/4 transmission line 65C is provided as an impedance conversion circuit between the output terminal of the third amplification circuit 62C and the combiner 63. Thus, when the load 80 is capacitive (i.e., when the polarity of the reactance component of the load 80 is negative), the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 is inductive (i.e., the polarity of the reactance component of the load 80 is positive).

More specifically, the second λ/4 transmission line 65C has a function of causing the impedance as viewed from a circuit point between the combiner 63 and the second λ/4 transmission line 65C toward the load 80 to become different from the impedance as viewed from another circuit point between the second λ/4 transmission line 65C and the third amplification circuit 62C toward the load 80. That is, providing the second λ/4 transmission line 65C between the combiner 63 and the third amplification circuit 62C can make both the polarity of the reactance component of the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 and the polarity of the reactance component of the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80 opposite to each other.

In other words, the second λ/4 transmission line 65C has an effect of generating a phase difference of 180° between (a) the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 and (b) the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80.

Both the first 3λ/8 transmission line 64A provided between the first amplification circuit 62A and the divider 61 and the first λ/8 transmission line 64C provided between the third amplification circuit 62C and the divider 61 function as a phase adjustment circuit for making the respective phases of the two RF signals divided by the divider 61 the same at the two input terminals of the combiner 63.

FIG. 6C is a schematic diagram illustrating the input/output characteristics of the third amplification circuit 62C. When the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 is inductive, the gain of the third amplification circuit 62C tends to increase as compared with the case where the load 80 is resistive.

FIG. 6D is a schematic diagram illustrating the characteristics of the combined output of the respective outputs of the first amplification circuit 62A and the third amplification circuit 62C (i.e., output of the combiner 63). In the output of the combiner 63, decrease in the gain of the first amplification circuit 62A is complemented by increase in the gain of the third amplification circuit 62C. As a result, the amplifying apparatus 60 behaves in almost the same manner as in the case of supplying power to a resistive load.

FIG. 7A to FIG. 7D are schematic diagrams illustrating the operation and effects of the amplifying apparatus 60 when the load 80 is inductive. The configuration of the amplifying apparatus 60 shown in FIG. 7A is the same as the configuration shown in FIG. 6A.

As shown in FIG. 7A, when the load 80 is inductive, the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80 is substantially the same as the impedance of the load 80 and is inductive.

FIG. 7B is a schematic diagram illustrating the input/output characteristics of the first amplification circuit 62A. When the impedance as viewed from the output terminal of the first amplification circuit 62A toward the load 80 is inductive, the gain of the first amplification circuit 62A tends to increase as compared with the case where the load 80 is resistive, contrary to the case where the load 80 is capacitive of FIG. 6B.

The second λ/4 transmission line 65C is provided as an impedance transformation circuit between the combiner 63 and the output terminal of the third amplification circuit 62C. Thus, when the load 80 is inductive (i.e., the polarity of the reactance component of the load 80 is positive), the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 is capacitive (i.e., the polarity of the reactance component of the load 80 is negative).

FIG. 7C is a schematic diagram illustrating the input/output characteristics of the third amplification circuit 62C. When the impedance as viewed from the output terminal of the third amplification circuit 62C toward the load 80 is capacitive, the gain of the third amplification circuit 62C tends to decrease as compared with the case where the load 80 is resistive.

FIG. 7D is a schematic diagram illustrating the characteristics of the combined output of the respective outputs of the first amplification circuit 62A and the third amplification circuit 62C (i.e., output of the combiner 63). In the output of the combiner 63, decrease in the gain of the third amplification circuit 62C is complemented by increase in the gain of the first amplification circuit 62A. As a result, the amplifying apparatus 60 behaves in almost the same manner as in the case of supplying power to a resistive load.

In the parallel element circuit composed of the first amplification circuit 62A and the third amplification circuit 62C as described above, the second λ/4 transmission line 65C is provided as an impedance conversion circuit between the third amplification circuit 62C and the combiner 63. Hence, regardless of whether the load 80 changes into an inductive load or a capacitive load, the amplifying apparatus 60 can behave in almost the same manner as in the case where the load 80 is a resistive load, thereby the gain change of the amplifying apparatus 60 can be suppressed, and consequently, stable input/output characteristics can be provided.

The other parallel element circuit composed of the second amplification circuit 62B and the fourth amplification circuit 62D in the amplifying apparatus 60 also has the same effects as those of the parallel element circuit described by using FIG. 6A to FIG. 7D. In other words, the parallel element circuit includes an impedance conversion circuit between the load and the output terminal of at least one of two amplification circuits. The impedance conversion circuit is configured in such a manner that the polarity of the reactance as viewed from the output terminal of one of two amplification circuits toward the load is opposite to the polarity of the reactance as viewed from the output terminal of the other of two amplification circuit toward the load.

In other words, the transmission line between the combiner and the output terminal of the amplification circuit has a transmission line length corresponding to the wavelength that generates a phase difference of 180° between the impedance as viewed from the output terminal of the other of the amplification circuits toward the load 80 and the impedance as viewed from the output terminal of one of the amplification circuits toward the load 80. The amplifying apparatus 60 includes two parallel element circuits, including one pair of the first amplification circuit 62A and the third amplification circuit 62C, and the other pair of the second amplification circuit 62B and the fourth amplification circuit 62D. Thus, in each of the two parallel element circuits, the gain change of the amplifying apparatus 60 can be suppressed and stable input/output characteristics as a whole can be provided.

As shown in FIG. 3, between the first to fourth amplification circuits 62A, 62B, 62C, and 62D, the impedance as viewed from the output terminal of each amplification circuit (62A, 62B, 62C, or 62D) toward the load 80 through the impedance conversion circuit is different. In other words, the impedance as viewed from the output terminal of at least one of two amplification circuits constituting each parallel element circuit toward the load 80 via the impedance conversion circuit is different between the plurality of parallel element circuits. In the first embodiment, the number of the parallel element circuits is two. The amplifying apparatus 60 enables heat dispersion and radiation of the amplification circuits by being provided with such a plurality of parallel element circuits. Hereinbelow, on the basis of FIG. 8 and FIG. 9, a description will be given of the layout of the plurality of amplification circuits in the amplifying apparatus 60 and the effects of heat dispersion of the amplification circuits.

FIG. 8 is a graph illustrating the drain current of the amplification circuit based on the phase of the load 80. “The phase of the load 80” refers to the phase of the complex impedance or the phase of the complex reflection coefficient as viewed from the output terminal of the amplification circuit toward the load 80. FIG. 8 schematically shows the drain current of the amplification circuit when the phase of the load 80 is changed to −135°, −90°, −45°, 0°, 45°, 90°, 135°, 180° in the amplifying apparatus according to Comparative Example 1. As shown in FIG. 8, the drain current of the amplification circuit tends to be larger as the phase of the load 80 is closer to −90° which is on the most capacitive side, and the drain current of the amplification circuit tends to be smaller as the phase of the load 80 is closer to 90° which is on the most inductive side. Thus, the amplification circuit tends to generate more heat in the case when the drain current is larger on the capacitive side, and the amplification circuit tends to generate less heat when the drain current is smaller on the inductive side.

FIG. 9 illustrates the relationship between the phase of the load 80 and heat generation in the Smith chart. FIG. 9 uses shade of hatching to schematically illustrate high/low level of the heat generation temperature when the phase of the load 80 (i.e., the phase with respect to the impedance as viewed from the output terminal of each amplification circuit toward the load 80) is 0°, 45°, 90°, 135°, 180°, −135°, −90°, or −45°.

As shown in FIG. 9, the heat generation of the amplification circuit becomes larger as the phase of the load 80 becomes closer to −90° which is on the most capacitive side, and the heat generation of the amplification circuit becomes smaller as the phase of the load 80 becomes closer to 90° which is on the most inductive side. In other words, the amount of heat generation differs depending on the phase of the load 80. In each of FIG. 10A, FIG. 10B, FIG. 12, FIG. 13, FIG. 15, and FIG. 16 described below, the temperature of heat generation by the amplification circuit constituting the amplifying apparatus is schematically indicated by using the shade of hatching.

FIG. 10A and FIG. 10B illustrate the heat dispersion of the plurality of amplification circuits and their layout in the amplifying apparatus. FIG. 10A illustrates a schematic layout of the amplifying apparatus composed of two parallel element circuits, and the phase of the load 80 is −90° in one of two parallel element circuits and is 90° in the other one. FIG. 10B illustrates a schematic layout in the amplifying apparatus 60 according to the first embodiment composed of: a parallel element circuit in which the phases of the load 80 are −90° and 90°; and another parallel element circuit in which the phases of the load 80 are 0° and 180°.

In the circuit layout of FIG. 10A, the plurality of amplification circuits are disposed such that the phases of the load 80 are in the order of −90°, −90°, 90°, 90° from the top in FIG. 10A, that is, two amplifier circuits 262A in which the phase of the load 80 is −90° are biasedly disposed on one side of the amplifying apparatus 60 whereas two amplifier circuits 262B in which the phase of the load 80 is 90° are biasedly disposed on the other side of the amplifying apparatus 60. Thus, there is an imbalance in the amount of heat generated within the amplifying apparatus.

In the circuit layout of FIG. 10B, the plurality of amplification circuits are disposed such that the phases of the load 80 are in the order of −90°, 0°, 90°, 180° from the top in FIG. 10B, and thus, the heat of the amplification circuits are dispersed within the amplifying apparatus 60. In other words, in the amplifying apparatus 60 according to the first embodiment, the amplification circuits are disposed within the amplifying apparatus in such a manner that the phase with respect to the impedance is dispersed as viewed from the output terminal of each amplification circuit toward the load 80. Such a layout of the amplification circuits can reduce the imbalance in the amount of heat generation within the amplifying apparatus while maintaining stable input/output characteristics.

Modification of First Embodiment of Amplifying Apparatus

FIG. 11 is a block diagram illustrating a configuration of the amplifying apparatus 60 according to a modification of the first embodiment. The amplifying apparatus 60 according to the first embodiment is composed of two parallel element circuits. Since each of both parallel element circuits includes two amplification circuits, the amplifying apparatus 60 according to the first embodiment has a total of four amplification circuits. In the amplifying apparatus 60 according to the first embodiment, the number of amplification circuits forming each parallel element circuit is two. By contrast, the amplifying apparatus 60 according to the modification of the first embodiment is composed of n/2 parallel element circuits as shown in FIG. 11. Since each of the parallel element circuits includes two amplification circuits similarly to the first embodiment, the amplifying apparatus 60 according to the modification of the first embodiment has a total of “n” amplification circuits, wherein “n” is a positive even number. The amplifying apparatus 60 according to the modification of the first embodiment may be composed of three or more parallel element circuits, for example.

The divider 61 divides the input signal RFin outputted from the RF transmission-wave generator 35 into n input signals. The input signals divided into n channels by the divider 61 are inputted to each of the n amplification circuits.

The n input-side transmission lines 164 (164A, 164B, and 164C in the case of FIG. 11) are provided between the divider 61 and the input terminals of the n amplification circuits. The input-side transmission lines function as the phase adjustment circuits. Each of the n input-side transmission lines 164 is configured as a transmission line having a transmission line length corresponding to a (n−k)/2n wavelength for the k-th amplification circuit among the n amplification circuits, wherein “k” is a natural number from 1 to n. Regarding the (k=n)-th route, the input-side transmission line is not substantially provided or added.

In addition, n output-side transmission lines 165 (165B, 165C, and 165D in the case of FIG. 11) are provided between the combiner 63 and the output terminals of the n amplification circuits. The output-side transmission lines function as the impedance conversion circuits. Each of the n output-side transmission lines is configured as a transmission line with a transmission line length corresponding to a (k−1)/2n wavelength for the k-th amplification circuit. Regarding the k=1st route (i.e., first route), the output-side transmission line is not substantially provided or added.

The input-side transmission lines and the output-side transmission lines are configured such that the sum of the transmission line length of the input-side transmission line and the transmission line length of the output-side transmission line in each of the n amplification circuits is a length corresponding to a (n−1)/2n wavelength.

For example, in FIG. 11, the input-side transmission line 164A of λ(n−1)/2n, the input-side transmission line 164B of λ(n−2)/2n, and the input-side transmission line 164C of λ/2n are respectively provided between the divider 61 and the input terminal of the first amplification circuit 162A, the second amplification circuit 162B, or the (n−1)-th amplification circuit 162C. The output-side transmission line 165B of λ/2n, the output-side transmission line 165C of λ(n−2)/2n, and the output-side transmission line 165D of λ(n−1)/2n are respectively provided between the combiner 63 and the output terminal of the second amplification circuit 162B, the (n−1)-th amplification circuit 162C, or the n-th amplification circuit 162D. Note that λ is a wavelength.

The combiner 63 combines the output signals outputted from the n amplification circuits and supplies the combined signal to the RF coil as an RF signal. In other words, the input signal is divided into n channels by the divider 61, amplified by n amplification circuits, and then combined.

In the amplifying apparatus 60, n phase adjustment circuits are provided between the divider 61 and the respective input terminals of the n amplification circuits, and n impedance conversion circuits are provided between the combiner 63 and the respective output terminals of the n amplification circuits. Each of the n phase adjustment circuits adjusts the phase of the k-th amplification circuit among the n amplification circuits to a phase corresponding to a (n−k)/2n wavelength. Each of the n impedance conversion circuits adjusts the phase of the k-th amplification circuit to a phase corresponding to a (k−1)/2n wavelength. Further, the phase adjustment circuits and the impedance conversion circuits are configured in such a manner that, in each of the n amplification circuits, the sum of the phase of the phase adjustment circuit and the phase of the impedance conversion circuit corresponds to a (n−1)/2n wavelength.

Hereafter, a description will be given of the effects of heat dispersion in the amplification circuits of the modification of the first embodiment. FIG. 12 is a schematic diagram illustrating a first layout of the plurality of amplification circuits in the amplifying apparatus 60 according to the modification of the first embodiment. The amplifying apparatus 60 in FIG. 12 is composed of: amplification circuits 362A to 362H in the case of n=8 as an aspect of the plurality of amplification circuits; input-side transmission lines 364A to 364G; and output-side transmission lines 365B to 365H. FIG. 12 illustrates the layout of the amplifying apparatus 60 including four parallel element circuits composed of: a first parallel element circuit in which the phases of the load 80 are −90° and 90°; a second parallel element circuit in which the phases of the load 80 are 0° and 180°; a third parallel element circuit in which the phases of the load 80 are −45° and 135°; and a fourth parallel element circuit in which the phases of the load 80 are 45° and −135°.

In the circuit layout of FIG. 12, inside the amplifying apparatus, the eight amplification circuits 362A to 362H in which the phases of the load 80 are respectively −90°, −45°, 0°, 45°, 90°, 135°, 180°, and −135° are connected in parallel next to each other in order. In this circuit layout, for example, the amplification circuits 362A and 362B are disposed to be adjacent to each other, and the amplification circuit 362B and 362C are disposed to be adjacent to each other.

In other words, the respective n amplification circuits corresponding to n different phases obtained by dividing the phase range from −180° to +180° into n at equal intervals are arranged in phase order. The imbalance in the heat amount to be generated within the amplifying apparatus can be alleviated by appropriately arranging the n amplification circuits on the basis of the relationship between heat generation amount and the phase for the impedance as viewed from the output terminal of each amplification circuit toward the load 80 as shown in the Smith chart in FIG. 9. That is, the heat of the n amplification circuits can be dispersed within the amplifying apparatus.

FIG. 13 illustrates another circuit layout different from the amplifying apparatus 60 in FIG. 12. In the circuit layout of FIG. 13, in the amplifying apparatus, eight amplification circuits 362A to 362H in which the phases of the load 80 are respectively 90°, −45°, 0°, 45°, −90°, 135°, 180°, and −135° are arranged in parallel next to each other. In this circuit layout, for example, the amplification circuits 362E and 362B are disposed next to each other, and the amplification circuits 362B and 362C are disposed next to each other. In this manner, the respective n amplification circuits corresponding to n different phases obtained by dividing the phase range from −180° to +180° into n at equal intervals may not need to be arranged in phase order. For example, in the amplifying apparatus 60, the n amplification circuits may be arranged in such a manner that the polarity of the reactance as viewed from the output terminal of each amplification circuit toward the load 80 is opposite to or different from that of the adjacent amplification circuit.

For example, the amplifying apparatus 60 may be configured such that two amplification circuits constituting each of the parallel element circuits are not adjacent to each other. For example, for each of four pairs including: a first parallel element circuit in which the phases of the load 80 are −90° and 90°, a second parallel element circuit in which the phases of the load 80 are 0° and 180°, a third parallel element circuit in which the phases of the load 80 are −45° and 135°, and a fourth parallel element circuit in which the phases of the load 80 are 45° and −135°, two amplification circuits constituting each of these four parallel element circuits may be arranged to be not adjacent to each other.

The amplifying apparatus 60 according to the modification of the first embodiment can increase the output power of the amplifying apparatus 60 while maintaining the effects of the first embodiment.

Second Embodiment of Amplifying Apparatus

FIG. 14 is a block diagram illustrating a configuration of the amplifying apparatus 60 according to the second embodiment. The amplifying apparatus