having control logic (e.g., local media controller 135) on the die and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

In one embodiment, the memory sub-system 110 includes a memory interface component 113. Memory interface component 113 is responsible for handling interactions of memory sub-system controller 115 with the memory devices of memory sub-system 110, such as memory device 130. For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

In one embodiment, the memory sub-system controller 115 includes a log manager 134 employed to perform failure-related data logging operations. Information stored by such logs may include, e.g., error messages, event data, failure-related data (including bitline threshold voltage distributions and associated metadata), media endurance data, other device health data, etc. The logged failure-related data and other log data may then be utilized for failure diagnostics, which involves determining the failure type, as described in more detail herein below. In some embodiments, at least part of the functionality of the log manager 134 can be performed by the local media controller 135. In some embodiments, log manager 134 is implemented by firmware, hardware components, or a combination of the above.

FIG. 2 is a simplified block diagram of a first apparatus, in the form of a memory device 130, in communication with a second apparatus, in the form of a memory sub-system controller 115 of a memory sub-system (e.g., memory sub-system 110 of FIG. 1), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller 115 (e.g., a controller external to the memory device 130), can be a memory controller or other external host device.

Memory device 130 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a wordline) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bitline). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells (not shown in FIG. 2) of at least a portion of array of memory cells 104 are capable of being programmed to one of at least two target data states.

Row decode circuitry 108 and column decode circuitry 111 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 204. Memory device 130 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 130 as well as output of data and status information from the memory device 130. An address register 114 is in communication with I/O control circuitry 112 and row decode circuitry 108 and column decode circuitry 111 to latch the address signals prior to decoding. A command register 124 is in communication with I/O control circuitry 112 and local media controller 135 to latch incoming commands.

A controller (e.g., the local media controller 135 internal to the memory device 130) controls access to the array of memory cells 104 in response to the commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells 204. The local media controller 135 is in communication with row decode circuitry 108 and column decode circuitry 111 to control the row decode circuitry 108 and column decode circuitry 111 in response to the addresses.

The local media controller 135 is also in communication with a cache register 218. Cache register 118 latches data, either incoming or outgoing, as directed by the local media controller 135 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data. During a programming operation (e.g., a write operation), data can be passed from the cache register 118 to the data register 121 for transfer to the array of memory cells 204; then new data can be latched in the cache register 118 from the I/O control circuitry 212. During a read operation, data can be passed from the cache register 118 to the I/O control circuitry 112 for output to the memory sub-system controller 115; then new data can be passed from the data register 121 to the cache register 218. The cache register 118 and/or the data register 121 can form (e.g., can form a portion of) a page buffer of the memory device 130. A page buffer can further include sensing devices (not shown in FIG. 2) to sense a data state of a memory cell of the array of memory cells 204, e.g., by sensing a state of a data line connected to that memory cell. A status register 122 can be in communication with I/O control circuitry 112 and the local memory controller 135 to latch the status information for output to the memory sub-system controller 115.

Memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 over a control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be further received over control link 132 depending upon the nature of the memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 over a multiplexed input/output (I/O) bus 136 and outputs data to the memory sub-system controller 115 over I/O bus 136.

For example, the commands can be received over input/output (I/O) pins [7:0] of I/O bus 136 at I/O control circuitry 112 and can then be written into command register 224. The addresses can be received over input/output (I/O) pins [7:0] of I/O bus 136 at I/O control circuitry 112 and can then be written into address register 214. The data can be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and then can be written into cache register 218. The data can be subsequently written into data register 121 for programming the array of memory cells 204.

In an embodiment, cache register 118 can be omitted, and the data can be written directly into data register 220. Data can also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference can be made to I/O pins, they can include any conductive node providing for electrical connection to the memory device 130 by an external device (e.g., the memory sub-system controller 115), such as conductive pads or conductive bumps as are commonly used.

In some implementations, additional circuitry and signals can be provided, and that the memory device 130 of FIG. 2 has been simplified. It should be recognized that the functionality of the various block components described with reference to FIG. 2 can not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of FIG. 2. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of FIG. 2. Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) can be used in the various embodiments.

FIG. 3 schematically illustrates a programming architecture implemented by the host system 120 in communication with the memory sub-system controller 115 managing one or more memory devices 130, in accordance with one or more aspects of the present disclosure. As schematically illustrated by FIG. 3, the host system may run one or more applications 310A-310B. In an illustrative example, the application 310A may be in communication with the file system driver 320, which may be running in the kernel space of the host system 120 and may be employed for processing certain system calls, such as read and write calls initiated by one or more applications 310, including the application 310A, running in the user space of the host system 120. The file system driver 320 may be employed to translate the read, write, and other system calls issued by the application 310A into low-level application programming interface (API) calls to the storage driver 330, which, in turn may communicate to the memory sub-system controller 115. The storage driver 330 may be running in the kernel mode of the host system and may be employed to process API calls issued by the file system driver 320 and/or system calls issued by the application 310B into storage interface commands to be processed by the storage the memory sub-system controller 115.

In some implementations, the storage driver 330 may implement a block storage model, in which the data is grouped into blocks of one or more pre-defined sizes and is addressable by a block number. The block storage model may implement “read” and “write” command for storing and retrieving blocks of data. In an illustrative example, the storage driver 330 may implement a key-value storage model, in which the data is represented by the “value” component of a key-value pair is addressable by the “key” component of the key-value pair. The key value storage model may implement “put and get” commands, which are functionally similar to the “write” and “read” commands of the block storage model. Thus, the term “data item” as used herein may refer to a data block or to a key-value pair.

In some implementations, the file system driver 320 and/or the storage driver 330 may support I/O control commands for retrieving the logs maintained by the log manager 134 of the memory-subsystem 110.

As noted herein above, the log manager 134 may maintain one or more logs, which may be stored on one or more memory devices and retrieved via the host interface. Information stored by such logs may include warning and error messages, event data, media endurance data, other device health data, etc. In some implementations, responsive to detecting a failure of the memory sub-system or one of its memory devices, the log manager 134 may store, in one or more log files, the failure-related data, which may include including bitline threshold voltage distributions and associated metadata. The metadata logged at the time of failure may include identifiers of page, block, and/or die exhibiting the failure and associated program-erase counter (PEC) values, power-on-time, die temperature values, etc.

FIG. 4 schematically illustrates an example bitline threshold voltage distribution that may be captured and logged by the log manager 134, in accordance with aspects of the present disclosure. As schematically illustrated by FIG. 4, for each bitline of a chosen set of bitlines of a memory device, plot 400 shows the threshold voltage values that have caused the bitline to transition from a non-conductive state to a conductive state in response to the threshold voltage having been applied to a selected wordline. In other words, for every dot in plot 400, its horizontal coordinate identifies a bitline, while the vertical coordinate represents the threshold voltage values that have caused the bitline to transition from a non-conductive state to a conductive state in response to the threshold voltage having been applied to a selected wordline. In an illustrative example of FIG. 4, the plot 400 of the bitline threshold voltage distribution has a tail 410 trailing off towards the lower threshold voltage values, which can be indicative of a resistive short or other contact within the media array (“failure type A”).

In various illustrative example, general failure mechanisms may include oxide breakdowns, shorts, resistive contacts via oxide formation or other, pinchoff, or pillar misalignment. These failures might also be “soft” failures, which could be a symptom of slight process variation that can't be attributed to any specific defect mode.

As noted herein above, the bitline threshold voltage distribution and associate metadata data may be utilized for training failure type prediction models that determine failure types. FIG. 5 schematically illustrates an example failure type prediction model operating in accordance with one or more aspects of the present disclosure. As schematically illustrated by FIG. 5, the failure type prediction model 500 may receive failure-related data 510 including bitline threshold voltage distributions and associated metadata which can be extracted from one or more log files produced by the log manager 134. For each detected failure, the failure type prediction model 500 may yield the failure type(s) 520 derived from failure-related data 510.

In some implementations, the failure type prediction model 500 may by implemented by one or more trainable classifiers. In an illustrative example, each trainable classifier may be implemented by one or more neural networks. In other illustrative examples, classifiers operating in accordance with aspects of the present disclosure may employ decision trees, rule-based engines, and/or other suitable technologies.

In some implementations, further processing can be done on the bitline data via grouping; windowing, subsets via random selection or N selection (selecting 1 bit every N) to reduce sample size and computation within the system.

“Neural network” herein refers to a computational model, which may be implemented by software, hardware, or combination thereof. A neural network includes multiple inter-connected nodes called “artificial neurons,” which loosely simulate neurons of a human brain. An artificial neuron may process a signal received, over a first edge, from another artificial neuron and transmit the transformed signal over a second edge to a third artificial neuron. The output of each artificial neuron may be represented by a mathematical transformation of a combination of its inputs. Edge weights, which increase or attenuate the signals being transmitted through respective edges connecting the neurons, as well as other network parameters, may be determined by training the network.

A supervised training process may utilize a training dataset that includes a set of data items labeled in accordance with known classification. In an illustrative example, training a neural network involves initializing the edge weights and/or other network parameters to random or predetermined values. For every input data item in the training dataset, the neural network is activated to produce an output, which is then compared with the desired output specified by the label associated with the input data item in the training dataset, and the error is back-propagated through layers of the neural network, in which the weights and/or other parameters are adjusted accordingly. This process may be repeated until the output error falls below a predetermined threshold.

As noted herein above, a classifier operating in accordance with aspects of the present disclosure may be trained by a supervised learning process using a training dataset that utilizes the failure-related data which is extracted from the log files produced by the log manager 134. As schematically illustrated by FIG. 5, each item 530A-530N of the training dataset 525 may include failure-related data 532 (including bitline threshold voltage distributions and associated metadata) labeled with a corresponding failure type 534.

The trained failure type prediction model may be employed to process the failure-related data extracted from one or more log files of a failed memory-subsystem in order to determine the actual failure type or predict a potential failure type. In an illustrative example, a failed memory sub-system may be shipped to the original equipment manufacturer (OEM) for failure analysis, and the log data extraction may be performed by the OEM. In an illustrative example, the log data may be extracted in the field upon detecting a memory sub-system failure, and the extracted log data may be transmitted to the OEM for failure analysis. In another illustrative example, the log data may be periodically extracted in the field irrespectively of the failure occurrences and transmitted to OEM for early detection of potential memory sub-system failures.

As further noted herein above, the process of memory-subsystem fabrication may involve post-fabrication testing of memory devices and/or their components. The testing process may involve applying certain workloads to the memory devices (e.g., program-erase cycles storing certain patterns of data, which may, in various examples, include random and/or regular patterns). However, since the field workload parameters may not be known at the time of post-fabrication testing, the results produced by the post-fabrication testing may significantly differ from the results observable in the field.

Furthermore, various component line models that predict failure type based on component line data and/or post-fabrication testing data would not yield the results that are similar to the field-observable outcomes unless such models are trained using training datasets that adequately reflect the failure type distributions observable in the field. In various illustrative examples, the component line data may include values of parameters that characterize a memory device or its components (e.g., dies), and can be yielded by a manufacturing test such as current measurement, time0 bit failures or parametric values such as CMOS oscillator variation. In some implementations, the component line data may include fabrication metrics such as physical parameters including film deposition thicknesses, etc.

FIG. 6 schematically illustrates an example component line model operating in accordance with one or more aspects of the present disclosure. As schematically illustrated by FIG. 6, the component line model 600 may receive component line data 610 for a memory device or component. In some implementations, the component line model 600 may further receive the post-fabrication testing data 615 for the memory device or component. The component line model 600 may yield the failure type(s) 620 that would be exhibited in the field by a memory device or component characterized by the input component line data 610 and/or post-fabrication testing data 615. The post-fabrication testing data may include bitline threshold voltage distributions and associated metadata for the memory device or component.

In some implementations, the component line model 600 may by implemented by one or more trainable classifiers. In an illustrative example, each trainable classifier may be implemented by one or more neural networks. In other illustrative examples, classifiers operating in accordance with aspects of the present disclosure may employ decision trees, rule-based engines, and/or other suitable technologies.

In order to ensure that the component line model 600 yields the results that match, with a predefined accuracy, the field-observable outcomes, the component line model 600 may be trained on training datasets that include, for each memory device or component of a chosen set of memory devices and/or components, both component line data and the field-observed failure-related data including bitline threshold voltage distributions and associated metadata. In an illustrative example, the field-observed failure related data may be extracted from one or more log files of a failed memory sub-system that has been shipped to the OEM for failure analysis. In an illustrative example, the field-observed failure related data may be extracted in the field from one or more log files of a failed memory sub-system and may be transmitted to the OEM for failure analysis.

As schematically illustrated by FIG. 6, each item 630A-630N of the training dataset 625 may include component line data 632 for a particular memory device or component, field-observed failure-related data 633 for the same memory device or component (including bitline threshold voltage distributions and associated metadata), and a corresponding filed-observed failure type 634. In some implementations, each item 630A-630N of the training dataset 625 may further include post-fabrication test data for the same memory device or component (including bitline threshold voltage distributions and associated metadata).

The trained component line model may be employed to process component line data and/or post-fabrication test data associated with a memory device or component in order to determine the actual failure type or predict a potential failure type.

As further noted herein above, the logged failure-related data including bitline threshold voltage distributions and associated metadata may be employed for identifying post-fabrication testing workloads that would closely simulate field workloads ensuring that the testing procedure outcomes (e.g., the failure type distributions) would match, with a predefined accuracy, the outcomes observable in the field. In some implementations, a workload prediction model may be trained to determine the post-fabrication test workload that would, for a given memory device or component characterized by component line data, produce parameters of a workload that, when utilized for performing the post-fabrication testing of the memory device or component, would yield outcomes that would match, with a predefined accuracy, the outcomes that would have been observed in the field for the same memory device or component.

FIG. 7 schematically illustrates an example workload prediction model operating in accordance with one or more aspects of the present disclosure. As schematically illustrated by FIG. 7, the workload prediction model 700 may receive component line data 710 for a memory device or component. The workload prediction model 700 may further receive field-observed failure-related data 715 (including bitline threshold voltage distributions and associated metadata) for the memory device or component. The workload prediction model 700 may yield the post-fabrication testing workload parameters derived from the input component line data 710 and field-observed failure-related data 715.

In some implementations, the workload prediction model 700 may by implemented by one or more trainable classifiers. In an illustrative example, each trainable classifier may be implemented by one or more neural networks. In other illustrative examples, classifiers operating in accordance with aspects of the present disclosure may employ decision trees, rule-based engines, and/or other suitable technologies.

The workload prediction model 700 may be trained on training datasets that include, for each memory device or component of a chosen set of memory devices and/or components, both component line data and the field-observed failure-related data including bitline threshold voltage distributions and associated metadata. In an illustrative example, the field-observed failure related data may be extracted from one or more log files of a failed memory sub-system that has been shipped to the OEM for failure analysis. In an illustrative example, the field-observed failure related data may be extracted in the field from one or more log files of a failed memory sub-system and may be transmitted to the OEM for failure analysis.

As schematically illustrated by FIG. 7, each item 730A-730N of the training dataset 725 may include component line data 732 for a particular memory device or component, field-observed failure-related data 733 for the same memory device or component (including bitline threshold voltage distributions and associated metadata), and a corresponding failure type 734.

The trained workload prediction model may be employed to process component line data associated with a memory device or component in order to determine the actual failure type or predict a potential failure type.

FIG. 8 schematically illustrates an example method 800 of implementing a failure type prediction model, in accordance with aspects of the present disclosure. The method 800 can be performed by processing logic that can include hardware (e.g., general purpose or specialized processing devices, circuitry, dedicated logic, programmable logic, microcode, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or various combinations thereof. In some implementations, method 800 may be performed by a single processing thread. Alternatively, method 800 may be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 800 may be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 800 may be executed asynchronously with respect to each other. In some embodiments, the method 800 is performed by the example computer system 1100 of FIG. 11. Operations of the method 800 can be specified by a sequence of command codes, which the processing logic can retrieve from a dedicated storage location. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in various embodiments. Thus, not all operations are required in every embodiment.

As schematically illustrated by FIG. 8, at operation 810, the processing logic implementing the method receives a first failure-related dataset reflecting a first bitline threshold voltage distribution associated with a first memory device. The first bitline threshold voltage distribution may specify, for every bitline of a chosen set of bitlines of the first memory device, one or more threshold voltage values that have caused the bitline to transition from a non-conductive state to a conductive state in response to a threshold voltage value of the one or more threshold voltage values having been applied to a selected wordline of the memory device. The first failure-related dataset can further comprise a plurality of metadata items associated with the first bitline threshold voltage distribution. The first failure-related dataset can be extracted from one or more log files maintained by a memory sub-system controller, as described in more detail herein above.

At operation 820, the processing logic determines, based on the first failure-related dataset, a first failure type distribution for the first memory device. In an illustrative example, the first failure type distribution reflected by the first failure-related dataset is built from one or more graphical user interface (GUI) inputs allowing a user to label the first bitline threshold voltage distribution with one or more failure types. In an illustrative example, the first failure type distribution reflected by the first failure-related dataset is determined by applying a rule-based logic or a decision tree-based logic to the first failure-related dataset.

At operation 830, the processing logic creates a training dataset comprising the first failure-related dataset and the first failure type distribution, as described in more detail herein above.

At operation 840, the processing logic trains, using the training dataset, a failure type prediction model to determine, for a second memory device, a second failure type distribution based on a second failure-related dataset comprising second bitline threshold voltage data associated with a second memory device, as described in more detail herein above.

At operation 850, the processing logic utilizes the failure type prediction model to determine, for the second memory device, the second failure type distribution based on the second failure-related dataset comprising second bitline threshold voltage data associated with the second memory device, as described in more detail herein above.

FIG. 9 schematically illustrates an example method 900 of implementing a failure type prediction model, in accordance with aspects of the present disclosure. The method 900 can be performed by processing logic that can include hardware (e.g., general purpose or specialized processing devices, circuitry, dedicated logic, programmable logic, microcode, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or various combinations thereof. In some implementations, method 900 may be performed by a single processing thread. Alternatively, method 900 may be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 900 may be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 900 may be executed asynchronously with respect to each other. In some embodiments, the method 900 is performed by the example computer system 1100 of FIG. 11. Operations of the method 900 can be specified by a sequence of command codes, which the processing logic can retrieve from a dedicated storage location. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in various embodiments. Thus, not all operations are required in every embodiment.

As schematically illustrated by FIG. 9, at operation 910, the processing logic implementing the method receives a first component line dataset associated with a first memory device.

At operation 920, the processing logic receives a first post-fabrication testing dataset comprising a first bitline threshold voltage distribution associated with the first memory device. The first failure-related dataset can be extracted from one or more log files maintained by a memory sub-system controller, as described in more detail herein above.

At operation 930, the processing logic creates a training dataset comprising the first component line dataset and the first post-fabrication testing dataset, as described in more detail herein above.

At operation 940, the processing logic trains, using the training dataset, a component line model to predict, based on a second component line dataset associated with a second memory device and a second post-fabrication testing dataset comprising a second bitline threshold voltage distribution associated with the second memory device, a second failure type distribution to be exhibited in the field by the second memory device, as described in more detail herein above.

At operation 950, the processing logic utilizes the component line model to predict, based on the second component line dataset associated with the second memory device and the second post-fabrication testing dataset comprising the second bitline threshold voltage distribution associated with the second memory device, the second failure type distribution to be exhibited in the field by the second memory device, as described in more detail herein above.

FIG. 10 schematically illustrates an example method 1000 of implementing a workload prediction model, in accordance with aspects of the present disclosure. The method 1000 can be performed by processing logic that can include hardware (e.g., general purpose or specialized processing devices, circuitry, dedicated logic, programmable logic, microcode, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or various combinations thereof. In some implementations, method 1000 may be performed by a single processing thread. Alternatively, method 1000 may be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 1000 may be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 1000 may be executed asynchronously with respect to each other. In some embodiments, the method 1000 is performed by the example computer system 1100 of FIG. 11. Operations of the method 1000 can be specified by a sequence of command codes, which the processing logic can retrieve from a dedicated storage location. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in various embodiments. Thus, not all operations are required in every embodiment.

As schematically illustrated by FIG. 10, at operation 1010, the processing logic implementing the method receives a first component line dataset associated with a first memory device.

At operation 1020, the processing logic receives a first failure-related dataset comprising a first bitline threshold voltage distribution associated with the first memory device. The first failure-related dataset can be extracted from one or more log files maintained by a memory sub-system controller, as described in more detail herein above.

At operation 1030, the processing logic creates a training dataset comprising the first component line dataset and the first failure-related dataset, as described in more detail herein above.

At operation 1040, the processing logic trains, using the training dataset, a workload prediction model to predict, based on a second component line dataset associated with a second memory device and a second bitline threshold voltage distribution associated with the second memory device, a second post-fabrication testing workload to be applied to the second memory device in order to yield a post-fabrication testing outcome that would match, with a predefined accuracy, a filed-observable outcome for the second memory device, as described in more detail herein above.

At operation 1050, the processing logic utilizes the workload prediction model to predict, based on the second component line dataset associated with the second memory device and the second bitline threshold voltage distribution associated with the second memory device, the second post-fabrication testing dataset to be applied to the second memory device in order to yield a post-fabrication testing outcome that would match, with a predefined accuracy, a filed-observable outcome for the second memory device, as described in more detail herein above