21 through ST2m arranged in a second row are coupled to a second source select line SSL2 in another example. In an embodiment, the source select transistors of the memory strings ST11 through ST1m and ST21 through ST2m are coupled in common to one source select line.

The first memory cell MC1 through the n-th memory cell MCn in each memory string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first memory cell MC1 through the n-th memory cell MCn are coupled to the first word lines WL1 through the n-th word line WLn, respectively.

In an embodiment, at least one of the memory cells MC1 to MCn is used as a dummy memory cell. When the dummy memory cell is provided, the voltage or current of the corresponding memory string is stably controlled. Accordingly, the reliability of data stored in the memory block MB1 may be improved.

The drain select transistor DST of each memory string is coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors DST of memory strings arranged in the row direction are coupled to a drain select line extending along the row direction. For example, the drain select transistors DST of the memory strings ST11 through ST1m in the first row are coupled to a first drain select line DSL1. The drain select transistors DST of the memory strings ST21 through ST2m in the second row are coupled to a second drain select line DSL2 in another example.

FIG. 5 is a flowchart illustrating an erase operation of a memory device according to an embodiment of the present disclosure.

FIG. 6 is a timing diagram of signals during the erase operation of a memory device according to an embodiment of the present disclosure.

The erase operation of the memory device according to an embodiment of the present disclosure is described below with reference to FIG. 1 through FIG. 6.

The memory device 1100 receives S510 a command CMD corresponding to an erase operation and an address ADD corresponding to a memory block on which the erase operation is to be performed. The command CMD and the address ADD may be received from the memory controller 1200.

The control logic 300 of the memory device 1100 receives the command CMD and the address ADD, which correspond to the erase operation, from the input/output circuit 250, and controls the peripheral circuits 200 to perform the erase operation on a memory block (for example, MB1) corresponding to the address ADD.

A first erase voltage Vera1 is applied S520 to at least one of a source line SL and bit lines BLs during a first period. The first erase voltage Vera1 may be a positive voltage increasing with a constant slope. For example, the voltage generating circuit 210 applies the first erase voltage Vera1 to the source line SL coupled to the selected memory block MB1 in response to receiving an operation signal OP_CMD during the first period. The page buffer group 230 applies the first erase voltage Vera1 to bit lines BL1 to BLm (BLs) of the memory cell array 100 in response to receiving page buffer control signals PBSIGNALS during the first period.

The first period is a period during which a GIDL current generation operation is performed. The voltage generating circuit 210 generates the negative voltage during at least part of a period of the GIDL current generation operation.

A negative voltage Vneg is applied S530 to the word lines WLs of the selected memory block during the first period. For example, the negative voltage generator 211 of the voltage generating circuit 210 generates the negative voltage Vneg under the control of the erase operation controller 310 and applies the negative voltage Vneg generated by the negative voltage generator 211 to all word lines WLs of the selected memory block. The negative voltage generator 211 generates the negative voltage Vneg during at least part of the first period. Vneg is a voltage lower than a ground voltage.

During the first period, the ground voltage is applied to the drain select line DSL and the source select line SSL, for example, by the row decoder 220. The drain select transistor DST and the source select transistor SST are therefore in a turned-off state. Because the drain select transistor DST and the source select transistor SST are in a turned-off state, current does not flow through channel regions of the memory cells.

The first erase voltage Vera1 gradually increases, and the potential reaches V1, such as shown in FIG. 6. That is, the potential of at least one of the source line SL and the bit lines BLs reaches V1. In one example, a potential difference between the gate of the source select transistor SST and the source line SL is V1. In another example, a potential difference between the drain select transistor DST and the bit lines BLs is V1. V1 is a voltage threshold and is, for example, a voltage having a magnitude sufficient to generate a gate induced drain leakage (GIDL) current in at least one of the channel region of the source select transistor SST and the channel region of the drain select transistor DST. The GIDL current is generated when the voltage of at least one of the source line SL and the bit lines BLs reaches or exceeds V1.

When the potential of at least one of the source line SL and the bit lines BLs reaches V1, the erase operation controller 310 controls the row decoder 220 such that the drain select line DSL and the source select line SSL float. When the drain select line DSL is floating, hot holes, also referred to as hot electrons, are formed in the channel region of the drain select transistor DST due to the potential difference V1 between the gate of the drain select transistor DST and the plurality of bit lines BLs. The formed hot holes are moved to the channel regions of the plurality of memory cells. When the source select line SSL is floating, hot holes are formed in the channel region of the source select transistor SST due to the potential difference V1 between the gate of the source select transistor SST and the source line SL. The formed hot holes are moved to the channel regions of the plurality of memory cells.

In an embodiment of the present disclosure, the channel potential of the memory cells is controlled at a negative potential by applying the negative voltage Vneg to all word lines WLs during the period for the above-described GIDL current generation operation, for example, the first period of FIG. 6. Compared to the example when the ground voltage is applied to all word lines WLs, in the example when the negative voltage Vneg is applied to all word lines WLs, the channel potential of the memory cells is relatively low, and band-to-band generation of carriers between at least one of the source line SL and the bit lines BLs and the channels of the memory cells increases, resulting in an increase in the quantity of holes injected from at least one of the source line SL and the bit lines BLs into the channels. Accordingly, compared to the example when the ground voltage is applied to all word lines WLs, in the example when the negative voltage Vneg is applied to all word lines WLs, the potential of V