FIG. 4 may mean a power supply voltage, and VSS may mean a ground voltage.

Accordingly, a cycle type of FIG. 4 indicates whether a command input in each cycle is a command or an address. For example, when the cycle type is a command, data currently input through a data bus indicates a command, and when the cycle type is an address, data currently input through the data bus indicates an address. In addition, I/O [7:0] indicates a data bus, and a ready (RDY) signal is a signal informing the controller whether the NAND flash memory device is ready or in use (eg, erase operation in progress), At the first time when this signal reaches the LOW level, the NAND flash memory device notifies the controller that the erase operation is currently in progress, and this is to inform the controller that the erase operation of the NAND flash memory device is currently in progress at a tBERS when this signal becomes the LOW level. That is, the NAND flash memory device maintains a high state of a pin transmitting the red (RDY) signal among a plurality of pins connected to the controller until it becomes a busy state for performing a specific operation, and may change to the low state at the point in time when the busy state is reached.

In this case, the erase operation of the NAND flash memory device as described above may be largely divided into three sections. The first section is a time for transferring a command and an address to the NAND flash memory device, and the second section means a time (tWB) required until the NAND flash memory device enters a busy state for performing a specific operation, and the third section means a time (tBERS) for erasing memory cells in block units.

In addition, the NAND flash memory device as described above operates based on a power supply voltage (eg, VCC). But, when the power supply voltage is reduced to a level at which the NAND flash memory device cannot normally perform, intermittent data corruption occurs.

That is, when the input voltage decreases below a certain level while the NAND flash memory device is performing a program or erase operation, the NAND flash memory device stops the operation and then resumes the program or erase operation when a normal voltage is input.

In this case, a non-volatile memory such as the NAND flash memory device generates a charge gain differently from a volatile memory when a power reset (or power supply interruption) is performed during the program or erase operation as described above. Here, the charge gain refers to a state in which the threshold voltage Vt of a cell is located in a marginal region that does not distinguish between ‘0’ and ‘1’. Here, the marginal region means a region in which the threshold voltage Vt of the cell is between 0V and the reference threshold voltage RV. In this case, since the memory may perform an erroneous operation, the reliability of the product is greatly reduced.

FIG. 5 is a view illustrating a charge gain in a NAND flash memory device. Referring to FIG. 5, the NAND flash memory device includes a charge gain generated during a program operation and a charge gain generated during an erase operation.

As shown in FIG. 5(a), the NAND flash memory device may perform a program operation according to a command of the controller. And, when the power is cut off while the electrons are moving by the program operation, the movement of the electrons is stopped when the power is cut off. Here, the threshold voltage Vt of the memory cell when the program operation is stopped may be located in a marginal region where ‘0’ and ‘1’ cannot be distinguished. And, when the threshold voltage Vt of the memory cell is located in the marginal region as described above, the controller (to be described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is ‘0’ or ‘1’. This may cause system failure.

As shown in FIG. 5(b), the NAND flash memory device may perform an erase operation according to a command of the controller. And, when the power is cut off while the electrons are moving by the erase operation, the movement of the electrons is stopped when the power is cut off. Here, the threshold voltage Vt of the memory cell at the point in time when the erase operation is stopped may be located in a marginal region in which ‘0’ and ‘1’ cannot be distinguished. And, when the threshold voltage Vt of the memory cell is located in the marginal region as described above, the controller (to be described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is ‘0’ or ‘1’. This may cause system failure.

Hereinafter, a NAND flash memory system according to an embodiment will be described.

FIG. 6 is a block diagram illustrating an element of a NAND flash memory system according to a first embodiment.

Referring to FIG. 6, the system 100 includes a power supply device and a control device 200. The power supply device may include a converter 110, an input voltage detector 120, and a detection signal transmitter 130.

The converter 110 of the power supply device may receive an input voltage corresponding to a main power, convert the input voltage into a voltage required by each element of the control device 200 and output the converted voltage.

In addition, the input voltage detector 120 of the power supply may detect the voltage of the main power and output a detected signal.

Also, the detection signal transmitter 130 of the power supply device may transmit an output signal of the input voltage detector 120 to the control device 200.

The control device 200 may include a storage device. The control device 200 may operate by using a voltage input from the power supply device as a driving voltage. The control device 200 may communicate with the vehicle controller 300 and store data transmitted from the vehicle controller 300. For example, the control device 200 may be provided in a vehicle to support an eCall function of the vehicle. That is, the control device 200 may communicate with the vehicle controller 300 to store information for reporting and requesting relief in an emergency situation. For example, the information may include accident occurrence location information, vehicle type information, driving direction information, a number of seat belts operated at the time of the accident, and the like.

The control device 200 may include a memory 210, a power supply unit 220, an auxiliary power unit 230, and a controller 240. In addition, the controller 240 of the control device 200 may control the memory 210. Preferably, the controller 240 may receive an operation signal (eg, a ready and busy output signal) from the memory 210, and access to the memory 210 based on the received operation signal. The operation signal may correspond to the timing of the NAND flash memory device constituting the memory 210. Here, the timing may be converted into a different time period according to an operation type of the device. For example, the different time period for each operation type includes a time tR (reading operation) for loading data from a memory cell (not shown) into a page register (not shown), a time tPROG (program operation) for loading data from a page register into a memory cell, a time tBERS (erase operation for erasing memory cells in block units and the like.

Also, the controller 240 of the control device 200 may control access to the memory 210 based on an output signal according to an input voltage operation transmitted from the power supply devices 110, 120, and 130.

Specifically, the controller 240 of the control device 200 may stop the operation of the memory under an unstable condition of the input voltage or a data protection condition of the memory 210 based on the output signal of the input voltage detector 120 of the power supply device transmitted from the power supply device 110, 120, 130. Here, stopping the operation of the memory 210 may mean stopping access to the memory 210, and furthermore, it may mean blocking the output of a command for controlling the operation of the memory 210. That is, the controller 240 of the control device 200 detects the unstable condition or the data protection condition of the input voltage while the protection function of the memory 210 is on, and based on this, the memory 210 operation can be stopped.

Hereinafter, the control device 200 and the power supply devices 110, 120, and 130 will be described in detail.

The power supply device may include a converter 110, an input voltage detector 120, and a detection signal transmitter 130. At this time, although each component of the power supply devices 110, 120, and 130 is illustrated as being configured separately from the control device 200 in the drawings, the embodiment is not limited thereto. That is, some of the elements constituting the power supply devices 110, 120, and 130 may be included in the control device 200.

The converter 110 may receive an input voltage and convert the input voltage to generate an output voltage.

The converter 110 may be implemented as a regulator. That is, the regulator may receive an input voltage through an input terminal and output an output voltage obtained by converting the input voltage through an output terminal. The voltage supplied to the control device 200 through the regulator may be a driving voltage of each element constituting the control device 200. For example, the voltage supplied to the control device 200 through the regulator may be a driving voltage of the memory 210. The regulator supplies a stable driving voltage to the control device 200 by stabilizing and outputting the input voltage so that the memory 210 constituting the control device 200 operates stably.

Meanwhile, the input voltage input to the converter 110 may be supplied from a power supply unit (not shown). For example, the power supply unit may be a battery of a vehicle in which the NAND flash memory system is installed.

The input voltage detector 120 may detect a level of the input voltage input through the power supply unit, and output a voltage detection signal according to the detection level.

In this case, the input voltage may have a first level V1 under a normal condition.

In addition, the input voltage detector 120 may output a first voltage detection signal when the input voltage has a level in a range between the first level V1 and a second level V2 smaller than the first level V1. In addition, the input voltage detector 120 may output a second voltage detection signal when the level of the input voltage is less than the second level V2 which is smaller than the first level V2. Here, the first voltage detection signal may be a low-level detection signal, and the second voltage detection signal may be a high-level detection signal, but is not limited thereto.

To this end, the input voltage detector 120 may include a comparator (not shown). The comparator may receive a reference signal corresponding to the second level V2 through a positive terminal, and may receive the input voltage through a negative terminal, and may output a high-level or low-level voltage detection signal according to a comparison result of the input voltage and the reference signal.

Meanwhile, the input voltage detector 120 may adjust a detection voltage through a voltage dividing resistor or the like. The voltage divider resistor divides the input voltage by a predetermined voltage division ratio and transmits it to the comparator.

The detection signal transmitter 130 may be connected to the control device 200, and thus may transmit a voltage detection signal detected through the input voltage detector 120 to the control device 200. Specifically, the detection signal transmitter 130 may be connected to the controller 240 of the control device 200, and may transmit a high signal or a low signal to the controller 240 based on the voltage detection signal.

To this end, the detection signal transmitter 130 may include first to third resistors R1, R2, and R3 and a transistor S1. The first to third resistors R1, R2, R3 and the transistor S1 may be a logic circuit that converts and outputs the high voltage of the voltage detection signal into a low voltage that can be received by the controller 240 of the control device 200. A detailed connection structure and operation thereof will be described as follows.

The first resistor R1 may have one end connected to an output terminal of the input voltage detector 120 and the other end connected to one end of the third resistor R3 and a base of the transistor S1.

The second resistor R2 may have one end connected to a power terminal of the power supply unit 220 of the control device 200 and the other end connected to a collector of the transistor S1 and a signal input terminal GPIO of the controller 240.

The third resistor R3 may have one end connected to the other end of the first resistor R1 and the base of the transistor S1, and the other end connected to a emitter of the transistor S1 and a ground terminal.

Transistor S1 may have the base connected to the output terminal of the input voltage detector 120 through the first resistor R1, the collector connected to the signal input terminal GPIO of the controller 240, and the emitter connected to the ground terminal.

The transistor S1 may receive the voltage detection signal of the input voltage detector 120 through the base.

Specifically, the transistor S1 may be turned on or off by the voltage detection signal of the input voltage detector 120 input to the base. For example, the voltage detection signal may be a high signal or a low signal as described above. In addition, the transistor S1 may be switched to an on state when a high signal is applied to the base, and accordingly, may output a second detection signal indicating voltage abnormality to the collector. Also, the transistor S1 may be switched to an off state when a low signal is applied to the base, and accordingly, may output a first detection signal indicating normal voltage, which is a high signal, to the collector terminal. Meanwhile, the transistor S1 is turned on by a high signal and turned off by a low signal in the embodiment, but the embodiment is not limited thereto and operations thereof may be interchanged.

The memory 210 may be a nonvolatile memory in which data can be programmed, erased and read. For example, the memory 210 may be a nonvolatile memory device that can be electrically programmed and erased, and does not require a refresh function to rewrite data at a predetermined period. Specifically, the memory 210 may be a NAND type flash memory device.

Since the memory 210 has been described in detail with reference to FIGS. 1 to 5, a detailed description thereof will be omitted herein.

The power supply unit 220 is connected to the output terminal (out) of the converter 110 to receive the output voltage of the converter 110, and stabilize the received output voltage to apply a driving voltage to the memory 210. That is, the power supply unit 220 may be a power management IC (PMIC) that supplies a driving voltage to the memory 210. The PMIC constituting the power supply unit 220 may be a power control module composed of a discrete power device module for power output, a high voltage power circuit, a low voltage digital circuit, and a high voltage and low voltage analog circuit, and accordingly, it can serve to convert, distribute, charge, and control the input voltage input to the control device 200 according to the memory 210.

An auxiliary power supply 230 may be disposed between the power supply unit 220 and the memory 210. The auxiliary power unit 230 may be a capacitor that performs a charging operation under a first condition and a discharging operation under a second condition. Here, the first condition may be a condition in which an input voltage of a normal range is input to the input terminal of the present system, and the second condition may be a condition in which a low voltage out of the normal range is input to the input terminal.

The auxiliary power unit 230 may supply a driving voltage to the memory 210 by discharging when the output voltage of the power supply unit 220 is lower than a preset second level V2 under a system power-on condition. At this time, the discharge time of the auxiliary power unit 230 is determined in proportion to the capacity of the capacitor constituting the auxiliary power unit 230. Accordingly, the capacity of the capacitor constituting the auxiliary power supply unit 230 in the embodiment may be determined in consideration of the time for loading data from memory cells of memory 210 into page registers, the time to load data from the page register into the memory cell, the time for erasing the memory cells in block units.

The controller 240 may control the operation of the memory 210.

Specifically, the controller 240 may access to the memory 210 to control a program operation, an erase operation, and a read operation of the memory 210.

To this end, the controller 240 may be connected to the memory 210 through a bus. In addition, the controller 240 may transmit a command and an address to the memory 210 through the bus, and may transmit and receive data.

Meanwhile, the controller 240 may monitor the output signal of the detection signal transmitter 130. That is, the controller 240 may monitor a change in the input voltage input to the system.

In addition, when the first detection signal notifying that the input voltage is normal is input through the detection signal transmitter 130, the controller 240 accesses to the memory 210 to perform a program operation or an erase operation.

At this time, when the second detection signal notifying an abnormality of the input voltage is input through the detection signal transmitter 130, the controller 240 blocks the output of the command to the memory 210 from a point in time when the second detection signal is input.

In other words, when the second detection signal is input through the detection signal transmitter 130, the controller 240 blocks the command output to stop access to the memory 210.

Then, the controller 240 ignores all commands related to the operation of the memory 210 from the time when the second detection signal is input, and blocks a command from being output to the memory 210 from a time point when the second detection signal is input.

In addition, the controller 240 and the memory 210 may be powered off after a predetermined time from the time point when the second detection signal is input. Here, the predetermined time may mean a time until the operation (program operation or erase operation) previously performed by the memory 210 is normally completed by the auxiliary power supplied through the auxiliary power supply unit 230.

The power-off of the memory 210 may be performed when the input voltage of the main power to the system decreases to a third level V3 corresponding to the power-off voltage of the memory 210. That is, when the input voltage of the main power decreases to the third level V3, the memory 210 may be naturally powered off due to insufficient power.

Also, even if the input voltage of the main power is restored to the first level V1 without decreasing to the third level V3, the memory 210 may be powered off. To this end, the vehicle controller 300 may turn off the power supply unit 220 of the control device 200 to power off the control device 200. Thereafter, the vehicle controller 300 may turn on the power supply unit 220 again to power on the control device 200.

However, the memory 210 in the embodiment may be a NAND flash memory device corresponding to a non-volatile memory. In this case, unlike RAM, which is a volatile memory, data stored in a NAND flash memory device is not erased even when the input power is cut off. Accordingly, the NAND flash memory device does not have to worry about internal data loss even when the input power is cut off, and for this reason, the auxiliary power does not need to be supplied even when the power is suddenly cut off. However, unlike the RAM, the NAND flash memory device distinguishes between ‘0’ and ‘1’ by comparing the threshold voltage Vt of the memory cell with the marginal region set based on the reference threshold voltage RV, as described in FIGS. 1 to 5.

Accordingly, if the memory 210 is in a program operation or an erase operation at the time the second detection signal is input, and the power-off sequence proceeds without completing the program operation or the erase operation, the program operation or the erase operation is continued at a later power recovery time.

However, as described above, when the threshold voltage Vt of the memory cell has a value in the marginal region (0V to the reference threshold voltage RV) at the time of power recovery, it is impossible to determine whether the value of the memory 210 is ‘0’ or ‘1’, and accordingly, the controller 240 may malfunction. Accordingly, when the time point at which the second detection signal is input is the program operation time (tPROG) or the erase operation time (tBERS) of the memory 210, the controller 240 may delay the power-off sequence until the program operation or the erase operation is completed. In other words, the controller 240 may supply auxiliary power to prevent the memory 210 from being powered off until the program operation or the erase operation currently being performed by the memory 210 is completed.

In addition, the memory 210 may be driven by the discharge voltage of the auxiliary power supply 230 under the data protection condition of the memory 210 as described above to complete the program operation or the erase operation. Also, when the program operation or the erase operation is completed, the memory 210 may transmit a completion signal thereof to the controller 240.

The controller 240 may recognize that the operation of the memory 210 has been completed, and may proceed with a power-off sequence of the memory 210.

The embodiment detects an unstable state of the input power and controls the operation of the NAND flash memory device based on this, and accordingly, it is possible to prevent defects such as data corruption that may occur when the NAND flash memory device operates in an unstable state of the input power. Specifically, according to the embodiment, the flash access is blocked when the input power is unstable, and accordingly, it is possible to prevent malfunction of the NAND flash memory device in an unstable environment of the input power.

In addition, when the operation of the NAND flash memory device in the embodiment is in progress at the time of power interruption detection, auxiliary power is supplied until the ongoing operation is completed, and accordingly, it is possible to solve data corruption due to charge gain that occurs when power is blocked during a program operation or an erase operation of the NAND flash memory device. Accordingly, the operation reliability of the NAND flash memory device may be improved.

In addition, a power-off sequence of the NAND flash memory device in the embodiment is performed when a power supply interruption is detected, and a power-on sequence is performed when a normal power supply is detected, and accordingly, operation reliability and user satisfaction can be improved as the flash memory normally operates when the input power is restored.

Meanwhile, the auxiliary power unit 230 in FIG. 6 has been described as being provided in the control device 200, but the auxiliary power supply unit 230 may be disposed in a location other than between the power supply unit 220 and the memory 210 in the control device 200.

FIGS. 7 and 8 are views for explaining a modified example of the NAND flash memory system shown in FIG. 6.

Meanwhile, only the arrangement position of the auxiliary power unit of FIGS. 7 and 8 for supplying auxiliary power to the memory 210 when an abnormality occurs in the input voltage is different, and other features may be the same as in FIG. 6. Accordingly, only the auxiliary power supply unit will be described below.

Referring to FIG. 7, the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply unit 220, and a controller 240. In addition, the auxiliary power supply unit 140 is disposed between the output terminal of the converter 110 and the input terminal of the power supply unit 220. In addition, the auxiliary power unit 140 provides a discharge voltage to the power supply unit 220 when an abnormality occurs in the input voltage to the system, so that the driving voltage by the discharge voltage may be transferred to the memory 210.

In addition, referring to FIG. 8, the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply unit 220, and a controller 240. In addition, the auxiliary power supply unit 150 is disposed at the input terminal of the converter 110. In addition, the auxiliary power supply unit 150 provides a discharge voltage to the converter 110 at a time when an abnormality occurs in the input voltage to the system, so that the driving voltage may be transferred to the memory 210 by the discharge voltage.

FIG. 9 is a view for explaining step by step a method of operating a NAND flash memory system according to an exemplary embodiment.

Referring to FIG. 9, the controller 240 may access to the memory 210 and transmit a command and an address to the memory 210 under a condition that an input voltage within a normal range is input. That is, the controller 240 transmits a command to the memory 210 under the normal condition so that at least one of a program operation, an erase operation (or an delete operation) and a read operation of the memory 210 may be performed (S100).

Thereafter, the controller 240 may check the voltage detection signal input through the signal input terminal GPIO in a polling or interrupt method. In addition, the controller 240 may determine whether a second detection signal indicating that an input voltage lower than the second level V2 is detected through the signal input terminal GPIO is received (S110).

In addition, when a second detection signal indicating that an input voltage lower than the second level V2 is detected is received, the controller 240 stops access to the memory 210 and blocks the output the command provided to the memory 210 (S120).

FIGS. 10 and 11 are views showing a power sequence according to a change in an input voltage.

Referring to FIG. 10, the input voltage may have a first level V1 under a normal condition. In addition, the input voltage detector 120 and the detection signal transmitter 130 may output a voltage abnormality detection signal when the input voltage decreases to the second level V2.

Accordingly, the controller 240 may stop to the access (ACCESS STOP) to the memory 210 at a first time point T1 at which the voltage abnormality detection signal is received.

Thereafter, the level of the input voltage may continue to decrease to a third level V3. Also, when the input voltage is reduced to the third level V3, the memory 210 may be powered off due to insufficient power.

Meanwhile, the power input to the system may be momentarily cut off as shown in FIG. 10, and the level of the input voltage may decrease to 0V.

However, unlike this, the power input to the system may be restored to a normal voltage level after being momentarily cut off.

That is, referring to FIG. 11, the input voltage may have a first level V1 under a normal condition. In addition, the input voltage detector 120 and the detection signal transmitter 130 may output a voltage abnormality detection signal when the input voltage decreases to the second level V