FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of memory system 100 that is given over to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic 260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the memory system 100 is the amount of area to devote to the memory structure 202 and the amount of area to devote to the peripheral circuitry.

Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, for example, FIG. 4) in particular may benefit from specialized processing operations.

To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed dies that are then bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more dies, such as two memory dies and one control die, for example.

FIG. 2B shows an alternative arrangement to that of FIG. 2A which may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement the non-volatile storage 130 of memory system 100. The integrated memory assembly 207 includes two types of semiconductor dies (or more succinctly, “die”). Memory structure die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to the memory structure 202 in the memory structure die 201. In some embodiments, the memory structure die 201 and the control die 211 are bonded together. In an embodiment, circuitry on the control die 211 applies a stress voltage to the dummy memory holes 233 and tests whether there is a defect associated with the dummy memory holes 233.

FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 211 coupled to memory structure 202 formed in memory structure die 201. Common components are labelled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory structure die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the on the memory structure die 201.

System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory structure die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 211 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

FIG. 2B shows column control circuitry 210 including read/write circuits 225 on the control die 211 coupled to memory structure 202 on the memory structure die 201 through electrical paths 206. For example, electrical paths 206 may provide electrical connection between column decoder 212, driver circuitry 214, and block select 216 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of the memory structure die 201, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 206, including a pair of bond pads, which connects to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each electrical path 208 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 211 and memory structure die 201.

For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller 120, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read/write circuits 225, sense amps, a microcontroller, a microprocessor, and/or other similar functioned circuits. A control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FPGA, ASIC, integrated circuit, or other type of circuit.

For purposes of this document, the term “apparatus” can include, but is not limited to, one or more of, memory system 100, storage 130, memory die 200, integrated memory assembly 207, and/or control die 211.

In some embodiments, there is more than one control die 211 and more than one memory structure die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201. FIG. 3A depicts a side view of an embodiment of an integrated memory assembly 207 stacked on a substrate 271 (e.g., a stack comprising control die 211 and memory structure die). The integrated memory assembly 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are more than three memory structure dies 201 and more than three control dies 211. In FIG. 3A there are an equal number of memory structure dies 201 and control dies 211; however, in one embodiment, there are more memory structure dies 201 than control dies 211. For example, one control die 211 could control multiple memory structure dies 201.

Each control die 211 is affixed (e.g., bonded) to at least one of the memory structure die 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two die 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the die 201, 211, and further secures the die together. Various materials may be used as solid layer 280.

The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of FIG. 3A).

A memory die through silicon via (TSV) 276 may be used to route signals through a memory structure die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.

FIG. 3B depicts a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 207 of FIG. 3B has three control dies 211 and three memory structure dies 201. In some embodiments, there are many more than three memory structure dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory structure die 201. Optionally, a control die 211 may be bonded to two or more memory structure dies 201.

Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 3A, the integrated memory assembly 207 in FIG. 3B does not have a stepped offset. A memory die through silicon via (TSV) 276 may be used to route signals through a memory structure die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211.

As has been briefly discussed above, the control die 211 and the memory structure die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two die together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.

When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor die including the bond pads. The film layer is provided around the bond pads. When the die are brought together, the bond pads may bond to each other, and the film layers on the respective die may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller sizes and pitches.

Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the die may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the die together. Various materials may be used as under-fill material.

FIG. 3C is a block diagram depicting one embodiment of a portion of column control circuitry 210 that contains a number of read/write circuits 225. Each read/write circuit 225 is partitioned into a sense amplifier 325 and data latches 340. A managing circuit 330 controls the read/write circuits 225. The managing circuit 330 may communicate with state machine 262. In one embodiment, each sense amplifier 325 is connected to a respective bit line. Each bit line may be connected, at one point in time, to one of a large number of different NAND strings. A select gate on the NAND string may be used to connect the NAND string channel to the bit line.

Each sense amplifier 325 operates to provide voltages to one of the bit lines (see BL0, BL1, BL2, BL3) during program, verify, erase, and read operations. Sense amplifiers are also used to sense the condition (e.g., data state) of a memory cell in a NAND string connected to the bit line that connects to the respective sense amplifier. The following will discuss use of the sense amplifier 325 to sense a condition (e.g., data state) of a memory cell.

Each sense amplifier 325 may have a sense node. During sensing, a sense node is charged up to an initial voltage, Vsense_init, such as 3V. The sense node is then connected to the bit line for a sensing time, and an amount of decay of the sense node is used to determine whether a memory cell is in a conductive or non-conductive state. The amount of decay of the sense node also indicates whether a current Icell in the memory cell exceeds a reference current, Iref. A larger decay corresponds to a larger current. If Icell<=Iref, the memory cell is in a non-conductive state and if Icell>Iref, the memory cell is in a conductive state. In an embodiment, the sense node has a capacitor that is pre-charged and then discharged for the sensing time.

In particular, the comparison circuit 320 determines the amount of decay by comparing the sense node voltage to a trip voltage after the sensing time. If the sense node voltage decays below the trip voltage, Vtrip, the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is above the program verify voltage. A sense node latch 322 is set to 0 or 1, for example, by the comparison circuit 320 based on whether the memory cell is in a conductive or non-conductive state, respectively. The bit in the sense node latch 322 can also be used in a lockout scan to decide whether to set a bit line voltage to an inhibit or a program enable level in a next program loop. The bit in the sense node latch 322 can also be used in a lockout mode to decide whether to set a bit line voltage to a sense voltage or a lockout voltage in a read operation.

The data latches 340 are coupled to the sense amplifier 325 by a local data bus 346. The data latches 340 include three latches (ADL, BDL, CDL) for each sense amplifier 325 in this example. More or fewer than three latches may be included in the data latches 340. In one embodiment, for programming each data latch 340 is used to store one bit to be stored into a memory cell and for reading each data latch 340 is used to store one bit read from a memory cell. In a three bit per memory cell embodiment, ADL stores a bit for a lower page of data, BDL stores a bit for a middle page of data, CDL stores a bit for an upper page of data. Each read/write circuit 225 is connected to an XDL latch 348 by way of an XDL bus 352. In this example, transistor 336 connects local data bus 346 to XDL bus 352. An I/O interface 332 is connected to the XDL latches 348. The XDL latch 348 associated with a particular read/write circuit 225 serves as an interface latch for storing/latching data from the memory controller.

Managing circuit 330 performs computations, such as to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. Each set of data latches 340 is used to store data bits determined by managing circuit 330 during a read operation, and to store data bits imported from the data bus 334 during a program operation which represent write data meant to be programmed into the memory. I/O interface 332 provides an interface between XDL latches 348 and the data bus 334.

During reading, the operation of the system is under the control of state machine 262 that controls the supply of different control gate voltages to the addressed memory cell. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and a corresponding output will be provided from the sense amplifier to managing circuit 330. At that point, managing circuit 330 determines the resultant memory state by consideration of the tripping event(s) of the sense circuit and the information about the applied control gate voltage from the state machine. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 340.

During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 340 from the data bus 334 by way of XDL latches 348. The program operation, under the control of the state machine 262, applies a series of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse may be stepped up in magnitude from a previous program pulse by a step size in a process referred to as incremental step pulse programming. In one embodiment, each program voltage is followed by a verify operation to determine if the memory cells have been programmed to the desired memory state. In some cases, managing circuit 330 monitors the read back memory state relative to the desired memory state. When the two agree, managing circuit 330 sets the bit line in a program inhibit mode such as by updating its latches. This inhibits the memory cell coupled to the bit line from further programming even if additional program pulses are applied to its control gate.

FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 4 shows a portion 400 of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D. The conductive layers are labeled as one of: SGD, WL, or SGS. An SGD conductive layer serves as drain side select lines. A WL conductive layer serves as a word line. An SGS conductive layer serves as a source side select line. The numbers of each of these conductive layers is limited for ease of illustration. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 4, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure 202 is provided below.

In one embodiment the block is operated as a number of “sub-blocks.” Each of these “sub-blocks” has many NAND strings. In an embodiment, an isolation region (IR) divides the SGD layers into multiple SGD select lines, each of which is used to select a sub-block (e.g., set of NAND strings). FIG. 4 depicts an example having one IR region and thereby two strings. However, there may be more than one IR region and thereby more than two sub-blocks. Optionally, the IR region can extend down through all of the alternating dielectric layers and conductive layers.

FIG. 4A is a block diagram explaining one example organization of memory structure 202, which is divided into two planes 403-A and 403-B. Each plane 403 is then divided into M physical blocks. In one example, each plane has about 2000 physical blocks (or more briefly “blocks”). However, different numbers of blocks and planes can also be used. In one “full-block” embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In a “sub-block mode” embodiment, blocks are divided into sub-blocks and the sub-blocks are the unit of erase. In an embodiment, a block contains a number of word lines with each sub-block containing a unique set of the data word lines. In an embodiment, each plane 403-A, 403-B has a set of bit lines that extend across all of the blocks in that plane. In an embodiment, one block per plane is selected at a time. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although FIG. 4A shows two planes 403-A, 403-B more or fewer than two planes can be implemented. In some embodiments, memory structure 202 includes four planes. In some embodiments, memory structure 202 includes eight planes. In some embodiments, programming can be performed in parallel in a first selected block in plane 403-A and a second selected block in plane 403-B.

FIGS. 4B1-4F depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of FIG. 4 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B1 is a block diagram depicting a top view of a portion of block of memory cells showing an array region 411 and an embodiment of a dummy array region 412. FIG. 4B1 depicts a plurality of circles that represent the vertical columns (or memory holes). Some of the memory holes are used to implement NAND strings that are eligible to store data. Some of the memory holes do not contain NAND strings that are eligible to store data and are referred to as “dummy memory holes” or “dummy NAND strings.” The memory holes in memory array region 411 used to implement NAND strings that are eligible to store data. The dummy memory holes are in dummy array region 412. Note that the block contains many more memory holes that contain NAND strings that are eligible to store data than dummy memory holes.

Each of the vertical columns (memory holes) in memory array region 411 include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B1 depicts vertical columns 422, 432, 442, and 452. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of the vertical columns are provided below. Since the physical block depicted in FIG. 4B1 extends in the direction of arrow 433, the physical block includes more vertical columns than depicted in FIG. 4B. The vertical columns (dummy memory holes) in dummy array region 412 may be fabricated in a similar manner as the vertical columns in memory array region 411.

FIG. 4B1 also depicts a first set of bit lines 415 and a second set of dummy bit lines 417. The first set of bit lines 415 are associated with the NAND strings that are eligible to store data. The second set of dummy bit lines 417 are associated with the dummy memory holes in dummy array region 412. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. The bit lines 415 and dummy bit lines 417 may also extend over other blocks in the plane.

The block depicted in FIG. 4B1 includes a set of isolation regions 402, 404, 406, 408, and 410, which are formed of SiO₂; however, other dielectric materials can also be used. Isolation regions 402, 404, 406, 408, and 410 serve to divide the top layers of the lock into four regions; for example, the top layer depicted in FIG. 4B1 is divided into regions 420, 430, 440, and 450, which are referred to herein as “sub-blocks.” Each sub-block contains a large number of NAND strings. In one embodiment, isolation regions 402 and 410 separate the physical block 407 from adjacent physical blocks. Thus, isolation regions 402 and 410 may extend down to the substrate. In one embodiment, the isolation regions 404, 406, and 408 only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. Referring back to FIG. 4, the IR region may correspond to any of isolation regions 404, 406, or 408. In one example implementation, a bit line 415 only connects to one vertical column/NAND string in each of regions (sub-blocks) 420, 430, 440, and 450. Similarly, a dummy bit line 417 only connects to one dummy memory hole in each of regions (sub-blocks) 420, 430, 440, and 450. In that implementation, each block has sixteen rows of active columns and each bit line 415 connects to four NAND strings in each block. In one embodiment, all of the four vertical columns/NAND strings connected to a common bit line are connected to the same word line (or set of word lines); therefore, the system uses the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

Although FIG. 4B1 shows each region (420, 430, 440, 450) having four rows of vertical columns, four regions (420, 430, 440, 450) and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or fewer regions (420, 430, 440, 450) per block, more or fewer rows of vertical columns per region and more or fewer rows of vertical columns per block. FIG. 4B1 also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

Because the dummy bit lines 417 are connected to the dummy memory holes in dummy array region 412 the memory system is able to drive a voltage to the dummy memory holes in dummy array region 412. In an embodiment, the memory system drives a voltage onto one or more of the dummy bit lines 417 to provide the voltage to one or more of the dummy memory holes in dummy array region 412. The dummy bit lines 417 also allow sensing of the dummy memory holes in dummy array region 412. In an embodiment, the memory system senses a signal on one or more of the dummy bit lines 417 to sense one or more of the dummy memory holes in dummy array region 412. The sensing results may be used to determine whether there is a defect associated with the dummy memory holes.

In an embodiment, two or more of the dummy bit lines 417 are electrically connected together, which reduces the amount of circuitry needed to provide a voltage to dummy memory holes and/or sense dummy memory holes. In an embodiment, all of the dummy bit lines 417 are electrically connected together. FIG. 4B2 is a block diagram depicting a top view of a portion of block of memory cells showing a memory array region 411 and an embodiment of a dummy array region 412 in which dummy bit lines are electrically connected to each other. FIG. 4B2 depicts an embodiment in which the dummy bit lines 417 are electrically connected by conductive line 418. Voltage driver 413 may be used to drive a voltage onto the electrically connected dummy bit lines 417. Sense node 414 may be used to sense a signal on the electrically connected dummy bit lines 417. The sense node 414 and voltage driver 413 may be implemented by a read/write circuit 225 or sense amplifier 325 similar to those used for NAND strings eligible to store data. However, the sense node 414 and voltage driver 413 could be implemented with other circuitry. Because the dummy bit lines 417 are electrically connected together only a small amount of circuitry is needed to operate the dummy bit lines 417.

FIG. 4C depicts an example of a stack 435 showing a cross-sectional view along line AA of FIG. 4B1. Therefore, FIG. 4C is depicting a slice in memory array region 411. Note that the dummy memory holes in dummy array region 412 may have substantially the same structure for at least a portion of the memory hole depicted in FIG. 4C. However, in an embodiment, the dummy memory holes are not electrically connected to the source line. The SGD layers include SGDT0, SGDT1, SGD0, and SGD1. The SGD layers may have more or fewer than four layers. The SGS layers includes SGSB0, SGSB1, SGS0, and SGS1. The SGS layers may have more or fewer than four layers. Six dummy word line layers DD0, DD1, WLIFDU, WLIDDL, DS1, and DS0 are provided, in addition to the data word line layers WL0-WL111. There may be more or fewer than 112 data word line layers and more or fewer than six dummy word line layers. Each NAND string has a drain side select gate at the SGD layers. Each NAND string has a source side select gate at the SGS layers. Also depicted are dielectric layers DL0-DL124.

Columns 432, 434 of memory cells are depicted in the multi-layer stack. The stack includes a substrate 457, an insulating film 454 on the substrate, and a portion of a source line SL. A portion of the bit line 419 is also depicted. Note that NAND string 484 is connected to the bit line 419. NAND string 484 has a source-end at a bottom of the stack and a drain-end at a top of the stack. The source-end is connected to the source line SL. A conductive via 429 (also referred to as a bit line contact) connects the drain-end of NAND string 484 to the bit line 419.

In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-WL111 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0 and DS1 connect to dummy memory cells. The term “dummy memory cell” refers to a memory cell on a NAND string in the memory array region 411. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have the same structure. Drain side select layers SGD are used to electrically connect and disconnect (or cut off) the channels of respective NAND strings from bit lines. Source side select layers SGS are used to electrically connect and disconnect (or cut off) the channels of respective NAND strings from the source line SL.

In some embodiments, the stack 435 is divided into two or more tiers. A two or other multi-tier stack can be used to form a relatively tall stack while maintaining a relatively narrow memory hole width (or diameter). After the layers of the lower tier 423 are formed, memory hole portions are formed in the lower tier 423. Subsequently, after the layers of the upper tier 421 are formed, memory hole portions are formed in the upper tier 421, aligned with the memory hole portions in the lower tier 423 to form continuous memory holes from the bottom to the top of the stack. The resulting memory hole is narrower than would be the case if the hole were etched from the top to the bottom of the stack rather than in each tier individually. An interface (IF) region is created where the two tiers are connected. The IF region is typically thicker than the other dielectric layers. Due to the presence of the IF region, the adjacent word line layers suffer from edge effects such as difficulty in programming or erasing. These adjacent word line layers can therefore be set as dummy word lines. In some embodiments, the tiers are erased independent of one another. Hence, data may be maintained in the upper tier after the lower tiers is erased. Likewise, data may be maintained in the lower tier after the upper tier is erased.

FIG. 4D depicts a view of the region 445 of FIG. 4C. FIG. 4D will be discussed with reference to a NAND string in the memory array region 411. However, an embodiment of a dummy NAND string in dummy array region 412 also has the structure depicted in FIG. 4D. Data memory cell transistors 520, 521, 522, 523, and 524 are indicated by the dashed lines. A number of layers can be deposited along the sidewall (SW) of the memory hole 432 and/or within each word line layer, e.g., using atomic layer deposition. For example, each column (e.g., the pillar which is formed by the materials within a memory hole) can include a blocking oxide/block high-k material 470, charge-trapping layer or film 463 such as SiN or other nitride, a tunneling layer 464, a polysilicon body or channel 465, and a dielectric core 466. A word line layer can include a conductive metal 462 such as Tungsten as a control gate. For example, control gates 490, 491, 492, 493 and 494 are provided. In this example, all of the layers except the metal are provided in the memory hole. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the data memory cell transistor. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a data memory cell transistor is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

Each of the memory holes can be filled with a plurality of annular layers (also referred to as memory film layers) comprising a blocking oxide layer, a charge trapping layer, a tunneling layer and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are between the core region and the WLLs in each of the memory holes. In some cases, the tunneling layer 464 can comprise multiple layers such as in an oxide-nitride-oxide configuration.

FIG. 4E1 depicts a view of the region 447 of FIG. 4C. The structure in FIG. 4E1 is for a NAND string in the memory array region 411. Source side select transistors 570, 571, 572, and 573 are indicated by the dashed lines. The layers 470, 463, 464, 465 along the sidewall (SW) of the memory hole 432 are depicted (see FIG. 4D). A select line layer can be formed from the conductive metal 462 (see FIG. 4D) such as Tungsten as a control gate to the select transistors SGSB0, SGSB1, SGS0, and SGS1, respectively. For example, control gates 590, 591, 592, and 593 are provided. In this example, all of the layers except the metal are provided in the memory hole. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

FIG. 4E1 shows a source line (SL) 542. The source line 542 is formed from a conductive material such as tungsten or silicon. The bottom portion of the channel 465 is in direct physical and electrical contact with the source line (SL). Above the source line 542 is an upper DSC (direct source contact) polysilicon region 546. Below the source line 542 is a lower DSC polysilicon region 540.

Unlike the NAND string in FIG. 4E1 in which the channel 465 is directly connected to the source line, the channel 465 of an embodiment of a dummy NAND string is separated from the source line by an insulator. Therefore, the channel 465 of this embodiment of the dummy NAND string is floating at the source end. FIG. 4E2 depicts the source end of an embodiment of a dummy memory hole. Note that the channel 465 is not in direct electrical contact with the source line (SL) due to the presence of layers 464, 463, and 470. Therefore, the channel 465 is floating at the source end of the memory hole.

FIG. 4F is a schematic diagram of a portion of the memory array 202. FIG. 4F shows physical data word lines WL0-WL111 running across the entire block. The structure of FIG. 4G corresponds to a portion 407 in Block 2 of FIG. 4A, including bit line 419. Within the physical block, in one embodiment, each bit line is connected to five NAND strings. Thus, FIG. 4F shows bit line 419 connected to NAND string NS0, NAND string NS1, NAND string NS2, and NAND string NS3.

In one embodiment, there are four sets of drain side select lines in the block. For example, the set of drain side select lines connected to NS0 include SGDT0-s0, SGDT1-s0, SGD0-s0, and SGD1-s0. The set of drain side select lines connected to NS1 include SGDT0-s1, SGDT1-s1, SGD0-s1, and SGD1-s1. The set of drain side select lines connected to NS2 include SGDT0-s2, SGDT1-s2, SGD0-s2, and SGD1-s2. The set of drain side select lines connected to NS3 include SGDT0-s3, SGDT1-s3, SGD0-s3, and SGD1-s3. Herein the term “SGD” may be used as a general term to refer to any one or more of the lines in a set of drain side select lines. In an embodiment, each line in a given set may be operated independent from the other lines in that set to allow for different voltages to the gates of the four drain side select transistors on the NAND string. Moreover, each set of drain side select lines can be selected independent of the other sets. Each set drain side select lines connects to a group of NAND strings in the block. Only one NAND string of each group is depicted in FIG. 4F. These four sets of drain side select lines correspond to four sub-blocks. A first sub-block corresponds to those vertical NAND strings controlled by SGDT0-s0, SGDT1-s0, SGD0-s0, and SGD1-s0. A second sub-block corresponds to those vertical NAND strings controlled by SGDT0-s1, SGDT1-s1, SGD0-s1, and SGD1-s1. A third sub-block corresponds to those vertical NAND strings controlled by SGDT0-s2, SGDT1-s2, SGD0-s2, and SGD1-s2. A fourth sub-block corresponds to those vertical NAND strings controlled by SGDT0-s3, SGDT1-s3, SGD0-s3, and SGD1-s3. As noted, FIG. 4F only shows the NAND strings connected to bit line 419. However, a full schematic of the block would show every bit line and five vertical NAND strings connected to each bit line.

Although the example memories of FIGS. 4-4F are three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other 3D memory structures can also be used with the technology described herein.

FIG. 5 is a diagram depicting a one layer of a portion of a block in a 3D NAND memory structure. The layer is a word line layer 601 in the 3D NAND structure. In particular, this may be one of the word line layers in an upper tier. FIG. 5 corresponds to an edge of the block and shows a small portion of the memory array region 411, the dummy array region 412, a DMH2 region 602 and an SGD region 604. There may be some additional regions referred to as a staircase structure (to the right of SGD region 604) that are not depicted in FIG. 5. The block is bounded by ST structures 402, 410. Referring back to FIG. 4B1, SGD layers may have isolation regions 404, 406, 408 within the block to divide the SGD layer into separate SGD select lines in order to operate the block as sub-blocks. However, the isolation regions 404, 406, 408 are not depicted in FIG. 5, as FIG. 5 shows a word line layer 601.

One of the memory NAND strings (or regular memory hole) 612 is referenced in the memory array region 411. The memory array region 411 extends in the y-direction as indicated by arrow 633. One of the dummy NAND strings (or dummy memory hole) 614 is referenced in the dummy array region 412. The dummy memory holes in dummy array region 412 are shaded to highlight the dummy memory holes; however, as noted above, the dummy memory holes may be fabricated to contain the same memory cell films as the memory holes in the memory array region 411. In the layer depicted in FIG. 5, the dummy memory holes in dummy array region 412 have substantially the same diameter as the memory holes in memory array region 411. However, the diameter of a memory hole typically may be layer dependent, as will be discussed below.

In the word line layer 601 depicted in FIG. 5, the dummy memory holes in DMH2 region 602 have a substantially larger diameter than the dummy memory holes in dummy array region 412. In the layer depicted in FIG. 5, the dummy memory holes in the DMH2 region 602 have an inner film region 616 that may be formed from the same memory cell films as is used for the dummy memory holes 614 and regular memory holes 612. However, the portions of the dummy memory holes in DMH2 region 602 at different word line layers do not necessarily have all of the memory cell films. The dummy memory holes in DMH2 region 602 also have an outer insulting region 618 that surrounds the inner film region 616. The outer insulting region 618 provides electrical isolation between the inner film region 616 and the word line layer 601.

In the word line layer 601 depicted in FIG. 5, the SGD holes 620 in SGD region 604 has approximately the same diameter as the dummy memory holes in DMH2 region 602. The SGD holes 620 in SGD region 604 are filled with an insulator such as silicon oxide.

The bit lines are not depicted in FIG. 5. However, bit lines extend in the x-direction above the highest layer in the stack over at least the memory array region 411 and the dummy array region 412. In an embodiment, regular bit lines extend the x-direction over the memory array region 411 and dummy bit lines extend in the x-direction over the dummy array region 412. In a further embodiment, dummy bit lines also extend in the x-direction over DMH2 region 602 and contact the inner film regions 616.

FIG. 6A is a stack 635 showing a cross-sectional view along line BB of FIG. 5. Therefore, FIG. 6A is depicting a slice in dummy array region 412. In general, the stack has one or more tiers. In this example, the stack 635 has an upper tier 721, a middle tier 722, and a lower tier 723. The diameter of the memory holes may increase going upwards in a tier. Four dummy memory holes (or dummy NAND strings) 614a, 614b, 614c, 614d are depicted. Each dummy NAND string is connected to a dummy bit line. Dummy NAND string 614a is connected to dummy bit line 417a by way of bit line contact 706a; dummy NAND string 614b is connected to dummy bit line 417b by way of bit line contact 706b; dummy NAND string 614c is connected to dummy bit line 417c by way of bit line contact 706c; and dummy NAND string 614d is connected to dummy bit line 417d by way of bit line contact 706. Each of the dummy NAND strings 614 may have memory cell films similar to the films 470, 463, 464, 465 shown in FIGS. 4D and 4E2. Note that memory cell films 470, 463, 464, 465 are just one example and that NAND strings can be formed with other memory cell film layers.

The stack 635 has alternating conductive and insulating layers. Many of the conductive layers are word line layers. One of the word line layers (WL) and one of the insulating (or dielectric) layers (D) are labeled. A source line (SL) is at the bottom of the stack 635, just below an SGS layer. In an embodiment, the dummy NAND strings 614 are floating at the source end in that the dummy NAND strings 614 are electrically isolated from the source line (SL). However, the channels (e.g., channel 465, see FIGS. 4D and 4E2) are electrically connected to the dummy bit lines 417 by way of the bit line contacts 706. In an embodiment, the dummy bit lines 417a, 417b, 417c, and 417d are electrically connected (along with other dummy bit lines). In an embodiment, the memory system applies a first voltage to the dummy bit lines 417 while applying a second voltage to one or more of the conductive layers in the stack 635 in order to stress the dummy memory holes 614. In an embodiment, the memory system senses a signal on dummy bit lines 417 while applying a voltage to one or more of the conductive layers in the stack 635 in order to determine whether there is a defect (e.g., conductive layer to dummy memory hole 614 short). For example, this could be a leakage current test.

FIG. 6B1 is a stack 635 showing a cross-sectional view along line CC of FIG. 5. Therefore, FIG. 6B1 is depicting a slice in the DMH2 region 602. The stack 635 in FIG. 6B1 shows the alternating conductive and insulating layers in the upper tier 721, middle tier 722, and lower tier 723. The diameter of the DMH2 memory holes may increase going upwards in a tier. Two DMH2 memory holes 724a, 724b are depicted. Each DMH2 memory hole has an inner film region 616 and an outer insulting region 618. The inner film region 616 has a larger diameter in the upper tier 721 than in the middle tier 722 and lower tier 723 in this example. The portion 725 of the inner film region 616 in the upper tier 721 may contain the same memory cell films as are present in the dummy NAND strings and regular NAND strings. The portion 727 of the inner film region 616 in the lower two tiers 722, 723 contains fewer than all of the memory cell films. However, at least one of the memory cell film layer may be present in the middle tier 722 and lower tier 723. Moreover memory cell film layer 727 contains a conductive film in an embodiment. Therefore, there is a possibility for an electrical short between a conductive layer and the inner film region 616. The outer insulting region 618 provides a considerable amount of protection to prevent a conductive layer (e.g., word line) from coming into electrical contact with a memory cell film layer (e.g., channel 465). However, there is still some chance of an electrical short between a conductive layer (e.g., word line) and a conductive region in the inner film region 616 (regardless of the tier).