a receives the enable signal e1 at the enable terminal AR. The secondary flip-flop 104b receives the enable signal e2 at the enable terminal AR. The secondary flip-flop 104c receives the enable signal e3 at the enable terminal AR.

Each secondary flip-flop 104 includes a clock input terminal CP. In one embodiment, each secondary flip-flop 104 receives a same clock signal at the clock input terminal CP. During standard operation the enable signal e is low (or otherwise indicates no error state) and the input data value at the data input terminal D is provided to the data output terminal Q upon the rising or falling edge (as the case may be) of the clock signal CP.

If an error state is present at a secondary flip-flop 104, then the error signal e goes high (or otherwise indicates the presence of an error state). This causes the alternate input data value di to be passed to the data output terminal Q.

In one embodiment, the alternate input data value di is passed to the data output terminal Q without regard to the state of the clock signal CP. In other words, if an error state is detected and an enable signal e goes high for a particular secondary flip-flop 104, then the error state is corrected substantially immediately without regard for the clock signal CP. This has the advantage of ensuring that errors do not accumulate among the secondary flip-flops 104 even for low power devices in which the frequency of the clock signal CP is very low.

The main flip-flop 102 includes an error detection circuit one. The error detection circuit one includes a first 104aOR gate 114. A first input of the first 104aOR gate 114 is coupled to the data output terminal Q of the secondary flip-flop 104a and receives the output data value q1. A second input of the 104aOR gate 114 is coupled to the data output terminal Q of the secondary flip-flop 104b and receives the output data value q2.

The error detection circuit one includes a second 104aOR gate 116. A first input of the 104aOR gate 116 is coupled to the data output terminal Q of the secondary flip-flop 104c and receives the output data value q3. A second input of the second 104aOR gate 116 is coupled to the data output terminal Q of the secondary flip-flop 104b and receives the output data value q2.

The error detection circuit one includes an and gate 118, an and gate 120, and an and gate 122. The output of the 104aOR gate 114 is provided to a first input terminal of each of the and gates 118, 120, and 122. The first terminal of the and gate 118 inverts the value of the output of the 104aOR gate 114 or receives an inverted value of the output of the 104aOR gate 114. The output of the 104aOR gate 116 is provided to a second input terminal of each of the and gates 118, 120, and 122. The second input terminal of the and gate 122 inverts the output value of the 104aOR gate 116 or receives an inverted value of the output of the 104aOR gate 116.

The output of the and gate 118 is the enable signal e3. The output of the and gate 118 is coupled to the enable terminal AR of the secondary flip-flop 104c and provides the enable signal e3 to the enable signal AR of the secondary flip-flop 104c. Accordingly, the output of the and gate 118 indicates whether or not an error state is present at the secondary flip-flop 104c. The enable signal e3 will go high if the data value q3 is different than both of the data values q1 and q2.

The output of the and gate 120 is the enable signal e2. The output of the and gate 120 is coupled to the enable terminal AR of the secondary flip-flop 104b and provides the enable signal e2 to the enable signal AR of the secondary flip-flop 104b. Accordingly, the output of the and gate 120 indicates whether or not an error state is present at the secondary flip-flop 104c. The enable signal e2 will go high if the data value q2 is different than both of the data values q1 and q3.

The output of the and gate 122 is the enable signal e1. The output of the and gate 120 is coupled to the enable terminal AR of the secondary flip-flop 104a and provides the enable signal e1 to the enable signal AR of the secondary flip-flop 104a. Accordingly, the output of the and gate 122 indicates whether or not an error state is present at the secondary flip-flop 104a. The enable signal e1 will go high if the data value q1 is different than both of the data values q2 and q3. Other configurations of an error detection circuit one can be utilized without departing from the scope of the present disclosure.

The main flip-flop 102 includes an output circuit 106. The output circuit 106 includes a comparison circuit 110. The comparison circuit 110 includes a first input coupled to the data output terminal Q of the secondary flip-flop 104a and receives the data value q1. The comparison circuit 110 includes a second input coupled to the data output terminal Q of the secondary flip-flop 104b and receives the data value q2.

The output circuit 106 includes an inverter 112. The input of the inverter 112 is coupled to the output of the comparison circuit 110. The output of the inverter 112 is coupled to the main data output terminal QM of the main flip-flop 102. In other words, the output of the inverter 112 provides the output data value to the main the data output terminal QM. The function of the comparison circuit 110 in accordance with one embodiment, is described in relation to FIG. 3.

FIG. 3 is a schematic diagram of a comparison circuit 110, in accordance with one embodiment. FIG. 3 also provides a logic table 300 associated with the comparison circuit 110. The comparison circuit 110 includes a first input In1 (e.g., receiving the data value q1), a second input In2 (e.g., receiving the data value q2), and an output terminal OUT. The comparison circuit 110 includes PMOS transistors P1 and P2 coupled in series between supply voltage VDD and the output OUT. The comparison circuit 110 includes NMOS transistors coupled in series between OUT and ground. The gate terminals of the transistors P1 and N2 are coupled to IN2. The gate terminals of the transistors P2 and N1 are coupled to IN1.

The logic table 300 indicates the function of the comparison circuit 110. If the inputs IN1 and IN2 are both 0, then the output OUT can change to 1 or can remain at 1 if the value of OUT was already 1. If the inputs IN1 and IN2 are both 1, then the output OUT can change to 0 or can remain at 0 if the value of OUTPUT was already 0. If the inputs IN1 and IN2 are not identical to each other, then the output OUT or remain at its previous value. In other words, the output of the comparison circuit 110 can only change if the values of IN1 and IN2 agree with each other. The output of the output circuit 106 will be the opposite of the output of the comparison circuit 110 due to the presence of the inverter 112 (see FIG. 2). Other configurations of a comparison circuit 110 can be utilized without departing from the scope of the present disclosure.

FIG. 4 is a schematic diagram of a secondary flip-flop 104, according to one embodiment. The secondary flip-flop 104 of FIG. 4 is one example of a secondary flip-flop 104 of FIG. 1 or 2. The secondary flip-flop 104 of FIG. 4 will provide the alternate input data value di from the alternate data input terminal DiQ to the data output terminal Q without regard to the state of the clock signal CP. In other words, when the enable signal at the enable terminal AR goes high, the alternate input data value di will be passed substantially immediately to the data output terminal Q.

The secondary flip-flop 104 includes a multiplexer 130. The multiplexer 130 includes a first input coupled to the data input terminal D. The multiplexer 130 includes a second input coupled to the alternate data input terminal DiQ. The multiplexer 130 includes a selection input coupled to the enable terminal AR. Accordingly, the selection input receives the enable signal e. If the enable signal is 0, then the multiplexer 130 outputs the input data value from the data input terminal D. If the enable signal is 1, then the multiplexer 130 outputs the alternate input data value from the alternate data input terminal DiQ.

The secondary flip-flop 104 includes an inverter 132. The input of the inverter 132 is coupled to the enable signal AR and outputs a complementary enable signal ARN that is the logical complement of the enable signal at AR.

The secondary flip-flop 104 includes a pair of inverters 134 136 connected in series. The input of the inverter 134 receives the clock signal CP and outputs the complementary clock signal CPN that is the logical complement of the clock signal CP. The input of the inverter 136 receives the complementary clock signal CPN and outputs the clock signal CPI that is the logical complement of CPN. Accordingly, CPI corresponds to the clock signal CP, but possibly with a slight delay.

The secondary flip-flop 104 includes a first latch 137. The first latch 137 corresponds to a master latch of the flip-flop 104. The first latch 137 includes a first inverter 138 and a second inverter 140 cross coupled together. The output of the inverter 138 is the output of the first latch 137.

The secondary flip-flop 104 includes a second latch 141. The second latch 141 corresponds to a slave latch of the flip-flop 104. The second latch 141 includes a first inverter 142 and a second inverter 144 cross coupled together. The output of the inverter 142 corresponds to the output of the second latch 141 and to the data output terminal Q of the secondary flip-flop 104.

The secondary flip-flop 104 includes a pass gate 150 coupled between the output of the multiplexer 130 and the input of the inverter 138. The pass gate 150 receives the clock signals CPI and CPN and is therefore controlled by the clock signals CPI and CPN. When CPI is low, the pass gate 150 is enabled. When CPI is high, the pass gate 150 is disabled.

The secondary flip-flop 104 includes an alternate loop 146 that bypasses the pass gate 150. The alternate loop 146 includes a pass gate 152. The pass gate 152 receives the signals ARN and AR and is therefore controlled by ARN and AR. The pass gate 152 is enabled when AR is high.

The secondary flip-flop 104 includes a pass gate 158 coupled between the output of the inverter 137 and the input of the inverter 142. The pass gate 158 receives the clock signals CPI and CPN. When CPI is high, the pass gate 158 is enabled. When CPI is low, the pass gate 158 is disabled.

The secondary flip-flop 104 includes an alternate loop 148 that bypasses the pass gate 158. The alternate loop 148 includes a pass gate 160. The pass gate 160 receives the signals ARN and AR. The pass gate 152 is enabled when AR is high.

The secondary flip-flop includes a pass gate 154 and a pass gate 156 coupled in series between the output of the inverter 140 and the input of the inverter 138. The pass gate 154 receives AR and ARN as control signals. The pass gate 154 is enabled when AR is low and is disabled when AR is high. The pass gate 156 receives CPN and CPI as control signals. The pass gate 156 is enabled when CPI is high and is disabled when CPI is low.

The secondary flip-flop includes a pass gate 162 and a pass gate 164 coupled in series between the output of the inverter 143 and the input of the inverter 142. The pass gate 162 receives AR and ARN as control signals. The pass gate 162 is enabled when AR is low and is disabled when AR is high. The pass gate 164 receives CPN and CPI as control signals. The pass gate 164 is enabled when CPI is low and is disabled when CPI is high.

The function of the secondary flip-flop 104 will now be described. The enable signal AR determines whether the secondary flip-flop 104 will operate in a standard operating mode or whether the secondary flip-flop 104 will operate in alternate operating mode. In the standard operating mode, the input data value at the data input terminal D is provided from the multiplexer 130 and the clock signal CP controls the operation of the secondary flip-flop 104. In the alternate operating mode, the alternate input data value from the alternate data input terminal DiQ is output from the multiplexer 130 and the clock signal CP does not control the function of the secondary flip-flop 104.

In the standard operating mode AR is low and ARN is high. This causes the pass gates 152 and 160 to be disabled, thereby disabling the alternate loops 146 and 148. In the standard operating mode, the pass gates 154 and 162 are enabled. When CPI is low, the pass gate 150 is enabled in the data value is provided from D to the first latch 137. The pass gate 156 is disabled. Accordingly, the complement of the input data value from the data input terminal D is provided at the output of the first latch 137. The pass gate 158 is disabled, preventing the inverse data value at the output of the first latch 137 from being passed to the input of the second latch 141.

In the standard operating mode, upon the clock signal CPI going high, the pass gate 150 is disabled and the pass gate 158 is enabled. The result is that the inverse data value at the output of the latch 137 is provided to the input of the latch 141. The inverter 142 inverts the output of the latch 137 and provides the input data value at the data output terminal Q. Furthermore, the pass gate 164 is disabled and the pass gate