1 may be variously changed in order to adjust the duty cycle offset and/or variance in the duty cycle of the duty adjustment circuit 310. The delay circuit 313 may include an odd number of inverters. As the number of inverters that constitute the delay circuit 313 is increased, the duty cycle offset and/or amount of change in the duty cycle of the duty adjustment circuit 310 may be increased. As the number of inverters that constitute the delay circuit 313 is decreased, the duty cycle offset and/or amount of change in the duty cycle of the duty adjustment circuit 310 may be decreased.

The first NAND gate 314 may receive the output signal of the inverter 311 and the output signal of the delay circuit 313. The second NAND gate 315 may receive the output signal of the first buffer 312 and the output signal of the first NAND gate 314. The second buffer 316 may receive the output signal of the second NAND gate 315, and may generate the second signal OS by buffering the output signal of the second NAND gate 315. The second buffer 316 may include an even number of inverters.

FIG. 3B is a timing diagram illustrating an operation of the duty adjustment circuit 310 illustrated in FIG. 3A. When the logic level of the input signal IN is changed from a low logic level to a high logic level, the logic level of the output signal of the second NAND gate 315 may be directly changed from a low logic level to a high logic level. In contrast, when the logic level of the input signal IN is changed from a high logic level to a low logic level, the output signal of the second NAND gate 315 may be delayed by the first delay time tD1, and the logic level of the output signal of the second NAND gate 315 may be changed from a high logic level to a low logic level. As illustrated in FIG. 3B, the duty adjustment circuit 310 may generate the second signal OS having a high level interval, which has been increased more than the input signal IN indicated by a dotted line by the first delay time tD1. The second signal OS may have a greater duty cycle than the input signal IN.

FIG. 3C is a diagram illustrating a configuration of a duty adjustment circuit 330 according to an embodiment. The duty adjustment circuit 330 may be applied as the duty adjustment circuit 220 of FIG. 2. Referring to FIG. 3C, the duty adjustment circuit 330 may receive the input signal IN and generate the second signal OS by adjusting the duty cycle of the input signal IN. The duty adjustment circuit 330 may generate the second signal OS having a smaller duty cycle than the input signal IN by reducing the duty cycle of the input signal IN.

The duty adjustment circuit 330 may include an inverter 331, a first buffer 332, a delay circuit 333, a first NOR gate 334, a second NOR gate 335, and a second buffer 336. The inverter 331 may receive the input signal IN and invert the input signal IN. The first buffer 332 may receive the output signal of the first inverter 331 and buffer the output signal of the inverter 331. The first buffer 332 may include an even number of inverters. The delay circuit 333 may receive the output signal of the inverter 331 and delay the output signal of the inverter 331 by a second delay time tD2. The second delay time tD2 may be variously changed to adjust the duty cycle offset and/or amount of change in the duty cycle of the duty adjustment circuit 330. The delay circuit 333 may include an odd number of inverters. As the number of inverters that constitute the delay circuit 333 is increased, the duty cycle offset and/or amount of change in the duty cycle of the duty adjustment circuit 330 may be increased. As the number of inverters that constitute the delay circuit 333 is decreased, the duty cycle offset and/or amount of change in the duty cycle of the duty adjustment circuit 330 may be decreased.

The first NOR gate 334 may receive the output signal of the inverter 331 and the output signal of the delay circuit 333. The second NOR gate 335 may receive the output signal of the first buffer 332 and the output signal of the first NOR gate 334. The second buffer 336 may receive the output signal of the second NOR gate 335, and may generate the second signal OS by buffering the output signal of the second NOR gate 335. The second buffer 336 may include an even number of inverters.

FIG. 3D is a timing diagram illustrating an operation of the duty adjustment circuit 330 illustrated in FIG. 3C. When the logic level of the input signal IN is changed from a high logic level to a low logic level, the logic level of the output signal of the second NOR gate 335 may be directly changed from a high logic level to a low logic level. In contrast, when the logic level of the input signal IN is changed from a low logic level to a high logic level, the output signal of the second NOR gate 335 may be delayed by the second delay time tD2, and the logic level of the output signal of the second NOR gate 335 may be changed from a low logic level to a high logic level. As illustrated in FIG. 3D, the duty adjustment circuit 330 may generate the second signal OS having a high level interval, which has been decreased more than the input signal IN indicated by a dotted line by the second delay time tD2, or the second signal OS having a low level interval, which has been increased more than the input signal IN by the second delay time tD2. The second signal OS may have a smaller duty cycle than the input signal IN.

FIG. 4 is a diagram illustrating a configuration of a reception circuit 400 according to an embodiment. The reception circuit 400 may be applied as the reception circuit 120 illustrated in FIG. 1. Referring to FIG. 4, the reception circuit 400 may include a first level shifter 410, a second level shifter 420, a mixing circuit 430, and a reception selection circuit 440. The first and second level shifters 410 and 420 may constitute a plurality of level shifters included in the level shifting circuit 121 of FIG. 1. The first level shifter 410 may be coupled to the signal transmission line 101, and may receive the transmission signal TS. The first level shifter 410 may generate a first shifted signal LS1 by changing the voltage level of the transmission signal TS. The first level shifter 410 may convert the transmission signal TS having the first power domain to the first shifted signal LS1 having the second power domain. The second level shifter 420 may be coupled to the signal transmission line 101, and may receive the transmission signal TS. The second level shifter 420 may generate a second shifted signal LS2 by changing the voltage level of the transmission signal TS. The second level shifter 420 may convert the transmission signal TS having the first power domain to the second shifted signal LS2 having the second power domain. The first level shifter 410 and the second level shifter 420 may have different duty cycle offsets.

In an embodiment, the direction of a change in the duty cycle of the first level shifter 410 may be opposite to the direction of a change in the duty cycle of the second level shifter 420. For example, when the first level shifter 410 increases the duty cycle of the transmission signal TS, the second level shifter 420 may decrease the duty cycle of the transmission signal TS. The first level shifter 410 may generate the first shifted signal LS1 having a greater duty cycle than the transmission signal TS by increasing the high level interval of the transmission signal TS. The second level shifter 420 may generate the second shifted signal LS2 having a smaller duty cycle than the transmission signal TS by increasing the low level interval of the transmission signal TS. To the contrary, when the first level shifter 410 decreases the duty cycle of the transmission signal TS, the second level shifter 420 may increase the duty cycle of the transmission signal TS. The first level shifter 410 may generate the first shifted signal LS1 having a smaller duty cycle than the transmission signal TS by increasing the low level interval of the transmission signal TS. The second level shifter 420 may generate the second shifted signal LS2 having a greater duty cycle than the transmission signal TS by increasing the high level interval of the transmission signal TS. In this case, an amount of change in the duty cycle of the first level shifter 410 may be substantially the same as or different from an amount of change in the duty cycle of the second level shifter 420.

In an embodiment, the direction of a change in the duty cycle of the first level shifter 410 may be the same as the direction of a change in the duty cycle of the second level shifter 420. For example, both the first and second level shifters 410 and 420 may increase the duty cycle of the transmission signal TS or may decrease the duty cycle of the transmission signal TS. The first and second level shifters 410 and 420 may generate the first and second shifted signals LS1 and LS2, respectively, each one having a greater duty cycle than the transmission signal TS, by increasing the high level interval of the transmission signal TS. To the contrary, the first and second level shifters 410 and 420 may generate the first and second shifted signals LS1 and LS2, respectively, each one having a smaller duty cycle than the transmission signal TS, by increasing the low level interval of the transmission signal TS. In this case, an amount of change in the duty cycle of the first level shifter 410 may be different from an amount of change in the duty cycle of the second level shifter 420. For example, an amount of change in the duty cycle of the first level shifter 410 may be greater than an amount of change in the duty cycle of the second level shifter 420. To the contrary, an amount of change in the duty cycle of the second level shifter 420 may be greater than an amount of change in the duty cycle of the first level shifter 410.

The mixing circuit 430 may mix the duty cycle offset of the first level shifter 410 and the duty cycle offset of the second level shifter 420. The mixing circuit 430 may additionally adjust the duty cycle offset of the reception circuit 400 by mixing the duty cycle offsets of the first and second level shifters 410 and 420. The mixing circuit 430 may receive the first and second shifted signals LS1 and LS2 from the first and second level shifters 410 and 420, respectively. The mixing circuit 430 may generate a mixed signal MS by mixing the first and second shifted signals LS1 and LS2. The mixing circuit 430 may generate the mixed signal MS having a duty cycle between the duty cycle of the first shifted signal LS1 and the duty cycle of the second shifted signal LS2 by mixing the first and second shifted signals LS1 and LS2. For example, the mixing circuit 430 may mix the first shifted signal LS1 and the second shifted signal LS2 at a ratio of 1 to 1. The mixed signal MS may have a duty cycle corresponding to the middle of the duty cycles of the first and second shifted signals LS1 and LS2. In an embodiment, the mixing circuit 430 may mix the first and second shifted signals LS1 and LS2 at a ratio different from the ratio of 1 to 1. To variously adjust the duty cycle offset of the reception circuit 400, the mixing ratio of the mixing circuit 430 may also be variously changed.

The reception selection circuit 440 may receive the mixed signal MS from the mixing circuit 430 and receive the second shifted signal LS2 from the second level shifter 420. The reception selection circuit 440 may receive a reception control signal RSEL. The reception selection circuit 440 may output one of the mixed signal MS and the second shifted signal LS2 as an output signal OUT based on the reception control signal RSEL. The logic level of the reception control signal RSEL may be changed by considering the duty cycle offsets of the transmission circuit 110 and the reception circuit 400 so that the duty cycle offsets of the transmission circuit 110 of FIG. 1 and the reception circuit 400 can be canceled. For example, when the reception control signal RSEL has a first logic level, the reception selection circuit 440 may output the second shifted signal LS2 as the output signal OUT. When the reception control signal RSEL has a second logic level, the reception selection circuit 440 may output the mixed signal MS as the output signal OUT.

FIG. 5A is a diagram illustrating a configuration of a level shifter 510 according to an embodiment. The level shifter 510 may be applied as at least one of the first level shifter 410 and the second level shifter 420 in FIG. 4. When the level shifter 510 is applied as the first level shifter 410, the level shifter 510 may generate the first shifted signal LS1 and a complementary signal LS1B by receiving the transmission signal TS. The level shifter 510 may convert the transmission signal TS having the first power domain to the first shifted signal LS1 having the second power domain. The level shifter 510 may include an inverter 511, a first transistor 512, a second transistor 513, a third transistor 514, and a fourth transistor 515. The inverter 511 may receive the transmission signal TS and invert the transmission signal TS. The inverter 511 may receive the first high power supply voltage VDD1. The inverter 511 may invert and drive the transmission signal TS between the first high power supply voltage VDD1 and the low power supply voltage VDDL. The first and second transistors 512 and 513 may each be an N channel MOS transistor. The gate of the first transistor 512 may receive the first transmission signal TS. The drain of the first transistor 512 may be coupled to a negative output node ON. The source of the first transistor 512 may be coupled to a terminal to which the low power supply voltage VDDL is supplied. The complementary signal LS1B may be output from the negative output node ON. The gate of the second transistor 513 may receive the output signal of the inverter 511. The drain of the second transistor 513 may be coupled to a positive output node OP. The source of the second transistor 513 may be coupled to a terminal to which the low power supply voltage VDDL is supplied. The first shifted signal LS1 may be output from the positive output node OP. The third and fourth transistors 514 and 515 may each be a P channel MOS transistor. The gate of the third transistor 514 may be coupled to the positive output node OP. The source of the third transistor 514 may receive the second high power supply voltage VDD2. The drain of the third transistor 514 may be coupled to the negative output node ON. The gate of the fourth transistor 515 may be coupled to the negative output node ON. The source of the fourth transistor 515 may receive the second high power supply voltage VDD2. The drain of the fourth transistor 515 may be coupled to the positive output node OP. The duty cycle offset of the level shifter 510 may be variously changed depending on the voltage levels of the first and second high power supply voltages VDD1 and VDD2 and the sizes of the first to fourth transistors 512, 513, 514, and 515. The size of the transistor may be a ratio of the channel width to channel length of the transistor. Each of the first and second level shifters 410 and 420 in FIG. 4 may have substantially the same configuration as the level shifter 510. However, the size of a transistor that constitutes the first level shifter 410 may be different from the size of a transistor that constitutes the second level shifter 420 so that the first and second level shifters 410 and 420 have different duty cycle offsets.

FIG. 5B is a diagram illustrating a configuration of a level shifter 520 according to an embodiment. The level shifter 520 may be applied as at least one of the first and second level shifters 410 and 420 in FIG. 4. When the level shifter 520 is applied as the first level shifter 410, the level shifter 520 may generate the first shifted signal LS1 by receiving the transmission signal TS. The level shifter 520 may convert the transmission signal TS having the first power domain to the first shifted signal LS1 having the second power domain. The level shifter 520 may include a first inverter 521, a second inverter 522, a third inverter 523, and a fourth inverter 524. The first inverter 521 may receive the first high power supply voltage VDD1. The second to fourth inverters 522, 523, and 524 may receive the second high power supply voltage VDD2. The first inverter 521 may receive the transmission signal TS, and may invert and drive the transmission signal TS. The output signal of the first inverter 521 may have a voltage level between the first high power supply voltage VDD1 and the low power supply voltage VDDL. The second inverter 522 may receive the output signal of the first inverter 521, and may invert and drive the output signal of the first inverter 521. The output signal of the second inverter 522 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The third inverter 523 may receive the transmission signal TS, and may invert and drive the transmission signal TS. The output signal of the third inverter 523 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The fourth inverter 524 may receive the output signal of the third inverter 523, and may invert and drive the output signal of the third inverter 523. The output signal of the fourth inverter 524 may have a voltage level between the second high power supply voltage VDD2 and the low power supply voltage VDDL. The output signals of the third inverter 523 and the fourth inverter 524 may be mixed in an output node 525. The first shifted signal LS1 may be output through the output node 525. The duty cycle offset of the level shifter 520 may be variously changed depending on the voltage levels of the first and second high power supply voltages VDD1 and VDD2 and the size of a transistor that constitutes the first to fourth inverters 521, 522, 523, and 524. The first and second level shifters 410 and 420 in FIG. 4 may have substantially the same configuration as the level shifter 520. However, the size of a transistor that constitutes the first level shifter 410 may be different from the size of a transistor that constitutes the second level shifter 420 so that the first and second level shifters 410 and 420 may have different duty cycle offsets.

FIG. 6 is a diagram illustrating a configuration of the mixing circuit 430 illustrated in FIG. 4. Referring to FIG. 6, the mixing circuit 430 may include a first buffer 610, a second buffer 620, a first resistor 631, a second resistor 632, a capacitor 633, and a third buffer 640. The first buffer 610 may receive the first shifted signal LS1 from the first level shifter 410, and may buffer the first shifted signal LS1. The second buffer 620 may receive the second shifted signal LS2 from the second level shifter 420, and may buffer the second shifted signal LS2. The first resistor 631 may be coupled between the first buffer 610 and a mixing node MN. One end of the first resistor 631 may receive the output signal of the first buffer 610. The other end of the first resistor 631 may be coupled to the mixing node MN. The second resistor 632 may be coupled between the second buffer 620 and the mixing node MN. One end of the second resistor 632 may receive the output signal of the second buffer 620. The other end of the second resistor 632 may be coupled to the mixing node MN. The capacitor 633 may be coupled to the mixing node MN. One end of the capacitor 633 may be coupled to the mixing node MN. The other end of the capacitor 633 may be coupled to a terminal to which the low power supply voltage VDDL is supplied. The output signals of the first and second buffers 610 and 620 may be mixed at the mixing node MN through the first and second resistors 631 and 632. For example, the current driving force of the first buffer 610 may be substantially the same as the current driving force of the second buffer 620. The resistance value of the first resistor 631 may be substantially the same as the resistance value of the second resistor 632. The first and second shifted signals LS1 and LS2 may be mixed at the ratio of 1 to 1 at the mixing node MN. If the current driving forces of the first and second buffers 610 and 620 and/or the resistance values of the first and second resistors 631 and 632 are differently adjusted, the first and second shifted signals LS1 and LS2 may be mixed at a ratio not the ratio of 1 to 1 at the mixing node MN.

An operation of the transmission and reception system 100 according to an embodiment may be described as follows with reference to FIGS. 1, 2, and 4. When the duty cycle offsets of the transmission circuits