FIG. 4, the current mirror includes a first secondary mirror transistor 404 and a second secondary mirror transistor 406 having first terminals 404a, 406a coupled to the first voltage supply terminal 106, having second terminals 404b, 406b coupled to the first terminals 112a, 114a of the first and second test transistors 112, 114, and having control terminals 404c, 406c coupled to the control terminal 402c of the primary mirror transistor 402.

Each mirror transistor is configured to pass the source current. For example, the primary mirror transistor 402 passes the source current between terminal 402a and terminal 402b. In response, the first secondary mirror transistor 404 passes a first current, which is approximately equal to the source current, between terminal 404a and terminal 404b. Likewise, in response to the primary mirror transistor 402 passing the source current, the second secondary mirror transistor 406 passes a second current, which is approximately equal to the source current, between terminal 406a and terminal 406b. Because the second terminals of the secondary mirror transistors are coupled together, the current supply circuit 104 outputs a supply current at terminal 104c that is approximately equal to the product of the source current multiplied by the number of secondary mirror transistors. For example, in the embodiment illustrated in FIG. 4, the current supply circuit 104 outputs (at terminal 104c) a supply current that is approximately equal to twice the source current. In some embodiments, the number of secondary mirror transistors is equal to the number of test transistors.

The ring oscillator circuit 120 includes an inverter chain 408 comprising an odd-numbered plurality of inverters coupled in series between an input terminal 408a of the first inverter chain 408 and an output terminal 408b of the first inverter chain 408. For example, the inverter chain 408 includes a first inverter (not labeled) having an input coupled to input terminal 408a, a second inverter (not labeled) having an input coupled to an output of the first inverter (not labeled), and a third inverter (not labeled) having an input coupled to an output of the second inverter (not labeled) and having an output coupled to output terminal 408b. The output terminal 408b of the inverter chain 408 is coupled to the input terminal 408a of the inverter chain 408, thereby forming the “ring” of the ring oscillator circuit 120. Although three inverters are shown in inverter chain 408 illustrated in FIG. 4, it will be appreciated that in some other embodiments, the inverter chain 408 could alternatively comprise some other odd number of inverters (e.g., 5 inverters, 7 inverters, etc.).

The inverter chain 408 generates an oscillating signal (the first oscillating signal). More particularly, because the inverter chain 408 includes an odd number of inverters, the signal at output terminal 408b is inverted relative to the signal at input terminal 408a. Because output terminal 408b is coupled to input terminal 408a, the signal output at output terminal 408b oscillates periodically.

Each inverter in the inverter chain 408 introduces a delay. As a result, a delay exists between the time an input signal is input at input terminal 408a and an output signal is output at output terminal 408b. The total delay is based on the number of inverters in the inverter chain 408 and the period of the periodic oscillating signal at output terminal 408b (the first oscillating signal) is based on the total delay. The ring oscillator circuit 120 outputs this oscillating signal (the first oscillating signal) to the control terminal 112c of the first test transistor 112 through terminal 120a.

The ring oscillator circuit 120 further includes an inverter 410. Inverter 410 has an input 410a coupled to the output terminal 408b of the inverter chain 408. Inverter 410 has an output 410b coupled to the control terminal 114c of the second test transistor 114 through terminal 120b. Inverter 410 inverts the oscillating signal at output 408b, thereby forming an inverted oscillating signal (the second oscillating signal), and outputs the inverted oscillating signal to the control terminal 114c of the second test transistor 114 through terminal 120b. Thus, the ring oscillator circuit 120 outputs complementary oscillating signals to the control terminals of the first and second test transistors 112, 114 through terminals 120a, 120b, respectively. As a result, the test transistors switch (e.g., transition between an “on” state and an “off” state) in a complementary manner. For example, when the first test transistor 112 is on, the second test transistor 114 is off, and vice versa.

In some cases, because the number of inverters between terminal 120a and terminal 120b is substantially less than the number of inverters in the inverter chain 408, the delay between the first oscillating signal and the second oscillating signal may be negligible.

In the embodiment illustrated in FIG. 4, the current through each test transistor is approximately two times the source current. This is because there are two secondary mirror transistors and thus the supply current is approximately two times the source current, but only one of the two test transistors is on at a time, so each test transistor passes the supply current at separate times.

In some embodiments, the mirror transistors (e.g., transistors 402, 404, 406) are P-channel transistors. The mirror transistors may, for example, be or comprise MOSFETs, BJTs, junction field effect transistors, fin field effect transistors, gate all-around field effect transistors, or some other suitable transistors.

FIG. 5 illustrates a timing diagram 500 corresponding to some embodiments of the system of FIG. 4.

Signal 502 illustrates the source current I_SRCgenerated by current source 102 over time (e.g., as measured by measurement circuit 128 at terminal 128b). In some embodiments, the source current I_SRCis approximately constant over time.

Signal 504 illustrates the voltage V_INat the first voltage supply terminal 106 over time (e.g., as measured by measurement circuit 128 at terminal 128c). The voltage V_INat the first voltage supply terminal 106 is approximately constant over time.

Signal 506 illustrates the voltage V_OUTat the third terminal 104c of the current supply circuit 104 over time (e.g., as measured by measurement circuit 128 at terminal 128a). The voltage V_OUTat terminal 104c is approximately constant over time.

Signal 508 illustrates the voltage V_C1at the control terminal 112c of the first test transistor 112 over time (e.g., as measured by measurement circuit 128 at terminal 128e). As discussed with regard to FIG. 2, the voltage V_C1at the control terminal 112c of the first test transistor 112 oscillates between a first voltage state and a second voltage state.

Signal 510 illustrates the current I₁through the first terminal 112a of the first test transistor 112 over time. In response to the voltage at 112c reaching the second voltage state (the “high” voltage state), current flows through the first test transistor 112 between the first terminal 112a and the second terminal 112b. As discussed with regard to FIG. 4, in the embodiment illustrated in FIG. 4, the current I₁through the first test transistor 112 is approximately two times the source current.

Signal 512 illustrates the voltage V_C2at the control terminal 114c of the second test transistor 114 over time (e.g., as measured by measurement circuit 128 at terminal 128f). As discussed with regard to FIG. 2, the voltage V_C2at the control terminal 114c of the second test transistor 114 oscillates between a first voltage state and a second voltage state (complementary to the voltage at control terminal 112c).

Signal 514 illustrates the current I₂through the first terminal 114a of the second test transistor 114 over time. In response to the voltage at 114c reaching the second voltage state (the “high” voltage state), current flows through the second test transistor 114 between the first terminal 114a and the second terminal 114b. As discussed with regard to FIG. 4, the current I₂through the second test transistor 114 is approximately two times the source current.

FIG. 6 illustrates a flow diagram 600 of some embodiments of the operation of the ring oscillator 120 of FIG. 4. While flow diagram 600 of FIG. 6 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At block 602, an output of an inverter chain is provided to an input of the inverter chain to generate a first oscillating signal at the output of the inverter chain. For example, output terminal 408b is coupled to input terminal 408a of inverter chain 408. Thus, the output of inverter chain 408 is provided to the input of inverter chain 408. As a result, the output of inverter chain 408 oscillates, thereby forming a first oscillating signal at output terminal 408b.

At block 604, the first oscillating signal is provided from the output of the inverter chain to the control terminal of the first test transistor. For example, the inverter chain 408 provides the first oscillating signal from output terminal 408b to the control terminal 112c of the first test transistor 112 through terminal 120a of the ring oscillator circuit 120.

At block 606, the output of the inverter chain is provided to an inverter to invert the first oscillating signal inverted to generate a second oscillating signal. For example, output terminal 408b of inverter chain 408 is coupled to input terminal 410a of inverter 410. Thus, the output of the inverter chain 408 is provided to the inverter 410. As a result, inverter 410 receives the first oscillating signal at input terminal 410a and inverts the first oscillating signal, thereby forming the second oscillating signal at output terminal 410b.

At block 608, the second oscillating signal is provided from the output of the inverter to the control terminal of the second test transistor. For example, inverter 410 provides the second oscillating signal from output terminal 410b to the control terminal 114c of the second test transistor 114 through terminal 120b of the ring oscillator circuit 120.

FIG. 7 illustrates a circuit diagram 700 of some embodiments of the system of FIG. 4, further comprising a third test transistor 702 and a fourth test transistor 704.

The third test transistor 702 and the fourth test transistor 704 have first terminals 702a, 704a coupled to terminal 104c of the current supply circuit 104 and have second terminals 702b, 704b coupled to the second voltage supply terminal 118. The ring oscillator circuit 120 has a third terminal 120c coupled to a control terminal 702c of the third test transistor 702. The ring oscillator circuit 120 has fourth terminal 120d coupled to a control terminal 704c of the fourth test transistor 704. The measurement circuit 128 has a terminal 128g coupled to the control terminal 702c of the third test transistor 702 and has a terminal 128h coupled to the control terminal 704c of the fourth test transistor 704.

Output terminal 408b of inverter chain 408 is coupled to the control terminal of each odd-numbered test transistor. Further, output terminal 410b of inverter 410 is coupled to the control terminal of each even-numbered test transistor. For example, output terminal 408b of inverter chain 408 is coupled to the control terminal 112c of the first test transistor 112 and to the control terminal 702c of the third test transistor 702. Further, output terminal 410b of inverter 410 is coupled to the control terminal 114c of the second test transistor 114 and to the control terminal 704c of the fourth test transistor 704. Thus, the oscillating signal provided to the control terminal of each even-numbered test transistor is inverted relative to the oscillating signal provided to the control terminal of each odd-numbered test transistor. As a result, the even-numbered test transistors and the odd-numbered test transistors switch (e.g., transition between an “on” state and an “off” state, and vice versa) in a complementary manner. For example, when the first test transistor 112 and the third test transistor 702 are on, the second test transistor 114 and the fourth test transistor 704 are off, and vice versa.

Because the odd-numbered and even-numbered test transistors switch in a complementary manner, the odd-numbered test transistors (e.g., the first test transistor 112 and the third test transistor 702) and the even-numbered test transistors (e.g., the second test transistor 114 and the fourth test transistor 704) can differ from one another. For example, in some embodiments, the odd numbered test transistors (e.g., the first test transistor 112) are a first type of transistor (e.g., having a first size and/or design) and the even-numbered test transistors (e.g., the second test transistor 114) are a second type of transistor (e.g., having a second size and/or design), different than the first type.

In some embodiments, as shown in FIG. 7, the current mirror of the current supply circuit 104 further includes a third secondary mirror transistor 706 and a fourth secondary mirror transistor 708 having first terminals 706a, 708a coupled to the first voltage supply terminal 106, having second terminals 706b, 708b coupled to the first terminals 112a, 114a, 702a, 704a of the test transistors 112, 114, 702, 704, and having control terminals 706c, 708c coupled to the control terminal 402c of the primary mirror transistor 402.

Similar to the first secondary mirror transistor 404 and the second secondary mirror transistor 406, the third secondary mirror transistor 706 passes a third current, which is approximately equal to the source current, between terminal 706a and terminal 706b in response to the primary mirror transistor 402 passing the source current. Likewise, the fourth secondary mirror transistor 708 passes a fourth current, which is approximately equal to the source current, between terminal 708a and terminal 708b in response to the primary mirror transistor 402 passing the source current. In the embodiment illustrated in FIG. 5, the current supply circuit 104 outputs (at terminal 104c) a supply current that is approximately equal to four times the source current.

In some embodiments, the system further includes a current sensor 714 coupled to the current source 102. In such embodiments, the second terminal 128b of the measurement circuit 128 is coupled to the current source 102 by the current sensor 714. In some embodiments, the current sensor 714 is coupled between the second terminal 102b of the current source 102 and ground 150. For example, the current sensor 130 has a first terminal 714a coupled to the second terminal 102b of the current source 102, has a second terminal 714b coupled to ground 150, and has a third terminal 714c coupled to the second terminal 128b of the measurement circuit 128. In some other embodiments (not shown), the current sensor is alternatively coupled between the first terminal 102a of the current source 102 and the second terminal 104b of the current supply circuit 104. The current sensor 714 senses the current generated by the current source 102 (e.g., the source current). In some embodiments, the current sensor 714 includes a current sense resistor (not shown) and a current sense amplifier (not shown).

In some embodiments, the system further includes a current control circuit 716 coupled to the current source 102. For example, the current source 102 has a control terminal 102c and the current control circuit 716 has a first terminal 716a coupled to the control terminal 102c. The current control circuit 716 is configured to control the level of the source current generated by the current source 102. For example, the current control circuit 716 is configured to tune the source current to a desirable level based on the number of test transistors that are coupled to the system for testing.

In the embodiment illustrated in FIG. 7, the current through each test transistor is approximately two times the source current. This is because there are four secondary mirror transistors and thus the supply current is approximately four times the source current, but two test transistors are on at a time, so the supply current is divided between the two test transistors. Thus, each test transistor passes approximately half of the supply current.

Although the embodiment illustrated in FIG. 7 shows the system including four test transistors, it will be appreciated that in some other embodiments, the system may include some other number of test transistors (e.g., three test transistors, five test transistors, six test transistors, etc.).

FIG. 8 illustrates a circuit diagram 800 of some embodiments of the system of FIG. 7 in which the ring oscillator 120 includes a second inverter 802 and a third inverter 804.

The second inverter 802 has an input terminal 802a coupled to the output terminal 410b of the first inverter 410 and has an output terminal 802b coupled to a control terminal 702c of the third test transistor 702 through terminal 120c. The third inverter 804 has an input terminal 804a coupled to the output terminal 802b of the second inverter 802 and has an output terminal 804b coupled to a control terminal 704c of the fourth test transistor 704 through terminal 120d.

Inverter 802 inverts the second oscillating signal at output terminal 410b, thereby forming a third oscillating signal, and outputs the third oscillating signal to the control terminal 702c of the third test transistor 702 through terminal 120c. Further, inverter 804 inverts the third oscillating signal at output terminal 802b, thereby forming a fourth oscillating signal, and outputs the fourth oscillating signal to the control terminal 704c of the fourth test transistor 704 through terminal 120d. Thus, the ring oscillator 120 outputs “non-inverted” oscillating signals (e.g., the first oscillating signal and the third oscillating signal) to control terminals of odd numbered test transistors (e.g., the first test transistor 112 and the third test transistor 702) and further outputs “inverted” oscillating signals (e.g., the second oscillating signal and the fourth oscillating signal) to even-numbered test transistors (e.g., the second test transistor 114 and the fourth test transistor 704). Consequently, the even-numbered test transistors and the odd-numbered test transistors switch in a complementary manner. For example, when the first test transistor 112 and the third test transistor 702 are on, the second test transistor 114 and the fourth test transistor 704 are off, and vice versa.

In some examples, the first oscillating and the third oscillating signal are approximately identical. Likewise, the second oscillating signal and the fourth oscillating signal are approximately identical. In some cases, a delay may exist between the first oscillating signal and the third oscillating signal, and between the second oscillating signal and the fourth oscillating signal. However, in many cases, the delay is generally negligible.

Although the embodiment illustrated in FIG. 8 shows the system including four test transistors, it will be appreciated that in some other embodiments, the system may include some other number of test transistors (e.g., three test transistors, five test transistors, six test transistors, etc.).

FIG. 9 illustrates a circuit diagram 900 of some embodiments of the system of FIG. 4 in which the output terminal 410b of inverter 410 is coupled to the input terminal 408a of inverter chain 408.

Output terminal 408b is coupled to control terminal 112c and input terminal 410a. Output terminal 410b is coupled to control terminal 114c and to input terminal 408a, thereby forming the “ring” of the ring oscillator circuit 120. The system of FIG. 9 operates similar to the system of FIG. 4 (which is shown in the timing diagram 500 of FIG. 5).

The total number of inverters in the ring oscillator circuit 120 is an odd number so that the signals at terminals 120a, 120b oscillate. For example, when there is an odd number of inverters coupled to the inverter chain 408, the inverter chain 408 has an even number of inverters so that the total number of inverters in the ring oscillator 120 is an odd number. Conversely, when there is an even number of inverters coupled to the inverter chain 408, the inverter chain 408 has an odd number of inverters so that the total number of inverters in the ring oscillator 120 is odd.

FIG. 10 illustrates a flow diagram 1000 of some embodiments of the operation of the ring oscillator 120 of FIG. 9. While flow diagram 1000 of FIG. 10 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At block 1002, the output of the inverter chain is provided to the input of the inverter and the output of the inverter is provided back to the input of input inverter chain to generate the first oscillating signal at the output of the inverter chain and the second oscillating signal at the output of the inverter. For example, output terminal 408b of inverter chain 408 is coupled to input terminal 410a of inverter 410 and output terminal 410b of inverter 410 is coupled to input terminal 408a of inverter chain 408. Thus, the output of inverter chain 408 is provided to the input of the inverter 410 and the output of the inverter 410 is provided to the input of the inverter chain 408. As a result, the output of inverter chain 408 oscillates, thereby forming the first oscillating signal, and the output of the inverter 410 oscillates, thereby forming the second oscillating signal.

At block 1004, the first oscillating signal is provided from the output of inverter chain to the control terminal of the first test transistor. For example, inverter chain 408 provides the first oscillating signal from output terminal 408b to the control terminal 112c of the first test transistor 112 through terminal 120a of the ring oscillator circuit 120.

At block 1006, the second oscillating signal is provided from the output of the inverter to the control terminal of the second test transistor. For example, inverter 410 provides the second oscillating signal from output terminal 410b to the control terminal 114c of the second test transistor 114 through terminal 120b of the ring oscillator circuit 120.

FIG. 11 illustrates a circuit diagram 1100 of some embodiments of the system of FIG. 9 in which the ring oscillator circuit 120 further comprises a second inverter 1102.

The system includes the first test transistor 112, the second test transistor 114, and the third test transistor 702. The second inverter 1102 is coupled to the first inverter 410. More particularly, an input terminal 1102a of the second inverter 1102 is coupled to the output terminal 410b of the first inverter 410. Further, an output terminal 1102b of the second inverter 1102 is coupled to the input terminal 408a of the inverter chain 408, thereby forming the “ring” of the ring oscillator 120. The output terminal 1102b of the second inverter 1102 is coupled to the control terminal 702c of the third test transistor 702. In the embodiment illustrated in FIG. 11, the first inverting chain 408 includes an odd numbered plurality of inverters so that the total number of inverters in the “ring” of the ring oscillator 120 is an odd number.

Although the embodiment illustrated in FIG. 11 shows the system including three test transistors, it will be appreciated that in some other embodiments, the system may include some other number of test transistors (e.g., four test transistors, five test transistors, six test transistors, etc.).

FIG. 12 illustrates a timing diagram 1200 corresponding to some embodiments of the system of FIG. 11.

Signal 1202 illustrates the source current I_SRCgenerated by current source 102 over time (e.g., as measured by measurement circuit 128 at terminal 128b). Signal 1204 illustrates the voltage V_INat the first voltage supply terminal 106 over time (e.g., as measured by measurement circuit 128 at terminal 128c).

Signal 1206 illustrates the voltage V_OUTat the third terminal 104c of the current supply circuit 104 over time (e.g., as measured by measurement circuit 128 at terminal 128a). The voltage at terminal 104c oscillates between a first voltage level and a second voltage level in response to the switching of the test transistors. For example, when the first test transistor 112 and the third test transistor 702 are off and the second test transistor 114 is on, the voltage at terminal 104c is at a first voltage level. Further, when the first test transistor 112 and the third test transistor 702 are on and the second test transistor 114 is off, the voltage at terminal 104c is at a second voltage level, less than the first voltage level. When the first and third test transistors 112, 702 are on, there is less resistance between terminal 104c and voltage supply terminal 118. Thus, the voltage at terminal 104c is reduced. When the second test transistor 114 is on, there is greater resistance between terminal 104c and voltage supply terminal 118. Thus, the voltage at terminal 104c is increased.

Signal 1208 illustrates the voltage V_C1at the control terminal 112c of the first test transistor 112 over time (e.g., as measured by measurement circuit 128 at terminal 128e).

Signal 1210 illustrates the current I₁through the first terminal 112a of the first test transistor 112 over time. In the embodiment illustrated in FIG. 11, the current through the first test transistor 112 is approximately one and a half times the source current.

Signal 1212 illustrates the voltage V_C2at the control terminal 114c of the second test transistor 114 over time (e.g., as measured by measurement circuit 128 at terminal 128f).

Signal 1214 illustrates the current I₂through the first terminal 114a of the second test transistor 114 over time. In the embodiment illustrated in FIG. 11, the current through the second test transistor 114 is approximately three times the source current.

Signal 1216 illustrates the voltage V_C3at the control terminal 702c of the third test transistor 702 over time (e.g., as measured by measurement circuit 128 at terminal 128g). The voltage at the control terminal 702c of the third test transistor 702 is approximately equal to the voltage at the control terminal 112c of the first test transistor 112.

Signal 1218 illustrates the current I₃through the first terminal 702a of the third test transistor 702 over time. In the embodiment illustrated in FIG. 11, the current through the third test transistor 702 is approximately one and a half times the source current.

FIG. 13 illustrates a circuit diagram 1300 of some embodiments of the system of FIG. 9 in which the ring oscillator circuit 120 includes a second inverter chain 1302 and a third inverter chain 1304.

The first inverter chain 408 comprises the first plurality of inverters coupled in series between the input terminal 408a and the output terminal 408b of the first inverter chain 408. The second inverter chain 1302 is coupled to the first inverter chain 408. The second inverter chain 102 comprises a second plurality of inverters coupled in series between an input terminal 1302a and an output terminal 1302b of the second inverter chain 1302. Input terminal 1302a is coupled to output terminal 408b. The third inverter chain 1304 is coupled to the second inverter chain 1302. The third inverter chain 1304 comprises a third plurality of inverters coupled in series between an input terminal 1304a and an output terminal 1304b of the third inverter chain 1304. Input terminal 1304a is coupled to output terminal 1302b. Output terminal 1304b is coupled to input terminal 408a.

The total number of inverters in the ring oscillator circuit 120 is an odd number. In some embodiments, each inverter chain may have the same number of inverters. In some other embodiments, the first inverter chain 408 may include more inverters than the second inverter chain 1302 and more inverters than the third inverter chain 1304. Although three inverters are shown in each chain in the embodiments illustrated in FIG. 13, it will be appreciated that in some embodiments, each inverter chain could alternatively include some other number of inverters.

In some cases, when the number of inverters in the second inverter chain 1302 and the third inverter chain 1304 is large and/or approximately equal to the number of inverters in the first chain 408, a delay may be observed between the switching of the test transistors. For example, as shown by signals 1408, 1412 of FIG. 14, the second test transistor 114 switches after a delay in response to the first test transistor 112 switching. Likewise, as shown by signals 1412, 1416 of FIG. 14, the third test transistor 702 switches after a delay in response to the second test transistor 114 switching. Consequently, the current through each test transistor varies due to the switching delays, as shown by signals 1410, 1414, 1418 of FIG. 14.

Although the embodiment illustrated in FIG. 13 shows the system including three test transistors, it will be appreciated that in some other embodiments, the system may include some other number of test transistors (e.g., four test transistors, five test transistors, six test transistors, etc.).

FIG. 14 illustrates a timing diagram 1400 corresponding to some embodiments of the system of FIG. 13.

Signal 1402 is the source current I_SRCgenerated by current source 102 over time. Signal 1404 is the voltage V_INat the first voltage supply terminal 106 over time. Signal 1406 is the voltage V_OUTat the third terminal 104c of the current supply circuit 104 over time. Signal 1408 is the voltage V_C1at the control terminal 112c of the first test transistor 112 over time. Signal 1410 is the current I₁through the first terminal 112a of the first test transistor 112 over time. Signal 1412 is the voltage V_C2at the control terminal 114c of the second test transistor 114 over time. Signal 1414 is the current I₂through the first terminal 114a of the second test transistor 114 over time. Signal 1416 shows the voltage V_C3at the control terminal 702c of the third test transistor 702 over time. Signal 1418 shows the current I₃through the first terminal 702a of the third test transistor 702 over time.

FIG. 15 illustrates a circuit diagram 1500 of some embodiments of the ring oscillator circuit