120. By way of example not limitation, the first epitaxial layer can be doped with arsenic (As) dopants, other suitable dopant species, or combinations thereof.

By way of example and not limitation, the first and second epitaxial layers can be “blanket-deposited” with a chemical vapor deposition (CVD) process using precursor gases, such as silane (SiH₄), disilane (Si₂H₆), germane (GeH₄), digermane (Ge₂H₆), dichlorosilane (SiH₂Cl₂), other suitable gases, or combinations thereof. In some embodiments, the first and second epitaxial layers are deposited at a temperature between about 550° C. and 800° C. and at a process pressure between about 1 Torr and about 600 Torr. In some embodiments, the second epitaxial layer is deposited at a higher temperature than that of the first epitaxial layer.

In some embodiments, the first epitaxial layer can be formed by ion implantation where a top portion of the substrate is doped with Ge or As to form a SiGe layer or an As-doped silicon layer. The second epitaxial layer can be subsequently formed on the first epitaxial layer.

In some embodiments, FIG. 4 is an isometric view of a first epitaxial layer 400 and a second epitaxial layer 405 deposited on substrate 120 according to operation 305. According to some embodiments, the thickness of first epitaxial layer 400 shown in FIG. 4 corresponds to the thickness of local isolation structure 115 shown in FIG. 1. Therefore, the thickness of first epitaxial layer 400 is substantial similar to the thickness of local isolation structure 115—for example, between about 5 nm and about 100 nm. According to some embodiments, second epitaxial layer 405 will be patterned to form epitaxial layer 110 shown in FIG. 1. Therefore, the as-deposited thickness of second epitaxial layer 405 corresponds to the thickness of epitaxial layer 110—for example, between about 5 nm and about 100 nm. As discussed above with respect to epitaxial layer 110, a second epitaxial layer thicker than about 100 nm can induce undesirable mechanical stress to substrate 120.

In referring to FIG. 3A, method 300 continues with operation 310 and the process of etching trench openings in first epitaxial layer 400, second epitaxial layer 405, and substrate 120. By way of example and not limitation, the trench openings in first epitaxial layer 400, second epitaxial layer 405, and substrate 120 can be formed with the patterning process described below. In referring to FIG. 4, a masking stack is disposed on second epitaxial layer 405 to cover the entire surface of second epitaxial layer 405. The masking stack is subsequently patterned to form patterned structures 410. Patterned structures 410 function as an etching mask in a subsequent etching process used to remove exposed portions of second epitaxial layer 405, first epitaxial layer 400, and substrate 120 to form trench openings 500 shown in FIG. 5—a cross-sectional view of the structure shown in FIG. 4 along cut-line AB. In some embodiments, patterned structures 410 include a bottom hard mask layer (e.g., an oxide layer) and a top photo mask layer (e.g., a photoresist layer), which are not shown in FIGS. 4 and 5 for simplicity. In some embodiments, patterned structures 410 include a bottom hard mask stack of alternating oxide and nitride layers, such as silicon oxide and silicon nitride, and a top photoresist layer.

The etching process can include a dry etching process, a wet etching process, or combinations thereof. In some embodiments, the etching process uses an etching chemistry that is selective towards the target layers—for example, substrate 120, first epitaxial layer 400, and second epitaxial layer 405.

By way of example and not limitation, a dry etching process can include an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, other suitable etching gases and/or plasmas, or combinations thereof. Examples of a fluorine-containing gas include, but are not limited to, carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), difluoromethane (CH₂F₂), trifluoromethane (CHF₃), and hexafluoroethane (C₂F₆). Examples of a chlorine-containing gas include, but are not limited to, chlorine (Cl₂), chloroform (CHCl₃), carbon tetrachloride (CCl₄), and boron trichloride (BCl₃). Examples of a bromine-containing gas include, but are not limited to, hydrogen bromide (HBr) and bromoform (CHBr₃).

By way of example and not limitation, a wet etching process can include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH), ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO₃), acetic acid (CH₃COOH), or combinations thereof.

In referring to FIG. 5, trench openings 500 are formed in un-masked portions of second epitaxial layer 405, first epitaxial layer 400, and substrate 120. Therefore, patterned structures 410 are formed on locations of substrate 120 where the formation of trench openings 500 is not desired. During the etching process of operation 310, multiple trench openings 500 can be formed as shown in FIG. 5. The location and size of trench openings 500 is defined by the relative position and dimensions (e.g., length and width) of patterned structures 410. According to some embodiments, trench openings 500 form shallow trench isolation (STI) openings, which when subsequently filled with a dielectric material form respective shallow trench isolation (STI) structures in substrate 120. In some embodiments, patterned structures 410 can have different spacing, shapes, and size from the patterned structures shown in FIG. 5. Further, the spacing, shape, and size of each patterned structure 410 can be different from one another. According to some embodiments, FIG. 5 shows selective portions of substrate 120 where trench openings 500 are formed. Other portions of substrate 120, not shown in FIG. 5, may remain covered by patterned structures 410 or have patterned structures 410 with different spacing, shape, and/or size.

According to some embodiments, trench openings 500 expose sidewall surfaces of first and second epitaxial layers 400 and 405 as shown in FIG. 5.

In referring to FIG. 3A, method 300 continues with operation 315 and the process of removing, through trench openings 500, portions of first epitaxial layer 400 to form a gap between second epitaxial layer 405 and substrate 120. In some embodiments, the removal process of operation 315 does not remove the entire first epitaxial layer 400. Instead, the removal process removes portions of first epitaxial layer 400 in the vicinity of trench openings 500. In other words, the resulting gap is formed around trench openings 500 and not over the entire substrate 120. This can be accomplished, for example, by appropriately timing the etching process or by locally controlling the etching selectivity of first epitaxial layer 400 with dopants. In some embodiments, the etching process used in operation 315 is capable of laterally etching first epitaxial layer 400 to form a gap between second epitaxial layer 405 and substrate 120.

In some embodiments, the etching processes can include dry etching, wet etching, or combinations thereof. For example, the etching process can include a cyclic process of dry and wet etching processes. By way of example and not limitation, a dry etching chemistry can include a chlorine containing gas, such as hydrochloric acid (HCl), Cl₂, chlorotrifluoromethane (CF₃Cl), CCl₄or silicon tetrachloride (SiCl₄) with helium (He) or argon (Ar) as the carrier gas. Respectively, a wet etching chemistry can include a tetramethylammonium hydroxide (TMAH) aqueous solution if first epitaxial layer 400 was previously doped with As or another dopant. Alternatively, the wet etching can include a solution of hydrogen peroxide (H₂O₂), CH3COOH, and hydrofluoric acid (HF) followed by a deionized water (DIW) clean.

According to some embodiments, FIG. 6 shows the structure of FIG. 5 after operation 315. As shown in FIG. 6, portions of first epitaxial layer 400 have been laterally etched (e.g., removed) to form gap 600 while other portions of first epitaxial layer 400—for example, located at a distance L from trench openings 500—have been preserved (e.g., not removed). In some embodiments, distance L ranges from about 5 nm to about 1 μm. Non-etched portions of first epitaxial layer 400 provide support for second epitaxial layer 405 and patterned structures 410 over gap 600, and prevent second epitaxial layer 405 and patterned structures 410 from collapsing.

In referring to FIG. 3A, method 300 continues with operation 320 and the process of depositing a first dielectric in trench openings 500 to fill gap 600 between second epitaxial layer 405 and substrate 120. By way of example and not limitation, the first dielectric can be deposited with a flowable CVD high aspect ratio process (HARP) where a liquid-like flowable dielectric is deposited, cured, and subsequently annealed to form the first dielectric. Alternatively, the first dielectric can be deposited with a high-density plasma process (HDP). In some embodiments, the first dielectric deposited in operation 320 is used to form isolation structure 115 described in FIG. 1. According to some embodiments, FIG. 7 shows the structure of FIG. 6 after the formation of first dielectric 700 according to operation 320. First dielectric 700 is deposited sufficiently thick to substantially fill gap 600 shown in FIG. 6. In some embodiments, first dielectric 700 does not completely fill gap 600. For example, air pockets or voids 710 can be formed between second epitaxial layer 405 and substrate 120 as shown in the insert of FIG. 7, which is a magnified view of first dielectric 700.

In referring to FIG. 3B, method 300 continues with operation 325 and the process of etching-back first dielectric 700 from the trench openings to form isolation structure 115 shown in FIG. 1 between second epitaxial layer 405 and substrate 120. In some embodiments, the etch-back process is an anisotropic dry etching process capable of selectively etching first dielectric 700 (e.g., silicon oxide). In some embodiments, the etch-back process removes first dielectric 700 so that trench openings 500 are exposed as shown in FIG. 8. Due to the anisotropy for the etch-back process, first dielectric 700 is not laterally etched and therefore not removed between second epitaxial layer 405 and substrate 120. Consequently, sidewall surfaces of second epitaxial layer 405 are aligned to sidewall surfaces of first dielectric 700 as shown in FIG. 8. In some embodiments, the un-etched portions of first dielectric 700 between second epitaxial layer 405 and substrate 120 form isolation structure 115 shown in FIG. 1. In some embodiments, after operation 325, patterned structures 410 can be removed with a wet etching process or any other suitable process.

In referring to FIG. 3B, method 300 continues with operation 330 and the process of depositing a third epitaxial layer in trench openings 500. In some embodiments, the third epitaxial layer is similar to second epitaxial layer 405. For example, the third epitaxial layer can be a substantially Ge-free Si epitaxial layer deposited with a CVD process using precursor gases, such as silane (SiH₄), disilane (Si₂H₆), dichlorosilane (SiH₂Cl₂), other suitable gases, and combinations thereof.

In some embodiments, prior to the deposition of the third epitaxial layer, a liner material is formed on surfaces of trench openings 500 at a thickness between about 1 nm and about 5 nm. The liner material can act as a passivation or buffer layer that suppresses defect formation during the growth process of third epitaxial layer. In some embodiments, the liner material is annealed at about 850° C. for about 100 seconds prior to the deposition of the third epitaxial layer. By way of example and not limitation, FIG. 9 shows the structure of FIG. 8 after the formation of liner 900 and third epitaxial layer 905 according to operation 330. In some embodiments, liner 900 facilitates the formation of third epitaxial layer 905 and third epitaxial layer 905 facilitates the formation of the nano-sheet layers formed in operation 340. For example, third epitaxial layer 905 prevents or suppresses the formation defects in the nano-sheet layers formed thereon.

In referring to FIG. 3B, method 300 continues with operation 335 and the process of planarizing third epitaxial layer 905 so that third epitaxial layer 905 becomes co-planar with second epitaxial layer 405. By way of example and not limitation, third epitaxial layer 905 can be planarized with a chemical mechanical planarization (CMP) process, which removes third epitaxial layer 905 and liner 900 over top surfaces of second epitaxial layer 405 and results in a planar top surface topography. The resulting structure with the planarized/polished third epitaxial layer 905 is shown in FIG. 10.

In referring to FIG. 3B, method 300 continues with operation 340 and the process of forming a stack of nano-sheet (NS) layers on second epitaxial layer 405. In some embodiments, the stack is also formed on third epitaxial layer 905. In some embodiments, the stack of NS layers includes alternating layers of NS layer 130, shown in FIG. 1, and another type of NS layer different from NS layer 130. By way of example and not limitation, FIG. 11 shows a stack of NS layers 1100 (stack 1100) with alternating layers of NS layers 1105 and NS layer 130 formed on second epitaxial layer 405 and third epitaxial layer 905 according to operation 340. In some embodiments, the material for NS layers 1105 in stack 1100 is selected so that NS layers 1105 can be selectively removed via etching from stack 1100 without removing NS layers 130. For example, if NS layers 130 are silicon NS layers, NS layers 1000 can be SiGe NS layers. In some embodiments, NS layers 130 and NS layers 100 are formed with a method similar to the one used to deposit first and second epitaxial layers 400 and 405. Removal of NS layers 1105 from stack 1100 forms the channel region of GAA FET 100 shown in FIG. 1.

By way of example and not limitation, stack 1100 can be formed across the entire surface of substrate 120 and be subsequently patterned so that portions of stack 1100 on third epitaxial layer 905 are selectively removed as shown in FIG. 12A. As a result, fin structures 1200 are formed on selected potions of second epitaxial layer 405 and sidewall surfaces of fin structures 1200 are aligned to sidewall surfaces of second epitaxial layer 405 and first dielectric 700. During the aforementioned patterning process, third epitaxial layer 905 and liner 900 are also removed between fin structures 1200 as shown in FIG. 12A. In some embodiments, a capping layer 1205 having a thickness between about 5 nm and about 15 nm is deposited to cover fin structures 1200 as shown in FIG. 12B. In some embodiments, capping layer 1205 is an oxide layer (e.g., a silicon oxide layer) that protects fin structures 1200 from a subsequent etch-back process. In referring to FIG. 12B, a second dielectric 1210 is deposited on capping layer 1205 over fin structures 1100, planarized with a CMP process, and subsequently etched-back to form shallow trench isolation (STI) structures 1215. In some embodiments, the etch-back process recesses both capping layer 1205 and second dielectric 1210 to the height level of second epitaxial layer 405 so that top surfaces of capping layer 1205 and STI structures 1215 are coplanar with top surfaces of second epitaxial layer 405.

In some embodiments, a sacrificial gate structure (not shown) is formed along the y-direction on a mid-portion of fin structures 1100 so that end-portions of fin structures along the x-axis are protruding from the sacrificial gate structure. Subsequently, an etching process removes (e.g., trims) the exposed end-portions of fin structures 1100. During the etching process, portions of second epitaxial layer 400 not covered by the sacrificial gate structure will be exposed and subsequently recessed with respect to covered mid-portions of epitaxial layer 400 and top surfaces of STI structures 1215 to form recessed portions 1220 as shown in the isometric view of FIG. 12C. The sacrificial gate structure can be used as a masking layer for the etching operation described above is not shown in FIG. 12C for simplicity and ease of visualization.

According to some embodiments, second epitaxial layer 405 with recessed portions 1220 and first dielectric 700 shown in FIG. 12C correspond respectively to epitaxial layer 110 and isolation structure 115 shown in FIG. 1. In some embodiments, S/D epitaxial structures 125 are formed on recessed portions 1220 of second epitaxial layer 405. Further, NS layers 1105 are removed from fin structures 1200 with a selective etching process and gate stack 140 replaces the sacrificial gate structures to form GAA FET 100 shown in FIG. 1.

According to some embodiments, FIGS. 13A and 13B are flow diagrams of a fabrication method 1300 for the formation of local isolation structures 200 and epitaxial layer 205 shown in FIG. 2. Other fabrication operations can be performed between the various operations of method 1300 and are omitted merely for simplicity. This disclosure is not limited to this operational description. Rather, other operations are within the spirit and scope of the present disclosure. It is to be appreciated that additional operations may be performed. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously, or in a different order than the ones presented in FIGS. 13A and 13B. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations. For illustrative purposes, method 1300 is described with reference to the embodiments shown in FIGS. 4-9 and 14A-17.

In some embodiments, operations 1305-1335 of method 1300 are identical to operations 305-335 of method 300 described above. Therefore, FIGS. 4-10 used to describe operations 305-335 of method 300 can be used to describe operations 1305-1335 of method 1300. For this reason, the description of method 1300 will continue from FIG. 10 and operation 1340 shown in FIG. 13B.

In referring to FIG. 13B, method 1300 continues with operation 1340 and the process of patterning second epitaxial layer 405 and first dielectric 700 to form an opening in first dielectric 700 to expose substrate 120. In some embodiments, FIG. 14 is an isometric view of FIG. 10. As shown in FIG. 14, third epitaxial layer 905 surrounded by liner 900 forms structures with a length along the x-direction and a width along the y-direction so that sidewall surfaces of second epitaxial layer 405 first dielectric 700 are aligned. According to operation 1340, portions of second epitaxial layer 405 and first dielectric 700 between the structures formed by third epitaxial layer 905 and liner 900 are patterned to form an opening 1500 with a length L to expose substrate 120 as shown in FIG. 15. In some embodiments, length L of opening