131 and 132 focus light at the image sensors 101 and 102, respectively, through one or more apertures for receiving light, one or more shutters for blocking light when outside an exposure window, one or more color filter arrays (CFAs) for filtering light outside of specific frequency ranges, one or more analog front ends for converting analog measurements to digital information, and/or other suitable components for imaging.

Each of the cameras 103, 105 may include one, two, or more image sensors 101, 102. For example, the camera 103 may include a first image sensor 101 and a second image sensor (not depicted). When multiple image sensors are present, the first image sensor 101 may have a larger field of view (FOV) than the second image sensor or the first image sensor 101 may have different sensitivity or different dynamic range than the second image sensor. In one example, the first image sensor 101 may be a wide-angle image sensor, and the second image sensor may be a telephoto image sensor. In another example, the first image sensor 101 is configured to obtain an image through a first lens with a first optical axis and the second sensor is configured to obtain an image through a second lens with a second optical axis different from the first optical axis. Additionally or alternatively, the first lens may have a first magnification, and the second lens may have a second magnification different from the first magnification. This configuration may occur in a camera module with a lens cluster, in which the multiple image sensors and associated lenses are located in offset locations within the camera module. Additional image sensors may be included with larger, smaller, or same fields of view. Although the example discussed above focused on the first camera 103, the second camera 105 may be configured using one or more of the configurations discussed above (such as with a first image sensor 102 and a second image sensor (not depicted)).

Each image sensor may include means for capturing data representative of a scene, such as image sensors (including charge-coupled devices (CCDs), Bayer-filter sensors, infrared (IR) detectors, ultraviolet (UV) detectors, complimentary metal-oxide-semiconductor (CMOS) sensors), and/or time of flight detectors. The apparatus may further include one or more means for accumulating and/or focusing light rays into the one or more image sensors (including simple lenses, compound lenses, spherical lenses, and non-spherical lenses). These components may be controlled to capture the first, second, and/or more image frames. The image frames may be processed to form a single output image frame, such as through a fusion operation, and that output image frame further processed according to the aspects described herein.

As used herein, image sensor may refer to the image sensor itself and any certain other components coupled to the image sensor used to generate an image frame for processing by the image signal processor or other logic circuitry or storage in memory, whether a short-term buffer or longer-term non-volatile memory. For example, an image sensor may include other components of a camera, including a shutter, buffer, or other readout circuitry for accessing individual pixels of an image sensor. The image sensor may further refer to an analog front end or other circuitry for converting analog signals to digital representations for the image frame that are provided to digital circuitry coupled to the image sensor.

In some embodiments, the image signal processor 112 may execute instructions from a memory, such as instructions 108 from the memory 106, instructions stored in a separate memory coupled to or included in the image signal processor 112, or instructions provided by the processor 104. In addition, or in the alternative, the image signal processor 112 may include specific hardware (such as one or more integrated circuits (ICs)) configured to perform one or more operations described in the present disclosure. For example, the image signal processor 112 may include one or more image front ends (IFEs) 135, one or more image post-processing engines (IPEs) 136, and or one or more auto exposure compensation (AEC) 134 engines. The AF 133, AEC 134, IFE 135, IPE 136 may each include application-specific circuitry, be embodied as software code executed by the ISP 112, and/or a combination of hardware within and software code executing on the ISP 112.

In some implementations, the memory 106 may include a non-transient or non-transitory computer readable medium storing computer-executable instructions 108 to perform all or a portion of one or more operations described in this disclosure. In some implementations, the instructions 108 include a camera application (or other suitable application) to be executed during operation of the processing system 100 for generating images or videos. The instructions 108 may also include other applications or programs executed for the processing system 100, such as an operating system, mapping applications, or entertainment applications. Execution of the camera application, such as by the processor 104, may cause the processing system 100 to generate images using the image sensors 101 and 102 and the image signal processor 112. The memory 106 may also be accessed by the image signal processor 112 to store processed frames or may be accessed by the processor 104 to obtain the processed frames. In some embodiments, the processing system 100 includes a system on chip (SoC) that incorporates the image signal processor 112, the processor 104, the sensor hub 150, the memory 106, and input/output components 116 into a single package.

In some embodiments, at least one of the image signal processor 112 or the processor 104 executes instructions to perform various operations described herein, including object detection, image processing, natural language processing, text generation, risk map generation, driver monitoring, driver alert operations, and the like. For example, execution of the instructions can instruct the image signal processor 112 to begin or end capturing an image frame or a sequence of image frames. In some embodiments, the processor 104 may include one or more general-purpose processor cores 104A capable of executing scripts or instructions of one or more software programs, such as instructions 108 stored within the memory 106. For example, the processor 104 may include one or more application processors configured to execute the camera application (or other suitable application for generating images or video) stored in the memory 106. In executing the camera application, the processor 104 may be configured to instruct the image signal processor 112 to perform one or more operations with reference to the image sensors 101, 102, as discussed above.

In some embodiments, the processor 104 may include ICs or other hardware (e.g., an artificial intelligence (AI) engine 124) in addition to the ability to execute software to cause the processing system 100 to perform a number of functions or operations, such as the operations described herein. In some other embodiments, the processing system 100 does not include the processor 104, such as when all of the described functionality is configured in the image signal processor 112. In particular embodiments, the processor 104 and/or another processor of the processing system 100 may include a machine learning processor. Machine learning processors may include one or more processing units tailored for operating/manipulating machine learning data/features structures (e.g., tensors), executing machine learning algorithms, or a combination thereof. A first example machine learning processor includes Neural Processors (NPs), hardware components specifically designed to perform calculations necessary for artificial neural networks, leveraging parallel processing capabilities to handle complex computational tasks efficiently. A second example machine learning processor includes Hardware-Based Machine Learning Accelerators (MLAs) that enhance the speed of machine learning applications by optimizing the underlying hardware for specific machine learning algorithms (such as for particular types of computing operations). A third example machine learning processor may include an machine learning (ML) core within a CPU, which may be embedded in a traditional CPU and may be specifically optimized to accelerate machine learning workloads or computations. A fourth example machine learning processor may include Neural Signal Processors (NSPs) and/or Neural Processing Units (NPUs) are other types of processors that are designed for optimized performance with neural network-based workloads.

In some embodiments, the display 114 may include one or more suitable displays or screens allowing for user interaction and/or to present items to the user, such as a preview of the image frames being captured by the image sensors 101 and 102. In some embodiments, the display 114 is a touch-sensitive display. The I/O components 116 may be or include any suitable mechanism, interface, or device to receive input (such as commands) from the user and to provide output to the user through the display 114. For example, the I/O components 116 may include (but are not limited to) a graphical user interface (GUI), a keyboard, a mouse, a microphone, speakers, a squeezable bezel, one or more buttons (such as a power button), a slider, a switch, and so on.

While shown to be coupled to each other via the processor 104, components (such as the processor 104, the memory 106, the image signal processor 112, the display 114, and the I/O components 116) may be coupled to each another in other various arrangements, such as via one or more local buses, which are not shown for simplicity. While the image signal processor 112 is illustrated as separate from the processor 104, the image signal processor 112 may be a core of a processor 104 that is an application processor unit (APU), included in a system on chip (SoC), or otherwise included with the processor 104. While the processing system 100 is referred to in the examples herein for including aspects of the present disclosure, some device components may not be shown in FIG. 1 to prevent obscuring aspects of the present disclosure. Additionally, other components, numbers of components, or combinations of components may be included in a suitable vehicle for performing aspects of the present disclosure. As such, the present disclosure is not limited to a specific device or configuration of components, including the processing system 100.

The processing system 100 may communicate as a user equipment (UE) within a wireless network 200, such as through WAN adaptor 152, as shown in FIG. 2. FIG. 2 is a block diagram illustrating details of an example wireless communication system according to one or more aspects. Wireless network 200 may, for example, include a 5G wireless network. As appreciated by those skilled in the art, components appearing in FIG. 2 are likely to have related counterparts in other network arrangements including, for example, cellular-style network arrangements and non-cellular-style-network arrangements (e.g., device-to-device or peer-to-peer or ad-hoc network arrangements, etc.).

Wireless network 200 includes base stations 205 and other network entities. A base station may be a station that communicates with the UEs and may also be referred to as an evolved node B (eNB), a next generation eNB (gNB), an access point, and the like. Each base station 205 may provide communication coverage for a particular geographic area. In 3GPP, the term “cell” may refer to this particular geographic coverage area of a base station or a base station subsystem serving the coverage area, depending on the context in which the term is used. In implementations of wireless network 200 herein, base stations 205 may be associated with a same operator or different operators (e.g., wireless network 200 may include a plurality of operator wireless networks). Additionally, in implementations of wireless network 200 herein, base station 205 may provide wireless communications using one or more of the same frequencies (e.g., one or more frequency bands in licensed spectrum, unlicensed spectrum, or a combination thereof) as a neighboring cell. In some examples, an individual base station 205 or UE 215 may be operated by more than one network operating entity. In some other examples, each base station 205 and UE 215 may be operated by a single network operating entity.

A base station may provide communication coverage for a macro cell or a small cell, such as a pico cell or a femto cell, or other types of cell. A macro cell generally covers a relatively large geographic area (e.g., several kilometers in radius) and may allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a pico cell, would generally cover a relatively smaller geographic area and may allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a femto cell, would also generally cover a relatively small geographic area (e.g., a home) and, in addition to unrestricted access, may also provide restricted access by UEs having an association with the femto cell (e.g., UEs in a closed subscriber group (CSG), UEs for users in the home, and the like). A base station for a macro cell may be referred to as a macro base station. A base station for a small cell may be referred to as a small cell base station, a pico base station, a femto base station or a home base station. In the example shown in FIG. 2, base stations 205d and 205e are regular macro base stations, while base stations 205a-205c are macro base stations enabled with one of three-dimension (3D), full dimension (FD), or massive MIMO. Base stations 205a-205c take advantage of their higher dimension MIMO capabilities to exploit 3D beamforming in both elevation and azimuth beamforming to increase coverage and capacity. Base station 205f is a small cell base station which may be a home node or portable access point. A base station may support one or multiple (e.g., two, three, four, and the like) cells.

Wireless network 200 may support synchronous or asynchronous operation. For synchronous operation, the base stations may have similar frame timing, and transmissions from different base stations may be approximately aligned in time. For asynchronous operation, the base stations may have different frame timing, and transmissions from different base stations may not be aligned in time. In some scenarios, networks may be enabled or configured to handle dynamic switching between synchronous or asynchronous operations.

UEs 215 are dispersed throughout the wireless network 200, and each UE may be stationary or mobile. It should be appreciated that, although a mobile apparatus is commonly referred to as a UE in standards and specifications promulgated by the 3GPP, such apparatus may additionally or otherwise be referred to by those skilled in the art as a mobile station (MS), a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal (AT), a mobile terminal, a wireless terminal, a remote terminal, a handset, a terminal, a user agent, a mobile client, a client, a gaming device, an augmented reality device, vehicular component, vehicular device, or vehicular module, or some other suitable terminology.

Some non-limiting examples of a mobile apparatus, such as may include implementations of one or more of UEs 215, include a mobile, a cellular (cell) phone, a smart phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a laptop, a personal computer (PC), a notebook, a netbook, a smart book, a tablet, a personal digital assistant (PDA), and a vehicle. Although UEs 215i-k are specifically shown as vehicles, a vehicle may employ the communication configuration described with reference to any of the UEs 215a-215k.

In one aspect, a UE may be a device that includes a Universal Integrated Circuit Card (UICC). In another aspect, a UE may be a device that does not include a UICC. In some aspects, UEs that do not include UICCs may also be referred to as IoE devices. UEs 215a-215d of the implementation illustrated in FIG. 2 are examples of mobile smart phone-type devices accessing wireless network 200. A UE may also be a machine specifically configured for connected communication, including machine type communication (MTC), enhanced MTC (eMTC), narrowband IoT (NB-IoT) and the like. UEs 215e-215k illustrated in FIG. 3 are examples of various machines configured for communication that access wireless network 200.

A mobile apparatus, such as UEs 215, may be able to communicate with any type of the base stations, whether macro base stations, pico base stations, femto base stations, relays, and the like. In FIG. 2, a communication link (represented as a lightning bolt) indicates wireless transmissions between a UE and a serving base station, which is a base station designated to serve the UE on the downlink or uplink, or desired transmission between base stations, and backhaul transmissions between base stations. UEs may operate as base stations or other network nodes in some scenarios. Backhaul communication between base stations of wireless network 200 may occur using wired or wireless communication links.

In operation at wireless network 200, base stations 205a-205c serve UEs 215a and 215b using 3D beamforming and coordinated spatial techniques, such as coordinated multipoint (CoMP) or multi-connectivity. Macro base station 205d performs backhaul communications with base stations 205a-205c, as well as small cell, base station 205f. Macro base station 205d also transmits multicast services which are subscribed to and received by UEs 215c and 215d. Such multicast services may include mobile television or stream video, or may include other services for providing community information, such as weather emergencies or alerts, such as Amber alerts or gray alerts.

Wireless network 200 of implementations supports mission critical communications with ultra-reliable and redundant links for mission critical devices, such UE 215e, which is a drone. Redundant communication links with UE 215e include from macro base stations 205d and 205e, as well as small cell base station 205f. Other machine type devices, such as UE 215f (thermometer), UE 215g (smart meter), and UE 215h (wearable device) may communicate through wireless network 200 either directly with base stations, such as small cell base station 205f, and macro base station 205e, or in multi-hop configurations by communicating with another user device which relays its information to the network, such as UE 215f communicating temperature measurement information to the smart meter, UE 215g, which is then reported to the network through small cell base station 205f. Wireless network 200 may also provide additional network efficiency through dynamic, low-latency TDD communications or low-latency FDD communications, such as in a vehicle-to-vehicle (V2V) mesh network between UEs 215i-215k communicating with macro base station 205e.

Aspects of the systems described with reference to, and shown in, FIGS. 1 and 2 may include determining attention weights for use in receiving and processing sensor data, which may include sensor data in different bitwidths.

FIG. 3 is a block diagram illustrating a system 300 for bitwidth-responsive processor operation according to one aspect of the present disclosure. The system 300 may be an exemplary implementation of the processing system 100. The system 300 includes sensors 33, 332 and a processor 302, which may be an exemplary implementation of the ISP 112, the process 104, or a combination thereof. The image sensors 101, 102 include image data 304, 306. The processor 302 includes a predetermined bitwidth 308, a first bitwidth 310, a second bitwidth 312, a processing components 3314, 316, 318, and output data 326. The processing components 314, 316, 318 include bit registers 320, 322, 324.

The processor 302 may be configured to receive, at a processor 302, first data 304 from a first sensor 330. The processor 302 may be any of various types of processors. For example, the processor 302 may be a CPU (such as the processor 104), an ISP (such as the ISP 112), and the like. Data 304, 306 received by the processor 302 may be in different formats and/or different bitwidths in various implementations. In certain implementations, the sensors 330, 332 may be image sensors (such as the image sensors 101, 102) and the data 304, 306 may be image data (such as image frames 230). The first data 304 may have a first bitwidth 310. Data may have different bitwidths depending on the sensors 330, 332 (such as capabilities of the sensors, operating modes of the sensors, and the like). In certain implementations, the sensors 330, 332 may be capable of capturing data in different bitwidths. In one particular implementation, the first sensor 330 may be an image sensor configured with at least three operating modes: a first mode that captures HDR image data in an 18-bit bitwidth (such as using three exposures), a second mode that captures HDR image data in a 14-bit bitwidth, and a third mode that captures non-HDR image data in a 10-bit bitwidth. The sensor 102 may similarly have different operating modes with different bitwidths (including one or more operating modes that differ from those of the first sensor 101). In such implementations, the bitwidth of the data 304, 306 received from the sensors 101, 102 may differ depending on the operating mode of the sensors 101, 102. In certain implementations, the first data 304 may be image data, the first sensor may be an image sensor. In such instances, the first bitwidth 310 may be a per-pixel bitwidth of the first data 304.

The processor 302 may be configured to determine that the first bitwidth 310 is less than a predetermined bitwidth 308 associated with the processor 302. In certain implementations, the predetermined bitwidth 308 may be a maximum supported bitwidth of the processor 302. In certain implementations, the processor 302 may include one or more components that are capable of processing data with a particular maximum bitwidth. For example, the processor 302 may include one or more bit registers 320, 322, 324 of a first size, and the maximum bitwidth of the processor 302 may be the first size of the bit registers. In the example above where the sensor 101 is capable of capturing image data 304 with bitwidth of up to 18 bits, the bit registers 320, 322, 324 may be 18 bits in size. Accordingly, the predetermined bitwidth 308 may be 18 bits. In certain implementations, the predetermined bitwidth 308 may be less than the maximum supported bitwidth of the processor 302. For example, the processor 302 may be operating in a low power mode, and the maximum supported bitwidth may be determined based on the low power mode (such as 1, 2, 3, 4, or more bits less than the maximum bitwidth for the processor. In certain implementations, the bitwidth may be determined based on the contents of the data 304. For example, the data 304 may be received in one of a plurality of predefined formats, and each of the predefined formats may be associated with a particular bitwidth. In additional or alternative implementations, the data 304 may include one or more predefined fields or headers that denote the bitwidth. In additional or alternative implementations, the processor 302 may employ pattern recognition to discern the number of significant bits used per data point and may determine the first bitwidth 310 based on the number of significant bits. In additional or alternative implementations, the sensors 330, 332 may be configured to signal the bitwidth 310 to the processor 302, such as through a register setting, control bit, or instruction received via a driver of the sensors 330, 332.

The processor 302 may be configured to determine a first operating mode for the processor 302 based on a first difference between the first bitwidth 310 and the predetermined bitwidth 308. The first operating mode may be selected to process data in the first bitwidth 310 while minimizing resource utilization. For example, the first operating mode may disable at least a subset of a plurality of bit registers 320, 322, 324 within the processor 302. In certain implementations, the bit registers 320, 322, 324 may be disable such that the bit registers 320, 322, 324 operate in the same bitwidth as the first bitwidth 310. For example, the subset of the bit registers 320, 322, 324 are disabled to zero out values for bits in positions greater than the first bitwidth 310. For example, where the maximum supported bitwidth is 18 bits (in positions indexed 0-17) and the received data has a 10-bit bitwidth, the registers 320, 322, 324 for bit positions 10-17 may be disabled.

The processor 302 may be configured to use clock gating to disable the bit registers 320, 322, 324. In clock gating, the clock signal that drives changes in the state of the bit registers may be selectively turned off for the registers associated with the disabled bit positions. The bit registers that match or fall within the bitwidth of the data remain active, continuing to process the meaningful data bits, while the excess registers are effectively set to a low-power state. For example, the processor 302 (such as the bitwidth component or another component) may dynamically configure clock signals for the bit registers based on the first bitwidth 310, such as by determining and issuing control signals that gate the clocks to the relevant portions of the circuitry.

In certain implementations, the first bitwidth 310 may be determined by a particular component of the processor 302 (such as a bitwidth determination component). In such instances, the determined bitwidth may be signaled to other components of the processor 302 (such as the processing components 314, 316, 318). In certain implementations, this signaling may be a specific indication of the first bitwidth 310, and the processing components 314, 316, 318 may determine and switch to the first operating mode based on the signaling. In additional or alternative implementations, the signaling may take the form of a modified clock signal that adjusts operation of the one or more components 314, 316, 318 to the first operating mode, as explained above.

As depicted, the processor 302 may include a variety of processing components tailored to perform specialized functions pertinent to receiving, handling, and/or processing received data. For example, where the data 304 is image data, the processing components may include an Analog-to-Digital Converter (ADC) block, a Bayer Filter Processor block, an Image Scaling block, a Noise Reduction block, a Color Correction Matrix (CCM) block, and the like. FIG. 3B depicts a processing component 350 according to one aspect of the present disclosure. The processing component 350 includes bit registers 352, 354, 358, 364 in different sizes. The processing component also includes an adder block 356, a gain block 360, and a multiplication block 362. The processing component 350 may be configured to receive two pixel values in the registers 352, 354, add the values together using the adder block 356, and store the resulting output in the register 358. The processing component 350 may then be determined to multiply the value in the register 358 by a gain value indicated by the gain block 360 (which may be a software interface (SWI) block that receives gain values from a programmable process) and may store the output in the register 364. The processing component 350 may support a maximum bitwidth of 18-bits (indexed from 0 to 17 in FIG. 3B). In the depicted example, however, the processing component 350 may have received 10-bit pixel values. Accordingly, bit positions 10-17 in the bit registers 352 have been disabled, leaving bit positions 0-9 in operation. To support the maximum possible output from the adder block 356, bit positions 11-18 have been disabled, leaving bit positions 0-10 in operation (such as because adding two 10-bit numbers may result in an 11-bit output). Bit positions 10-17 have also been disabled for the gain block, leaving bit positions 0-10 in operation. The bit register 364 is a 37-bit register, to support the maximum possible output from multiplying up to a 19-bit value from register 358 by up to an 18-bit value from the gain block 360. However, as bit positions 11-18 of register 358 and bit positions 10-17 of the gain block 360 have been disabled (leaving register 358 with 11 operational bits and block 360 with 10 operational bits), the bit positions 21-36 of the register 364 have been disabled, leaving bit positions 0-20 in operation to support up to a 21-bit output from the multiplication block 362 in the current operating mode.

Returning to FIG. 3A, in certain implementations, the processor 302 may be further configured to determine aligned first image data, and the output data 326 may be determined based on the aligned first image data 304. In certain implementations, the aligned first image data may be determined by performing least significant bit (LSB) alignment on the first image data 304. In additional or alternative implementations, the aligned first image data may be determined by performing most significant bit (MSB) alignment on the first image data 304. When data values are LSB aligned, the least significant bits of the data may be stored at the lower end of the storage unit. For example, an 8-bit number that is LSB aligned would be stored in bit positions 0-7 of a 10-bit register. When data values are LSB aligned, the least significant bits of the data may be stored at the higher end of the storage unit. For example, an 8-bit number that is MSB aligned would be stored in bit positions 3-10 of a 10-bit register. In certain implementations, performing LSB alignment may result in reduced power units, as corresponding portions of certain processing components (such as multiplication blocks) may be disabled for higher bit positions. In additional or alternative implementations, existing processor components may be typically configured to use MSB aligned data. In such instances, using MSB alignment may improve compatibility with existing components (such as existing SWI components).

The processor 302 may be configured to determine, by the processor 302 in the first operating mode, first output data 326 based on the first data 304. In certain implementations, the processor 302 may return to a default operating mode after determining the first output data. In additional or alternative implementations, the processor 302 may remain in the first operating mode until data is received that is in a bitwidth other than the first bitwidth 310. For example, the processor 302 may, after determining the first output data 326, receive second image data 306 from a second image sensor 102. The second image data 306 may have a second bitwidth 312 different from the first bitwidth 310. The processor 302 may be configured to determine that the second bitwidth 312 may be equal to the predetermined bitwidth 308 associated with the ISP. In certain implementations, determining a second operating mode for the ISP based on the determination that the second bitwidth 312 may be equal to the predetermined bitwidth 308. In certain implementations, determining, by the ISP in the second operating mode, second output data 326 based on the second image data 306.

For example, the processor 302 may receive and process one or more sets of first data 304 from the first sensor 330 and may subsequently receive one or more sets of second data 306 from the second sensor 332, and may switch to processing the second data 306 in the second operating mode. In certain implementations, the second image data 306 may be received as the next consecutive image frame after the first image data 304 within a stream of image frames received by the ISP. For example, the processor 302 may receive and process data from both sensors 330, 332 and may determine and process the data based on the bitwidths of the data using the techniques discussed above (such as in real time as the data is received). As one specific example, the sensors 330, 332 may be image sensors, and the processor 302 may receive and process image frames captured by the image sensors 330, 332 as they are captured. In certain implementations, the processor 302 may determine the bitwidths each time new data is received. In additional or alternative implementations, the processor 302 may track bitwidths for associated sensors. For example, the processor 302 may be configured to store (such as within an cache, register, and the like of the processor 302) (i) an indicator of the first bitwidth 310 in association with an identifier of the first sensor 330 and (ii) an indicator of the second bitwidth 312 in association with an identifier of the second sensor 332. In such implementations, the indicators may be stored for a predetermined period of time, for a predetermined amount of data received from the corresponding sensor, until data with a different bitwidth is received from the corresponding sensor, or combinations thereof.

FIG. 4 is a flow chart illustrating an example method 400 for bitwidth responsive processor operation according to one or more aspects of the present disclosure. The method may be performed by one or more of the above systems, such as the systems 100, 200, 300.

The method 400 includes receiving, at a processor, first data from a sensor, the first data has a first bitwidth (block 402). For example, the processor 302 may receive first data 304 from a sensor. In certain implementations, the processor 302 may be an ISP, the first sensor may be an image sensor 101, and the first data 304 may be image data. The first data 304 may have a first bitwidth 310, such as a first pixelwise bitwidth.

The method 400 includes determining that the first bitwidth is less than a predetermined bitwidth associated with the processor (block 404). For example, the processor 302 may determine that the first bitwidth 310 may be less than a predetermined bitwidth 308 associated with the processor 302. In certain implementations, the predetermined bitwidth 308 may be a maximum supported bitwidth of the processor 302.

The method 400 includes determining a first operating mode for the processor based on a first difference between the first bitwidth and the predetermined bitwidth (block 406). For example, the processor 302 may determine a first operating mode for the processor 302 based on a first difference between the first bitwidth 310 and the predetermined bitwidth 308. The first operating mode may disable at least a subset of a plurality of bit registers 320, 322, 324 within the processor 302, such as within one or more processing components 314, 316, 318 of the processor 302. In certain implementations, the subset of the bit registers 320, 322, 324 are disabled to zero out values for bits in positions greater than the first bitwidth 310. In certain implementations, the subset of the bit registers 320, 322, 324 are disabled using clock gating. In certain implementations, define clock gating. In certain implementations, the difference between the first bitwidth 310 and the maximum bitwidth may be determined by a dedicated module of the ISP and may be signaled to other components, such as processing components 314, 316, 318, of the processor 302 to adjust the operation of the subset of bit registers 320, 322, 324. In certain implementations, the method 400 may further include determining aligned first image data 304 by performing least significant bit (LSB) alignment on the first image data 304. In such instances, the output data 326 may be determined based on the aligned first image data 304.

The method 400 includes determining, by the processor in the first operating mode, first output data based on the first data (block 408). For example, the processor 302 may determine, in the first operating mode, first output data 326 based on the first data 304.

In certain implementations, the method 400 may further include receiving, at the processor 302, second data 306 from a second image sensor 102. The second data 306 may have a second bitwidth 312 different from the first bitwidth 310. For example, the method 400 may further include determining that the second bitwidth 312 is equal to the predetermined bitwidth 308 associated with the processor 302. In such instances, the method may also include determining a second operating mode for the processor based on the determination that the second bitwidth 312 is equal to the predetermined bitwidth 308. The method may additionally include determining, by the processor in the second operating mode, second output data 326 based on the second data 306. In certain implementations, the second data 306 may be received as the next consecutive image frame after the first data 304 within a stream of image frames received by the processor 302, such as when the processor 302 is an ISP and the data 304, 306 is image data. In certain implementations, the method 400 further includes storing, within the processor, (i) an indicator of the first bitwidth 310 in association with an identifier of the first image sensor 101 and (ii) an indicator of the second bitwidth 312 in association with an identifier of the second image sensor 102.

It is noted that one or more blocks (or operations) described with reference to FIG. 4 may be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks (or operations) of FIG. 4 may be combined with one or more blocks (or operations) of FIG. 1-3.

In one or more aspects, techniques for supporting vehicular operations may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein.

A first aspect provides a method that comprises receiving, at a processor, first data from a first sensor, wherein the first data has a first bitwidth; determining that the first bitwidth is less than a predetermined bitwidth associated with the processor; determining a first operating mode for the processor based on a difference between the first bitwidth and the predetermined bitwidth, wherein the first operating mode disables at least a subset of a plurality of bit registers within the processor; and determining, by the processor in the first operating mode, first output data based on the first data.

In a second aspect, in combination with the first aspect, the subset of the bit registers are disabled to zero out values for bits in positions greater than the first bitwidth.

In a third aspect, in combination with one or more of the first aspect through the second aspect, the subset of the bit registers are disabled using clock gating.

In a fourth aspect, in combination with one or more of the first aspect through the third aspect, the predetermined bitwidth is a maximum supported bitwidth of the processor.

In a fifth aspect, in combination with one or more of the first aspect through the fourth aspect, determining aligned first data is further comprised by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data.

In a sixth aspect, in combination with the fifth aspect, one or more software interface (SWI) components of the processor are configured to use LSB-aligned data.

In a seventh aspect, in combination with one or more of the first aspect through the sixth aspect, the difference between the first bitwidth and the predetermined bitwidth is determined by a first component of the processor and is signaled to other components of the processor to disable the subset of bit registers.

In an eighth aspect, in combination with one or more of the first aspect through the seventh aspect, the method further comprises receiving, at the processor, second data from a second sensor, wherein the second data has a second bitwidth different from the first bitwidth; determining that the second bitwidth is equal to the predetermined bitwidth associated with the processor; determining a second operating mode for the processor based on the determination that the second bitwidth is equal to the predetermined bitwidth; and determining, by the processor in the second operating mode, second output data based on the second data.

In a ninth aspect, in combination with the eighth aspect, the second data is received as a consecutive image frame after the first data within a stream of image frames received by the processor.

In a tenth aspect, in combination with one or more of the eighth aspect through the ninth aspect, the method further comprises storing, within the processor, (i) an indicator of the first bitwidth in association with an identifier of the first sensor and (ii) an indicator of the second bitwidth in association with an identifier of the second sensor.

In an eleventh aspect, in combination with one or more of the first aspect through the tenth aspect, the first data is image data, the first sensor is an image sensor, and the first bitwidth is a per-pixel bitwidth of the first data.

A twelfth aspect provides a device that comprises one or more sensors, including a first sensor; one or more processors, including a first processor configured to receive first data from the first sensor, wherein the first data has a first bitwidth; determine that the first bitwidth is less than a predetermined bitwidth associated with the first processor; determine a first operating mode for the processor based on a difference between the first bitwidth and the predetermined bitwidth, wherein the first operating mode disables at least a subset of a plurality of bit registers within the first processor; and determine, in the first operating mode, first output data based on the first data; and one or more memories configured to receive and store the first output data.

In a thirteenth aspect, in combination with the twelfth aspect, the subset of the bit registers are disabled to zero out values for bits in positions greater than the first bitwidth.

In a fourteenth aspect, in combination with one or more of the twelfth aspect through the thirteenth aspect, the subset of the bit registers are disabled using clock gating.

In a fifteenth aspect, in combination with one or more of the twelfth aspect through the fourteenth aspect, the predetermined bitwidth is a maximum supported bitwidth of the first processor.

In a sixteenth aspect, in combination with one or more of the twelfth aspect through the fifteenth aspect, the first processor is further configured to determine aligned first data by performing least significant bit (LSB) alignment on the first data, wherein the first output data is determined based on the aligned first data.

In a seventeenth aspect, in combination with the sixteenth aspect, one or more software interface (SWI) components of the processor are configured to use LSB-aligned data.

In an eighteenth aspect, in combination with one or more of the twelfth aspect through the seventeenth aspect, the difference between the first bitwidth and the predetermined bitwidth is determined by a first component of the first processor and is signaled to other components of the processor to disable the subset of bit registers.

In a nineteenth aspect, in combination with one or more of the twelfth aspect through the eighteenth aspect, the first data is image data, the first sensor is an image sensor, and the first bitwidth is a per-pixel bitwidth of the first data.

A twentieth aspect provides a system comprising a processor configured to receive first data from a first sensor, wherein the first data has a first bitwidth; determine that the first bitwidth is less than a predetermined bitwidth associated with the processor; determine a first operating mode based on a difference between the first bitwidth and the predetermined bitwidth, wherein the first operating mode disables at least a subset of a plurality of bit registers within the processor; and determine, in the first operating mode, first output data based on the first data.

In some implementations, the system includes a wireless device, such as a UE. In some implementations, the system may include at least one processor, and a memory coupled to the processor. The processor may be configured to perform operations described herein with respect to the apparatus. In some other implementations, the system may include a non-transitory computer-readable medium having program code recorded thereon and the program code may be executable by a computer for causing the computer to perform operations described herein with reference to the system. In some implementations, the system may include one or more means configured to perform operations described herein. In some implementations, a method of wireless communication may include one or more operations described herein with reference to the system.