120.

The delay circuit 140 converts only a phase of a high frequency component of the input inverted clock signal 122 into in-phase as the phase of the clock signal 121 by a delay function unique to the circuit. Then, a differential state of a direct current component of the inverted clock signal 122 with respect to a direct current component of the clock signal 121 is maintained between an input and an output of the delay circuit 140.

FIGS. 2 and 3 are diagrams illustrating a common mode rejection function of the differential amplifier 130. FIG. 2 illustrates an operation example in a case in which a differential signal of a relatively low frequency and an in-phase signal of a relatively high frequency are input to differential inputs Vin(+) and Vin(−) of the differential amplifier 130. At an output Vout of the differential amplifier 130, an amplitude of a high frequency signal being an in-phase signal is suppressed, but an amplitude of a differential signal having an opposite phase is added and increases. Specifically, the differential amplifier 130 has a common mode rejection characteristic in which a difference of a signal to be input is amplified, and an in-phase signal (e.g., common mode noise) is removed.

FIG. 3 illustrates an operation example in a case in which a frequency component of a clock signal as a high frequency component of a same phase, and a direct current component of the clock signal are input to the differential amplifier 130. In FIG. 3, GND denotes a position where a direct current component is zero. Further, in FIG. 3, an amplitude of a direct current component to be input to the Vin(+) side of the differential amplifier 130 is smaller than an amplitude of a direct current component to be input to the Vin(−) side. The differential amplifier 130 outputs a difference in amplitude between these direct current components from Vout. Further, high frequency components being in-phase input to the differential amplifier 130 is removed by a common mode rejection characteristic of the differential amplifier 130. Consequently, the differential amplifier 130 outputs a direct current signal in which ripple is suppressed. In the present example embodiment, the input 131 in FIG. 1 is associated with Vin(+) in FIG. 2, and the input 132 is associated with Vin(−).

In the duty ratio correction circuit 100 having a configuration as described above, it is possible to omit a low pass filter and an integral capacitor used in a general duty ratio correction circuit to extract a direct current component by removing a high frequency component, and remove ripple in a control voltage. Consequently, the duty ratio correction circuit 100 enables high-precision duty ratio correction of a clock signal, and high-speed stabilization of a duty ratio.

Note that, in the above example, it is preferable that a phase of a high frequency component to be input to the differential amplifier 130 completely becomes in-phase to sufficiently acquire an advantageous effect of a common mode rejection characteristic of the differential amplifier 130. However, even when a high frequency component does not have a completely same phase, a high frequency component suppressing effect is acquired by the duty ratio correction circuit 100, because an amplitude of an input signal to the differential amplifier 130 is output as a difference thereof due to a common mode rejection characteristic.

FIGS. 4 and 5 are diagrams illustrating an example of a change in waveform of the clock signal 121 and the inverted clock signal 141 to be input to the differential amplifier 130. In FIGS. 4 and 5, a waveform of the clock signal 121 and the inverted clock signal 141 to be input to the differential amplifier 130 changes from an upper waveform to a lower waveform as time elapses by feedback control by the duty ratio adjustment circuit 110. FIGS. 4 and 5 illustrate, as an example, a case in which a frequency of a clock signal is 1 GHz. Therefore, a cycle of a clock signal to be input and output in the differential amplifier 130 is 1 nanosecond (nsec), and a half cycle thereof is 0.5 nsec.

FIG. 4 illustrates an example in a case in which the duty ratio correction circuit 100 does not include the delay circuit 140. A solid line in FIG. 4 denotes the clock signal 121, and a dashed line in FIG. 4 denotes the inverted clock signal 122. In FIG. 4, the solid line and the dashed line overlap each other at a rising time and a falling time of a waveform. In FIG. 4, the clock signal 121 and the inverted clock signal 122 to be input to the differential amplifier 130 have a relationship in which phases are opposite to each other. In this case, since a high frequency component included in a rectangular wave becoming a cause of ripple is not in the same phase, the high frequency component is not suppressed in the differential amplifier 130 having a common mode rejection characteristic.

FIG. 5 illustrates an example in a case in which the duty ratio correction circuit 100 includes the delay circuit 140. A solid line in FIG. 5 denotes the clock signal 121, and a dashed line in FIG. 5 denotes the inverted clock signal 141. FIG. 5 illustrates a waveform example of the clock signal 121 and the inverted clock signal 141 to be input to the differential amplifier 130. The clock signal 121 and the inverted clock signal 141 to be input to the differential amplifier 130 have a relationship in which phases are the same by an operation of the delay circuit 140.

In FIG. 5, in a state in which a duty ratio converges to 50% by progress of feedback control, a high frequency component of each of a clock signal and an inverted clock signal is converted into an in-phase signal, and the in-phase signal is input to the differential amplifier 130. Then, the high frequency component included in a rectangular wave becoming a cause of ripple is suppressed by utilizing the above-described common mode rejection characteristic of the differential amplifier 130.

FIG. 6 is a diagram in which an example of a change in a control voltage in the duty ratio correction circuit 100 according to the present disclosure is appended to a graph in FIG. 21. As illustrated in FIG. 6, in the duty ratio correction circuit 100, a high frequency component included in the clock signal 121 and the inverted clock signal 141 is suppressed by the differential amplifier 130. Therefore, it is possible to omit an LPF and an integral capacitor being required in a general circuit, and achieve a state in which a control voltage has small ripple with a small time constant (specifically, in a short time). Consequently, the duty ratio correction circuit 100 enables high-precision duty ratio correction of a clock signal, and high-speed stabilization of a duty ratio.

Second Example Embodiment

[Configuration]

FIG. 7 is a diagram illustrating a configuration example of a duty ratio correction circuit 101 according to a present disclosure. The duty ratio correction circuit 101 includes a delay circuit 240, in place of the delay circuit 140 of the duty ratio correction circuit 100. FIG. 8 is a diagram illustrating a configuration example of the delay circuit 240. The delay circuit 240 includes an inverter group 241. In the inverter group 241, 2n inverters are connected in series. n is a natural number.

[Operation]

An inverted clock signal 122 is input to the delay circuit 240. Since the delay circuit 240 is constituted of even-numbered inverters, a logic and a direct current component of the input inverted clock signal 122 are output from the delay circuit 240, as an inverted clock signal 141 without being affected by the delay circuit 240. On the other hand, a high frequency component of the inverted clock signal 122 receives time delay associated to a half cycle of the inverted clock signal 122 by the delay circuit 240. The number of inverters included in the inverter group 241 is set in such a way that a high frequency component of the clock signal 121, and a high frequency component of the inverted clock signal 141 become an in-phase signal at an input of a differential amplifier 130 by delay by the delay circuit 240. In this way, the delay circuit 240 converts only a high frequency component of the inverted clock signal 141 into an in-phase signal, while maintaining a differential state of a direct current component with respect to the clock signal 121, and inputs the in-phase signal to the differential amplifier 130, as the inverted clock signal 122. The duty ratio correction circuit 101 including a configuration as described above also enables high-precision duty ratio correction of a clock signal, and high-speed stabilization of a duty ratio.

Third Example Embodiment

[Configuration]

FIG. 9 is a diagram illustrating a configuration example of a duty ratio correction circuit 102 according to a present disclosure. The duty ratio correction circuit 102 is different from the duty ratio correction circuit 100 in a point that the duty ratio correction circuit 102 includes a low pass filter (LPF) 301 and an integral capacitor 302. The LPF 301 suppresses a high frequency component of a clock signal 121 and an inverted clock signal 141. A cutoff frequency of the LPF 301 is higher than that of an LPF to be used in a general duty ratio correction circuit. The integral capacitor 302 is provided between an output of a differential amplifier 130, and a grounding point. A capacity of the integral capacitor 302 is smaller than that of an integral capacitor to be used in a general duty ratio correction circuit.

[Operation]

An output of the differential amplifier 130 may include a slight amount of a high frequency component that cannot be removed by a common mode rejection characteristic alone, and is derived from a rectangular wave of the clock signal 121 and the inverted clock signal 141. Then, a high frequency component as described above becomes a cause of slight ripple in a control voltage. The duty ratio correction circuit 102 according to the present disclosure suppresses a high frequency component as described above by using the LPF 301 and the integral capacitor 302. Since most of a high frequency component is removed by the differential amplifier 130, the LPF 301 can set a cutoff frequency to be high, as compared with an LPF to be used for ripple removal in a general duty ratio correction circuit. Further, in the duty ratio correction circuit 102, a capacity of the integral capacitor 302 can also be set to be small, as compared with a configuration to be used for ripple removal in a general duty ratio correction circuit. The duty ratio correction circuit 102 including a configuration as described above enables high-precision duty ratio correction of a clock signal, and high-speed stabilization of a duty ratio. Further, the duty ratio correction circuit 102 can further suppress ripple by using, as the LPF 301 and the integral capacitor 302, a compact component, as compared with a configuration to be used in a general duty ratio correction circuit.

Fourth Example Embodiment

[Configuration]

FIG. 10 is a diagram illustrating a configuration example of a duty ratio correction circuit 103 according to a present disclosure. The duty ratio correction circuit 103 is different from the duty ratio correction circuit 101 in a point that the duty ratio correction circuit 103 includes a delay circuit 340, in place of the delay circuit 240. The delay circuit 340 can switch the number of inverters for delaying an inverted clock signal.

[Operation]

The delay circuit 340 includes inverter groups 341 and 342. Both of the inverter groups 341 and 342 include a plurality of inverters, and the inverters are connected in series. A delay amount of the inverter group 341 is D1, and a delay amount of the inverter group 342 is D2. A switch 343 connects an output of an inverted clock signal 122 of an inverted signal generation circuit 120 to an input of the inverter group 341 or an input of the inverter group 342. A configuration as described above enables to change a delay amount of the delay circuit 340 by switching the switch 343. Specifically, a delay amount of the delay circuit 340 is set to either of the delay amount D1 of the inverter group 341, or D1+D2 being a sum of the delay amounts of the inverter groups 341 and 342. Switching connection of the inverter group (specifically, switching a delay amount) is performed, for example, by controlling the switch 343 according to a frequency of the inverted clock signal 122.

The delay circuits 240 and 340 are configuration examples of the delay circuit 140, and a constituent element of these delay circuits is not limited to an inverter. Specifically, the delay circuit 140 may utilize a delay amount unique to the circuit, and, for example, adjust a delay amount by switch control. At this occasion, it is preferable that only a high frequency component can be converted into an in-phase signal, while maintaining a differential state of a direct current component with respect to a clock signal having a different frequency. The delay circuits 240 and 340 include a plurality of inverters, as delay elements. Then, a delay amount of the delay circuits 240 and 340 is adjusted by switching the number of series connections of delay elements.

So far, the delay circuits 240 and 340 including an inverter group have been described. Next, an example of a determination procedure on the number of inverters included in an inverter group is described. The delay circuits 240 and 340 are configured in such a way that the input inverted clock signal 122 passes through even-numbered inverters, and is output as an inverted clock signal 141 to maintain a differential state of a direct current component. The number N of inverters necessary for converting a phase of a high frequency component of the inverted clock signal 141 to in-phase as a phase of a clock signal 121 is determined as follows. Note that, it is assumed that a duration of a half cycle of the inverted clock signal 122 to be input is T/2, and a delay time per inverter is d.

N
=

(

T
/
2

)

/
d

=

T
/

(

2
⁢
d

)

An even number closest to a value derived from the above equation becomes the number of inverters suitable for converting a high frequency component into an in-phase signal, while maintaining a differential state of a direct current component.

FIG. 11 is a diagram illustrating an example of a relationship between a clock frequency, and the number of inverters at the frequency. Since a cycle of a clock signal is different depending on a frequency of the clock signal, a delay amount required for a delay circuit also differs depending on a clock frequency. Referring to FIG. 11 enables to know the number of inverters according to a clock frequency. For example, when a clock signal having a clock frequency of 1 GHz is input to the duty ratio correction circuit 103, thirty-eight inverters as an inverter group are connected in series. When a clock signal having a clock frequency of 2 GHz is input to the duty ratio correction circuit 103, eighteen inverters as an inverter group are connected in series.

In this case, in the duty ratio correction circuit 103, the inverter group 341 may be constituted of eighteen inverters, and the inverter group 342 may be constituted of twenty inverters. When a frequency of a clock signal is 1 GHz, since delay associated to thirty-eight inverters is required, the switch 343 is switched in such a way that the inverted clock signal 122 passes through both of the inverter groups 341 and 342. When a frequency of a clock signal is 2 GHZ, since a delay amount is only required to be an amount associated to eighteen inverters, the switch 343 is switched in such a way that the inverted clock signal 122 passes only through the inverter group 341.

In this way, the duty ratio correction circuit 103 includes the switch 343, and two groups being the inverter groups 341 and 342. Thus, the duty ratio correction circuit 103 enables to perform duty ratio correction with respect to two types of clock signals having a different frequency by controlling the number of inverters of a delay circuit, specifically, a delay time, by controlling the switch 343. Further, the delay circuit 340 may be configured in such a way that an inverter group is further prepared, and a delay amount of three types or more can be set by a switch.

Switching of the switch 343 may be performed by a maintainer of equipment. Alternatively, the duty ratio correction circuit 103 may further include a frequency counter that measures a frequency of a clock signal to be input. The duty ratio correction circuit 103 may switch the switch 343 in such a way that a more preferred delay amount can be acquired according to a clock frequency measured by the frequency counter.

The duty ratio correction circuit 103 including a configuration as described above enables high-precision duty ratio correction of a clock signal, and high-speed stabilization of a duty ratio. Further, the duty ratio correction circuit 103 enables duty ratio correction with respect to a plurality of clock signals having a different frequency.

Fifth Example Embodiment

[Configuration]

FIG. 12 is a diagram illustrating a configuration example of a duty ratio correction circuit 10 according to a present disclosure. The duty ratio correction circuit 10 includes a duty ratio adjustment circuit 11, an inverted signal generation circuit 12, a differential amplifier 13, and a delay circuit 14.

[Operation]

The duty ratio adjustment circuit 11 adjusts a duty ratio of a first clock signal being an input clock signal, based on a control signal, and outputs, as a second clock signal, the first input clock signal in which the duty ratio is adjusted. The duty ratio adjustment circuit 11 is one example of a duty ratio adjustment means.

The second clock signal is input from the duty ratio adjustment circuit 11 to the inverted signal generation circuit 12. The inverted signal generation circuit 12 outputs an output clock signal having a phase of the second clock signal, and an inverted clock signal being a signal in which a phase of the output clock signal is inverted. The inverted signal generation circuit 12 is one example of an inverted signal generation means. Note that, the second clock signal may be input to the inverted signal generation circuit 12, and output to the delay circuit 14 without being inverted in the inverted signal generation circuit 12.

The delay circuit 14 has a delay amount causing a delay associated to a half cycle of an output clock signal between the output clock signal and an inverted clock signal. The delay circuit 14 is one example of a delay means. In other words, the delay circuit 14 causes a delay difference corresponding to a half cycle of a clock between two clock signals to be input to the differential amplifier 13. Note that, a function of the delay circuit 14 may be achieved by giving a delay only to either of an output clock signal and an inverted clock signal. Specifically, in this case, the other of the output clock signal and the inverted clock signal may be input as it is from the inverted signal generation circuit 12 to the differential amplifier 13.

The differential amplifier 13 outputs, as a control signal, a signal in which a difference in amplitude between the output clock signal and the inverted clock signal being output from the delay circuit 14 is amplified. The differential amplifier 13 is one example of a differential amplification means. The control signal output from the differential amplifier 13 is input to the duty ratio adjustment circuit 11.

In the duty ratio correction circuit 10, since a high frequency component of a clock signal to be input to the differential amplifier 13 becomes a same phase, a high frequency component is reduced at an output of the differential amplifier 13. Consequently, in the duty ratio adjustment circuit 11, an influence of ripple derived from a high frequency component is reduced in adjusting a duty ratio of a clock signal, based on a difference in direct current component. Further, in the duty ratio correction circuit