and 46 may be omitted since they are interconnects for reinforcing the power supply.

Above the output transistor P1 and the ESD protection diode 1b, M3 interconnects 53 and M4 interconnects 75 are formed in a lattice pattern as interconnects supplying VDDIO. The M3 interconnects 53 and the M4 interconnects 75 are mutually connected through vias. The M4 interconnects 75 have overlaps at positions in the X direction with the resistor elements RU. In other words, the M4 interconnects 75 supplying VDDIO are formed at positions in the X coordinate at which the resistor elements RU are formed.

Note that some of the resistor elements RU constituting the protective resistance Rsp may lie above the output transistor P1 or above the ESD protection diode 1b.

FIG. 6 shows a layout of the output transistor P1, which includes a plurality of p-type fins 66 extending in the X direction, arranged in order in the Y direction, and a plurality of gate interconnects 67 extending in the Y direction, arranged in order in the X direction. The fins 66 and the gate interconnects 67 overlapping in planar view form transistors. The transistors are mutually connected in parallel through interconnects not shown. The drains of the transistors are connected to the external output terminal PAD through the protective resistance Rsp.

FIG. 7 shows a layout of the ESD protection diode 1b, which includes a cathode part 36 formed of n-type fins 37 and anode parts 38a and 38b formed of p-type fins 39a and 39b, respectively. The fins 37, 39a, and 39b extend in the X direction. The cathode part 36 is connected to VDDIO, and the anode parts 38a and 38b are connected to the external output terminal PAD. Diodes are formed between the n-type fins 37 and the p-type fins 39a and 39b.

FIG. 8 is a plan view showing the structure of the M3 to M5 interconnect layers in part A2 of FIG. 3, showing a layout of a sector where the protective resistance Rsn is formed and sectors above the output transistor N1 and the ESD protection diode 1a. The layout of FIG. 8 corresponds to the vertically inverted one of the layout of FIG. 4 with VDDIO changed to VSS and the node B changed to the node A. Since the layout of FIG. 8 is easily understandable from the description on the layout of FIG. 4, detailed description thereof is omitted here.

The resistor elements RU are formed in the RMetal interconnect layer. Each two of the resistor elements RU are connected in series between the external output terminal PAD and the node A. The protective resistance Rsn is constituted by a plurality of such resistor elements RU.

Above the output transistor N1 and the ESD protection diode 1a, M3 interconnects 54 and M4 interconnects 76 are formed in a lattice pattern as interconnects supplying VSS. The M3 interconnects 54 and the M4 interconnects 76 are mutually connected through vias. The M4 interconnects 76 have overlaps at positions in the X direction with the resistor elements RU. In other words, the M4 interconnects 76 supplying VSS are formed at positions in the X coordinate at which the resistor elements RU are formed.

Note that some of the resistor elements RU constituting the protective resistance Rsn may lie above the output transistor N1 or above the ESD protection diode 1a.

FIG. 9 shows a layout of the output transistor N1. As shown in FIG. 9, the output transistor N1 includes a plurality of n-type fins 61 extending in the X direction, arranged in order in the Y direction, and a plurality of gate interconnects 62 extending in the Y direction, arranged in order in the X direction. The fins 61 and the gate interconnects 62 overlapping in planar view form transistors. The transistors are mutually connected in parallel through interconnects not shown. The drains of the transistors are connected to the external output terminal PAD through the protective resistance Rsn.

FIG. 10 shows a layout of the ESD protection diode 1a. As shown in FIG. 10, the ESD protection diode 1a includes an anode part 31 formed of p-type fins 32 and cathode parts 33a and 33b formed of n-type fins 34a and 34b, respectively. The fins 32, 34a, and 34b extend in the X direction. The anode part 31 is connected to VSS, and the cathode parts 33a and 33b are connected to the external output terminal PAD. Diodes are formed between the p-type fins 32 and the n-type fins 34a and 34b.

According to this embodiment, advantages as follows are obtained. That is, in the configuration of this embodiment, the resistor elements RU constituting the protective resistances Rsp and Rsn are placed above sectors other than the sectors where the output transistors P1 and N1 and the ESD protection diodes 1a and 1b are placed. With this, power supply lines for VDDIO and VSS can be provided abundantly in the interconnect layers above the output transistors P1 and N1 and the ESD protection diodes 1a and 1b.

With the above configuration, for the output transistors P1 and N1, a large current can be sufficiently passed through the transistors. Therefore, since the interconnect resistance decreases to prevent or reduce the voltage drop, the operating frequency is prevented from degrading and the quality of the signal waveform is improved. For the ESD protection diodes 1a and 1b, since the resistance values of the routes from the power supply to the diodes can be reduced, good ESD protection characteristics can be obtained.

Second Embodiment

FIG. 11 is a circuit configuration diagram of an output circuit 12 according to this embodiment. The circuit configuration of FIG. 11 is similar to the circuit configuration of FIG. 2 in the first embodiment, except for the position of insertion of a protective resistance. That is, in the output circuit 12 of FIG. 11, a protective resistance Rs is provided in place of the protective resistances Rsn and Rsp in FIG. 2. In FIG. 11, the drains of the output transistors P1 and N1 are mutually connected, and the protective resistance Rs is provided between the external output terminal PAD and the drains of the output transistors P1 and N1. Note that the node between the drains of the output transistors P